JPS6292364A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the characteristics of a photoconductive film by connecting two conductive layers holding an insulating layer with conductor as the surface of the conductive layer arranged to an upper section is left as it is flattened. CONSTITUTION:A photodiode 2 consisting of a p-layer 20 and an n-layer 22 laminated onto a MOS scanning circuit substrate 1 stores photo-charges corresponding to incident beams. Foundation electrodes 24 are arranged at intervals between the n-layer 22 and the substrate 1, and the base electrodes 24 are electrodes at every photosensitive cell for the photodiode 2 composed of the p-layer 20 and the n-layer 22. A transparent electrode layer 26 is lamianted on the upper surface of the p-lyer 20, and shielding layers 28 for shielding light are laminated mutually at intervals on the upper surface of the layer 26. Two n<+> regions 12 and 14 are shaped to one main surface of a p-type silicon substrate 10 in the MOS scanning circuit substrate 1. A gate electrode 18 is disposed on the surface of the substrate between both regions. The incidence of beams reflected by the surfaces of the adjacent base electrodes 24 and adjacent insulating layers 150 can be prevented by flattening the base electrodes 24, thus improving picture quality.

Description

Detailed Description of the Invention Technical Field The present invention relates to a semiconductor device, and in particular to a stacked solid-state imaging device in which a photoconductive film is formed on a semiconductor substrate having a charge storage and transfer function or a matrix-like MOS switching function. The present invention relates to applied semiconductor devices.

Background technology Solid-state imaging devices using semiconductors are becoming increasingly high-density, high-performance, and multifunctional, and are integrating pixel groups with photoelectric conversion and signal storage functions, switching circuits with scanning functions, color filters, etc. There is an increasing demand for the development of stacked solid-state imaging devices. However, when increasing the density of an element, the vertical dimension of the element, that is, the film thickness direction, cannot be made extremely thin due to the breakdown voltage of the insulating film and the specific resistance of the conductor film, etc., and the resolution in the horizontal direction cannot be made extremely thin. As a result of advances in photolithography technology and processing technology, miniaturization continues to advance, and the unevenness of the element surface tends to become steeper.

Therefore, in order to send the charges generated in the photoconductive film of the solid-state imaging device from the base electrode to the source region of the silicon substrate, a contact hole is provided directly in the insulating film above the source region, and the base electrode is inserted through this hole. When brought into contact with the source region, the steep step of the contact hole causes unevenness on the surface of the base electrode, which deteriorates the characteristics of the photoconductive film on the base electrode, increases dark current, and reduces the image quality. Resolution deteriorates.

Therefore, by drawing out the polycrystalline silicon film in contact with the source region onto a flat gate electrode and bringing this polycrystalline silicon film into contact with the underlying electrode, we will eliminate the unevenness on the surface of the underlying electrode and improve the characteristics of the photoconductive film. There is something like that. In this case, in order to make the surface of the substrate on which the base electrode is placed as flat as possible, silicate glass containing phosphorus (PSG) is used.
) By using a membrane and causing it to flow at high temperatures, the shape of the uneven parts is flattened. When etching this PSG film, it is necessary to increase the etching speed, increase the amount of side etching with respect to the mask, and increase the area of the polycrystalline silicon film for electrode extraction in order to provide margin for processing. There is.

In addition, due to the characteristics of the photoconductive film, the polycrystalline silicon film should be drawn out to the flat part above the gate electrode, avoiding directly above the source region with steep steps, and connected to the base electrode here, and the polycrystalline silicon film The film must completely cover the opening in the insulating film directly above the source region, and if the mask alignment is even slightly misaligned, the source region containing many impurities will be etched at the same time during the etching process of the polycrystalline silicon film for electrode extraction. There is a risk that

If a polycrystalline silicon film for electrode extraction is formed above the gate electrode with the above considerations in mind, a large capacitor will be formed between the gate electrode and the silicon oxide film, resulting in a large stray capacitance. Become. This is particularly noticeable in solid-state imaging devices because dozens of elements are arranged in an XY matrix on the blade side. Furthermore, since the polycrystalline silicon film for taking out the electrode is located on the gate electrode, there is a risk of short-circuiting with the gate electrode.

In addition, in a semiconductor device other than an integrated image pickup device as described in 2 above, when connecting two conductive layers with an insulating layer in between, the upper conductive layer is convex toward the lower conductive layer. It was connected by bending it like this. Therefore, the wire was easily broken at the bent portion, and the microprocessability was also low. Furthermore, since the formation temperature of polycrystalline silicon is as high as 800-11150° C., it has the disadvantage that it cannot be used in the process after AI wiring.

Purpose The present invention solves the drawbacks of the prior art, and provides a semiconductor device in which two conductive layers sandwiching an insulating layer are connected by a conductor while keeping the surface of the upper conductive layer flat. The purpose is to provide a manufacturing method thereof.

Another object of the present invention is to provide a stacked solid-state imaging device and a method for manufacturing the same, in which the characteristics of the photoconductive film are improved and there is no fear that the conductive film connecting the underlying electrode and the diode region will short-circuit with the gate electrode. be.

DISCLOSURE OF THE INVENTION According to the present invention, a first conductive layer, an insulating layer laminated on the first conductive layer, and an insulating layer laminated on the second conductive layer, a part of which is connected to the first conductive layer. In a semiconductor device having a second conductive layer on one main surface of the substrate, the insulating layer has an opening, and the first conductive layer and the second conductive layer are connected in the opening. The upper surface of the amorphous semiconductor is formed to be flat.

This semiconductor device is manufactured by the following method.

That is, this method includes the steps of forming a first conductive layer on the surface of a semiconductor substrate, forming an insulating layer on the first conductive layer,
The process of smoothing the surface and the smoothed insulating layer,
A step of forming a vertical opening reaching the upper surface of the first conductive layer, a step of forming an electrode made of an amorphous semiconductor in the opening and smoothing its surface, and a step of forming a vertical opening that reaches the upper surface of the first conductive layer, and a step of forming an electrode made of an amorphous semiconductor in the opening and smoothing the surface thereof. and a step of forming a conductive layer of 200 to 200.
It has the characteristic that a very low process temperature of 300°C can be used.

DESCRIPTION OF THE EMBODIMENTS Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a cross-sectional structure of an embodiment of a solid-state imaging device to which the present invention is applied.

Two layers 20 and 9 stacked on MO9 scanning circuit board 1
The photodiode 2 composed of the layer 22 accumulates photocharges corresponding to incident light. A base type wA 24 is arranged at intervals between the 9-layer 22 and the MO8 scanning circuit board 1, and this base electrode 24 is an electrode for each photosensitive cell of the photodiode 2 consisting of the 2-layer 20 and the 9-layer 22. be. 2
A transparent electrode layer 28 is laminated on the upper surface of the layer 20, and a light shielding shield layer 28 is laminated on the upper surface of the transparent electrode layer 2B at intervals.

The second layer 20 is formed of an amorphous p-type semiconductor doped with boron, such as a-9iH or a-GeSiH.

9 layer 22 is a non-doped amorphous n-type semiconductor, for example, a-
9iH, formed from a-GeSiH.

In addition, p ffj 2 Q and pn consisting of 9 layers 22
In place of the junction photodiode 2, a pi junction or p
It may be an in-junction photodiode or a photoconductive layer.

The transparent electrode layer 2B is made of ITO, In2O3, 5n02, or the like. The shield layer 28 is made of AI, Al-
3i-Cu, Al-3i, Cr, Ti, No,
It is formed of metal such as W, and is used to separate each pixel, so it can be omitted.

The MO9 scanning circuit board l has two n+ regions 12 and 14 formed on one main surface of a p-type silicon substrate lO. A gate electrode 18 is provided on the substrate surface between the two n+ regions 12 and 14 with a gate oxide film 1B interposed therebetween. Gate electrode 18 is advantageously made of polycrystalline silicon.

These two n+ regions 12 and 14, gate oxide film 1
6 and the gate electrode 18 form a MOS transistor or FET 100. In this example, it is an n-channel FET, with the n+ region 12 functioning as a source and the n+ region 14 functioning as a drain.

A source electrode 120 is connected to the n+ region 12, and the source electrode 120 is connected to the base electrode 24.

Furthermore, an insulating layer 110 of S s 02 is formed on the portion of the silicon substrate 10 where the n+ region 12.14 and the gate electrode 18 are not formed. A PSG insulating layer 130 is formed thereon, and a readout electrode 18 of A1 is formed from the drain 14. An insulating layer 150 made of PSG, 5I02, or organic polyimide is formed on the insulating layer 130 and the readout electrode 19 so that its upper surface is flat.

The source electrode 120 is buried in the openings of the insulating layers 130 and 150 perpendicularly to the surface of the n+ region 12, and its surface is flattened and brought into contact with the base electrode 24.

The source electrode 120 is made of an amorphous semiconductor a-SiH with P and
It is doped with impurities such as As to make it an n-type semiconductor.
It exhibits conductivity and has a specific resistance ρ of 10 −2 to 10 3 Ωcm.

Next, the operation of the solid-state imaging device of this embodiment will be explained.

When light enters the photodiodes 2 of each pixel portion separated by the shield layer 28 through the transparent electrode layer 26, a photocharge is generated in each photodiode 2 according to the amount of incident light. When a readout signal from a shift register (not shown) is applied to a selected gate electrode 18, the selected FET becomes conductive, and a signal charge corresponding to the photocharge accumulated in the photodiode 2 is transferred to the base electrode. 24, the signal passes through the source voltage 8i 120 and the FET 100 and is transferred to the n+ region 14.

The signal charge transferred to the n+ region 14 is the readout voltage Jji
19 perpendicularly to the plane of the paper of FIG.

In this embodiment, the source electrode 120 is avoided from directly above the gate electrode 18 and is connected to the photodiode 2 by the shortest distance, so that the stray capacitance generated between the source electrode 120 and the gate electrode 18 is reduced.

That is, conventionally, as shown in FIG.
is brought out above the gate electrode 18 and in contact with the base electrode 24, so that the source electrode 120 and the gate electrode 18
A large capacitance capacitor is formed through the insulating layer 130 in between, and the stray capacitance becomes large.

In addition, the source electrode 120 tends to remain in the concave portion due to the irregularities formed by the gate electrode I8, resulting in a short circuit between the patterns, or because it is located on the gate electrode 18, it is liable to short circuit with the gate electrode 18.

On the other hand, in this embodiment, the source voltage 5i1 is
20 is connected to the photodiode 2 at the shortest possible distance, avoiding directly above the gate electrode 18. This reduces the stray capacitance that occurs between the gate electrode 18 and prevents short circuits between the patterns and the gate electrode 18. There's nothing to do. Further, the upper surface of the source electrode 120 is flattened to form the base electrode 24.
Since the photodiode 2 is brought into contact with the photodiode 2, it is possible to reduce the unevenness of the 9th layer 20 and the 8th layer 22, thereby improving the characteristics such as improving the resolution of the photodiode 2.

Furthermore, by flattening the base electrode 24, the adjacent base electrode 24
Since the incident of light reflected on the surface of the adjacent insulating layer 150 can be prevented, the signal-to-noise ratio is improved and the image quality is improved.

Furthermore, since the device of this embodiment uses an amorphous semiconductor to form the photodiode, unlike a single crystal, it is easy to manufacture and inexpensive, and it is also easy to manufacture a large-area sensor.

FIG. 3 shows an example of the manufacturing process of the solid-state imaging device shown in FIG. 1.

First, as shown in FIG. 3(a), for example, a p-type resistivity of 1
For example, LOGO9 (Local Oxidation of
A protective oxide film 1θ0 for 0-order ion implantation, which is selectively formed to a thickness of about 0.8 pm using the 5ilicon) method, is
．． 051Lm is formed, and phosphorus ions are implanted into desired positions using a resist mask (not shown) to form n+ regions 12 and 14.

Next, as shown in FIG. 3(b), the protective oxide film 180 is removed, and the gate oxide film 16 is approximately 0.0. It is formed to a thickness of ip, rn. As the gate oxide film 16, a plurality of insulating films such as a silicon oxide film and a silicon nitride film may be used. Next, a gate electrode 18 of a polycrystalline silicon film is formed to a thickness of about 0.5 pm, and made into an n-type film by ion implantation or thermal diffusion.

Next, using a resist mask (not shown), the gate electrode 8i of the polycrystalline silicon film is selectively etched by dry etching.
18, and then the gate oxide film 16 is etched by a wet etching method to expose the n small region 12. Note that the n small region 1 exposed in this step
An n-type impurity may be newly implanted into 2.

Next, as shown in FIG. 3(C), PS is applied to the entire surface of the substrate 10.
Insulating layer 130 of G (silicate glass containing phosphorus)
is formed to a thickness of about 0.81 Lm. Furthermore, PSG is made to flow in a high temperature atmosphere to smooth out steep steps on the substrate surface as much as possible. In this case, smoothing is facilitated by performing it in wet oxygen or high pressure oxygen. Next, a contact hole for the AI readout electrode 18 is opened to form the readout electrode 18, and an insulating layer 150 made of PSG, 5I02, organic polyimide, or the like is formed.

Next, as shown in FIG. 3(d), the PSG insulating layer 130 and the PSG insulating layer 150 are selectively removed using a resist mask (not shown) until the surface of the n small region 12 is exposed.
is etched to form an opening 180.

The opening 180 is formed by a method in which, for example, a parallel 41-plate electric field is applied perpendicularly to the sample using a dry etching method. Use an etching gas with a high etching rate to make the etched cross section as steep as possible, as shown in the figure. By this step and the step of flowing the PSG insulating layer 150, the source electrode 12 made of amorphous SiH in the next step
It facilitates the embedding of 0 into the four parts.

After forming the steep opening 180 in this way, a source electrode 120 made of amorphous SiH is formed to have a thickness equal to or slightly thicker than the depth of the opening 180 on the n+ region 12, for example, about 2 gm. . The source electrode 120 made of n-type amorphous b SiH is formed by a plasma CVD method using a glow discharge decomposition method. S
+Ha gas and PH3 gas as a doping gas for n-type are decomposed by AC discharge or high-frequency discharge, and the decomposed gas atmosphere creates a source electrode made of n-type amorphous SiH (n+ a-SiH) containing phosphorus. form. In this case, for example, a parallel plate capacitive coupling type glow discharge decomposition device is used, the substrate temperature is 200 to 300°C, the pressure Q is l-1.0 Torr, and the power density per unit electrode area is 0.01 to 0.1 W/. Perform in C2.

Next, a resin-based organic material, such as a resist 180, is formed on the substrate surface by spin coating, and the surface is smoothed. In particular, after the resist 190 is applied, its surface becomes flat with almost no steps. At this time, the resist is coated in a single layer or in multiple coats until a flat surface is obtained.

Next, when the resist 180 is etched with oxygen gas using a dry etching method, for example, using a parallel plate dry etching device, the etching is gradually performed from the surface. The resist on the top is thin, and the resist on the recess is thick, so that the resist 190 can be left in self-alignment in the four parts of the n small region 12'', which is the deepest recess on the substrate surface, as shown in the figure. In this case, as shown in the figure, the surface of the resist 190 and the exposed source electrode 1 made of amorphous SiH
It is desirable that the 20 flat area surfaces coincide.

Next, as shown in FIG. 3(e), freon etching is performed by RIE (reactive, ion, etching) or plasma etching under conditions such that the etching rate of the resist 1=190 and the exposed source electrode 120 are the same. system gas and oxygen gas, e.g. 02F6+02, C2F
4+02, amorphous Si exposed using CF4+02
When the source electrode 120 made of H is etched, the resist (190) and the source electrode 120 are etched from the entire surface of the substrate.
is etched uniformly in the same way, so the structure of the etched cross section as shown in the figure is that of the insulating layer 13 made of PSG.
Source molar poles 120 made of amorphous SiH are embedded in the openings 180 of 0 and 150 in a self-aligned manner, and the substrate surface has a flat structure. The source electrode 120 made of amorphous SiH contains n-type impurities and has conductivity.

Note that in the step of FIG. 3(d), the resist 190
The resist 190 was left only on four parts of the substrate surface in a self-aligned manner, but this resist 190 was applied to the entire substrate without being etched, and as described above, the resist 190 and the amorphous S
The structure shown in FIG. 3(e) may be obtained by etching the source electrode 120 made of iH from the substrate surface under etching conditions with the same etching rate.

Next, as shown in FIG. 3 CF), A1. Al-5i-
A base electrode 24 is formed by depositing a metal film such as Cu, Cr, Ti, No, W, or the like. Next, the base electrode 24 and the PSG insulating layer 150 are coated with a-3iH or a-3iH or
Form eight layers 22 of -3iGeH.

In the case of glow discharge decomposition method, S r Ha, G
e Ha gas is decomposed by AC discharge or high frequency discharge, and eight layers 22 are formed on the MO8 scanning circuit board 1 by vapor phase growth using the decomposed gas atmosphere. In this case, for example, a parallel plate capacitive coupling type glow discharge decomposition device is used, and the second test is carried out at a pressure of 0.1 to 1.0 Torr and a power density of 0.01 to 0.1 W/c per unit electrode area.

Ge, Si or Ge-3 when using sputtering method
Eight layers 22 are formed on the MO9 scanning circuit board l by sputtering by discharging the target i with Ar-H2 gas. In either method, the substrate temperature of the MO3 scanning circuit board 1 is 150-300°C, and the thickness of the eight layers 22 is, for example, 0.5-2. Let OIi,m.

After forming the eight layers 22 on the MO3 scanning circuit board 1 and the base electrode 24 in this way, a-SiH or a
- Form two layers 20 of 3iGeH.

In the case of glow discharge decomposition method, SiH4, Ge
Ha gas and B2H6 gas as a doping gas for forming nine layers are decomposed by AC discharge or high frequency discharge, and eight layers 22-L are vapor-phase grown in the atmosphere of the decomposed gas to form pH2Q. In this case, for example, a parallel plate capacitively coupled glow discharge decomposition device is used, and a pressure of 0.1
~1. OTorr, power density per unit electrode area 0.0
Perform at 1 to 0.1 W/c 2.

Moreover, when the second layer 20 is made of a-GeSiH, S
Gas flow rate ratio of r Ha gas and G e H4 gas GeH4
/SiH4+ GeH4 may be set to 0.2 to 0.9.

When using the sputtering method, similarly to the formation of nfi22,
Ge, Si or Ge-5i targets are Ar
- N layer 22 is sputtered by discharging with H2 gas.
Two layers 20 are formed on top. The thickness of the second layer 20 is, for example, 0.
01-0・IILm.

Next, a transparent electrode layer 28 is formed using ITO, In2O3, 5n02, etc., and then AI, Al-5i-Cu,
A solid-state imaging device is manufactured by forming the optical shield layer 28 from a metal such as Al-3i, Cr, Ti, No, or W.

According to such a manufacturing method, the opening 180 is formed on the n÷ region 12 almost perpendicularly to the substrate, and the opening 180 is
It is possible to embed an amorphous film in 80 in a self-aligned manner and to flatten the surface.

Moreover, since amorphous SiH is used as the source electrode,
The temperature of the substrate may be 200 to 300° C., and there is no need to raise the temperature to 600 to 700° C. unlike when polysilicon is used, and it is easy to make the surface of the electrode v-carrying.

FIGS. 4(a) and 4(b) show other embodiments of the present invention.

A conductive layer 30 is formed on one main surface of the semiconductor substrate 10, an insulating layer 40 is formed on the conductive layer 30, and a conductive layer 50 is formed on the insulating layer 40. The conductive layer 30 and the conductive layer 50 are wirings made of metal such as AI, Al-9i, Al-3i-Cu. A through hole 42 is provided in the insulating layer 40, and this through hole 42 is filled with amorphous SiH to form a connection electrode 44. Phosphorus or arsenic is introduced into the amorphous SiH to make it small and its surface is flat.

The method for forming the through hole 42 in such a device, the method for forming the amorphous SiH filled in the through hole 42, and the method for flattening the surface of the amorphous SiH are the same as those in the method for manufacturing the solid-state imaging device described above. The same is true.

According to this embodiment, since the surface of the amorphous SiH filled in the through hole 42 is flat, the conductive layer 50 can be formed in a planar shape without unevenness. In the conventional device, as shown in FIG. 5, the upper electrode 52 is bent so as to contact the lower electrode 32, which tends to cause wire breakage at the bent portion 54, and because it is not flat, minute It was difficult to form a pattern. On the other hand, according to this embodiment, the -L plane of the conductive layer 44 is formed flat and has no unevenness, so the conductive layer 50 has few disconnections and has good microfabrication properties.

Effects According to the present invention, when connecting two conductive layers with an insulating layer sandwiched between them, the connection can be made with a conductor while keeping the surface of the upper conductive layer flat, which prevents disconnection from occurring. There is no risk and the micro-processability is also good.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of a solid-state imaging device to which the present invention is applied, FIG. 2 is a sectional view of a conventional solid-state imaging device, and FIGS.
(f) is a sectional view showing one embodiment of the manufacturing process of the solid-state imaging device shown in FIG. 1, FIG. 4(a) is a perspective view of another embodiment of the present invention, and FIG.
b) is a sectional view taken along line BB in FIG. 4(a), and FIG. 5 is a sectional view of a conventional semiconductor □ device. Explanation of symbols of main parts 10, substrate 12.14. n middle region 1B, . . . gate oxide film 18, . . gate electrode ill, . . . readout electrode 20, . . P layer 22, . . n layer 24.8. Base electrode 2Ei, . . . Transparent electrode 30, . Conductive layer 40, . . Insulating layer 44°1. Electrode 50 , Conductive layer 120 , Source electrode 130 , Insulating layer 150 , Insulating layer 180 , Protective oxide film 180 , Opening 190 , Resist patent applicant Fuji Photo Film Co., Ltd. Agent Katori Takao MaruyamaFigure 1Figure 2Tl(J 1(J(J jI3Figure

Claims (1)

[Claims] 1. a first conductive layer; an insulating layer laminated on the first conductive layer; and a portion of the insulating layer laminated on the insulating layer and connected to the first conductive layer. A semiconductor device having a second conductive layer on one main surface of the substrate, wherein the insulating layer has an opening, and the first conductive layer and the second conductive layer are arranged in the opening. A semiconductor device, characterized in that it is filled with an amorphous semiconductor that connects the second conductive layer, and that the amorphous semiconductor has a flat upper surface. 2. The device according to claim 1, wherein the device is a solid-state imaging device, and the second conductive layer is a readout base for a photosensitive means that generates and accumulates charges according to incident light. A semiconductor device, wherein the first conductive layer is an electrode, and the first conductive layer is an impurity-introduced region of a signal readout means for reading out a signal current corresponding to the charge from the photosensitive means. 3. In the device according to claim 2, the photosensitive means comprises the base electrode, a photosensitive layer formed on the base electrode, and a transparent electrode formed on the photosensitive layer. A semiconductor device characterized by: 4. The device according to claim 2, wherein the signal readout means is formed on two impurity-doped regions formed on one main surface of a semiconductor substrate, and above the two impurity-doped regions. 1. A semiconductor device comprising an insulating layer and a gate electrode formed on the insulating layer, wherein one of the two impurity doped regions is an impurity doped region of the signal reading means. 5. forming a first conductive layer on the surface of the semiconductor substrate; forming an insulating layer on the first conductive layer and smoothing the surface; and on the smoothed insulating layer, forming a vertical opening reaching the upper surface of the first conductive layer; forming an electrode made of an amorphous semiconductor in the opening and smoothing the surface thereof; forming a contacting second conductive layer. 6. The method according to claim 5, which is a method for manufacturing a solid-state imaging device, and the step of forming the first conductive layer includes forming an insulating film on the surface of a semiconductor substrate of one conductivity type. the step of selectively forming an impurity-introduced region by introducing impurities through the insulating layer; and the step of selectively forming a gate insulating film and a gate electrode on the substrate by removing the insulating film; The step of forming an insulating layer covering the substrate and the gate electrode is the step of forming an insulating layer that covers the substrate and the gate electrode, and the step of forming an opening portion is a step of forming an upper surface of one of the impurity-introduced regions in the smoothed insulating layer. The step of forming the second conductive layer is the step of forming a base electrode for each pixel, and the process further includes forming a photosensitive layer and a transparent electrode on the base electrode. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device.