EP0309542A1 - Charge-coupled device with dual layer electrodes - Google Patents
Charge-coupled device with dual layer electrodesInfo
- Publication number
- EP0309542A1 EP0309542A1 EP19880903574 EP88903574A EP0309542A1 EP 0309542 A1 EP0309542 A1 EP 0309542A1 EP 19880903574 EP19880903574 EP 19880903574 EP 88903574 A EP88903574 A EP 88903574A EP 0309542 A1 EP0309542 A1 EP 0309542A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- silicide
- layer
- electrodes
- gate electrodes
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000002355 dual-layer Substances 0.000 title claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 241000283986 Lepus Species 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42396—Gate electrodes for field effect devices for charge coupled devices
Definitions
- the present invention relates to charge coupled devices (CCDs) and more particularly to interline transfer CCDs.
- Interline transfer CCDs are used in imaging apparatus of the kind which comprises an array of photodetectors aligned in a plurality of rows each o which includes a plurality of photodetectors and in which the interline transfer CCDs are. interleaved between the rows of photodetectors.
- the currents detected by the individual photo ⁇ detectors in one row after integration in associate storage capacitors, are periodically transferred in parallel for storage as charges in individual cells of an adjacent interline transfer CCD and then such charges are read out serially from the CCD as currents into an output line for transmission to a utilization site.
- the interline transfer CCD itself be unaffected directly by the light used to excite the array of photocells and it is the usual practice to utilize a light shield over the CCD for this purpose, generally in the form of a layer of metal, deposited over the surface of the common silicon substrate in which have been formed the array of photodetectors and the interline transfer CCDs, and suitably patterned to permit light to reach the photodetectors but not to reach the critical gate electrode regions of the CCD.
- the gate electrodes typically are of doped polysilicon, which does not exhibit the desired opaqueness.
- a dual layer including a lower layer of doped polysilicon and an upper layer of silicide Such a dual layer will be referred to hereinafter as a polycide layer.
- tungsten silicide as the silicide has proven particularly advantageous, since it results in a polycide gate electrode which is both opaque and highly conductive.
- a silicide layer is uniformly deposited in turn over each of the two polysilicon layers usually deposited for forming the first—phase and second—phase set of gate electrodes, respectively, and the polysilicon and silicide layers are etched by reactive ion etching using a common mask to achieve automatic alignment of the two layers.
- the polycide process permits a high resistance oxide layer to be grown over the first—phase set of gate electrodes to provide electrical isolation from the overlapping second—phase set of gate electrodes.
- this invention is directed to a charge—coupled device using a two—phase gate electrode system having a first—phase set of gate electrodes interleaved with an overlapping second- phase set of gate electrodes in which both the first—phase set of electrodes and the second—phase set of electrodes are opaque and have a dual layer structure in which the lower layer is of polysilicon doped to be conductive and the upper layer is of an opaque silicide, and the two sets are separated by an isolation oxide grown from the silicide.
- FIG. 1 shows a section taken longitudinally along the channel region of one stage of a CCD which includes polycide first—phase and second—phase gate electrodes in accordance with the invention.
- the silicon wafer 10 whose bulk is p—type, includes at its upper surface a buried channel in which the signal charge transfer will be localized. This channel is formed by the implanta ⁇ tion of donor ions, represented schematically by the upper row of + signs 12.
- a silicon oxide layer 13 overlies the channel at the upper surface of the wafer. Overlying the oxide layer are the gate electrodes including the first—phase set of elec ⁇ trodes 1 of which only two are shown. Overlapping the first—phase set of electrodes is the second—phase set of electrodes 16, of which only one is shown.
- a clock source (not shown) will be connected between the two sets of electrodes to apply a voltage difference therebetween which varies periodically to transfer the signal packet of charges between successive potential wells in the buried channel set up by the two sets of gate electrodes.
- additional donor ions are impla'nted asymmetrically under each gate electrode, as shown denoted by the lower row + signs 18.
- this CCD is conventional.
- both sets of electrodes 1 and 16 include two layers.
- the lower layer 14A, 16A which contacts the gate oxide layer 13 is of polysilicon doped to be of low resistivity and is several thousand Angstroms thick, for example, about 3000 Angstroms thick. This layer is important because polysilicon is uniquely suited for serving as the control metal to the silicon oxide gate insulation.
- the upper level 14B, 16B is of a silicide, advantageously tungsten silicide of sufficient thickness to be opaque to ambient light and to have low resistance. A thickness of several thousand Angstroms, for example, 3000, is suffi ⁇ cient.
- a silicon oxide layer 20 provides electrical isolation between electrodes 14 and 16 in the regions of overlap.
- a preferred technique involves first depositing non—selectively a uniform layer of polysilicon of appropriate doping and thickness in conventional fashion, for example, chemical vapor deposition, and then sputter deposit ⁇ ing thereover non—selectively a layer of tungsten silicide of appropriate thickness, using a tungsten silicide source.
- the resulting two—layer structure is then masked in the pattern desired and plasma etched anisotropically to provide the desired substantially vertical side walls to the two—layer structure.
- the wafer before depositing the dual layer structure for use in forming the second—phase set of electrodes, the wafer is heated in an oxidizing ambient to grow a silicon oxide layer over the surface of the first—phase set of sufficient thickness to provide the desired isolation, for example, about a thousand Angstroms thick. After such growth, a dual layer can be deposited and then patterned as before, to form the second—phase set of gate electrodes.
- the desired dual layer polycide electrodes particu ⁇ larly if the material of the silicide layer is not readily amenable to sputtering.
- the metal component of the desired silicide for example, cobalt for cobalt silicide, or titanium for titanium silicide.
- the metal on polysilicon is heated at a temperature sufficient to form the metal silicide at regions of overlap by partial reaction of the polysilicon.
- the unreacted metal is removed selectively by a suitable etchant, leaving the dual layer of silicide and polysilicon at the original region of overlap.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Le dispositif à couplage de charge décrit, qui est destiné à être utilisé comme dispositif à couplage de charge à transfert interligne dans un appareil de représentation par images, comprend des photodétecteurs. Ledit dispositif à couplage de charge comporte des électrodes de porte opaques (14, 16) destinées à éviter que les électrodes de porte ne doivent être recouvertes d'une protection contre la lumière. On obtient l'opacité et la faible résistance de couche désirées des électrodes en utilisant une structure à deux couches comprenant une couche inférieure de polysilicium dopé (14A, 16A) et une couche supérieure d'un siliciure (14B, 16B), tel que du siliciure de tungstène.The described charge coupled device, which is intended to be used as a charge coupled interline transfer device in an image representation apparatus, includes photodetectors. The charge coupled device has opaque door electrodes (14, 16) to prevent the door electrodes from being covered with light protection. The desired opacity and low layer resistance of the electrodes are obtained by using a two-layer structure comprising a lower layer of doped polysilicon (14A, 16A) and an upper layer of a silicide (14B, 16B), such as tungsten silicide.
Description
Charge-coupled device with dual layer electrodes. Technical Field
The present invention relates to charge coupled devices (CCDs) and more particularly to interline transfer CCDs. Background Art
Interline transfer CCDs are used in imaging apparatus of the kind which comprises an array of photodetectors aligned in a plurality of rows each o which includes a plurality of photodetectors and in which the interline transfer CCDs are. interleaved between the rows of photodetectors. In operation, the currents detected by the individual photo¬ detectors in one row, after integration in associate storage capacitors, are periodically transferred in parallel for storage as charges in individual cells of an adjacent interline transfer CCD and then such charges are read out serially from the CCD as currents into an output line for transmission to a utilization site.
It is important for such utilization that the interline transfer CCD itself be unaffected directly by the light used to excite the array of photocells and it is the usual practice to utilize a light shield over the CCD for this purpose, generally in the form of a layer of metal, deposited over the surface of the common silicon substrate in which have been formed the array of photodetectors and the interline transfer CCDs, and suitably patterned to permit light to reach the photodetectors but not to reach the critical gate electrode regions of the CCD.
It would be advantageous to provide opaqueness to the gate electrodes so that a self- aligned built—in shield automatically exists with the definition of the gate electrodes and there is consequently avoided the need for additional
shielding. However, the gate electrodes typically are of doped polysilicon, which does not exhibit the desired opaqueness.
Another problem is that polysilicon even when doped tends to have a higher sheet resistivity than is desirable. It accordingly would be advan¬ tageous if, in addition to increased opaqμeness, the gate electrodes have a lower sheet resistance to improve the readout speed that can be realized. Disclosure of the Invention
To these ends, it has been found desirable to employ as the gate electrode a dual layer including a lower layer of doped polysilicon and an upper layer of silicide. Such a dual layer will be referred to hereinafter as a polycide layer. The use of tungsten silicide as the silicide has proven particularly advantageous, since it results in a polycide gate electrode which is both opaque and highly conductive. In the polycide process forming the preferred embodiment of the invention, a silicide layer is uniformly deposited in turn over each of the two polysilicon layers usually deposited for forming the first—phase and second—phase set of gate electrodes, respectively, and the polysilicon and silicide layers are etched by reactive ion etching using a common mask to achieve automatic alignment of the two layers. Moreover, the polycide process permits a high resistance oxide layer to be grown over the first—phase set of gate electrodes to provide electrical isolation from the overlapping second—phase set of gate electrodes.
In one aspect this invention is directed to a charge—coupled device using a two—phase gate electrode system having a first—phase set of gate electrodes interleaved with an overlapping second- phase set of gate electrodes in which both the
first—phase set of electrodes and the second—phase set of electrodes are opaque and have a dual layer structure in which the lower layer is of polysilicon doped to be conductive and the upper layer is of an opaque silicide, and the two sets are separated by an isolation oxide grown from the silicide. Brief Description of the Drawings ,
The invention will be better understood from the following more detailed description taken with the accompanying drawing in which:
FIG. 1 shows a section taken longitudinally along the channel region of one stage of a CCD which includes polycide first—phase and second—phase gate electrodes in accordance with the invention. Modes of Carrying Out the Invention
The invention will be described with particular reference to incorporation in a conven¬ tional two—phase buried channel CCD.
In FIG. 1, the silicon wafer 10, whose bulk is p—type, includes at its upper surface a buried channel in which the signal charge transfer will be localized. This channel is formed by the implanta¬ tion of donor ions, represented schematically by the upper row of + signs 12. A silicon oxide layer 13 overlies the channel at the upper surface of the wafer. Overlying the oxide layer are the gate electrodes including the first—phase set of elec¬ trodes 1 of which only two are shown. Overlapping the first—phase set of electrodes is the second—phase set of electrodes 16, of which only one is shown. A clock source (not shown) will be connected between the two sets of electrodes to apply a voltage difference therebetween which varies periodically to transfer the signal packet of charges between successive potential wells in the buried channel set up by the two sets of gate electrodes. To ensure the
desired directionality of the charge transfer between the wells, additional donor ions are impla'nted asymmetrically under each gate electrode, as shown denoted by the lower row + signs 18. In the respects described, this CCD is conventional. Moreover, in the aforementioned copending application, there is described one method for fabricating such a structure. In accordance with this invention, both sets of electrodes 1 and 16 include two layers. The lower layer 14A, 16A which contacts the gate oxide layer 13 is of polysilicon doped to be of low resistivity and is several thousand Angstroms thick, for example, about 3000 Angstroms thick. This layer is important because polysilicon is uniquely suited for serving as the control metal to the silicon oxide gate insulation. The upper level 14B, 16B is of a silicide, advantageously tungsten silicide of sufficient thickness to be opaque to ambient light and to have low resistance. A thickness of several thousand Angstroms, for example, 3000, is suffi¬ cient. A silicon oxide layer 20 provides electrical isolation between electrodes 14 and 16 in the regions of overlap.
Various techniques may be used to form such dual polycide layers.
In particular, a preferred technique involves first depositing non—selectively a uniform layer of polysilicon of appropriate doping and thickness in conventional fashion, for example, chemical vapor deposition, and then sputter deposit¬ ing thereover non—selectively a layer of tungsten silicide of appropriate thickness, using a tungsten silicide source. The resulting two—layer structure is then masked in the pattern desired and plasma etched anisotropically to provide the desired
substantially vertical side walls to the two—layer structure.
' Moreover, before depositing the dual layer structure for use in forming the second—phase set of electrodes, the wafer is heated in an oxidizing ambient to grow a silicon oxide layer over the surface of the first—phase set of sufficient thickness to provide the desired isolation, for example, about a thousand Angstroms thick. After such growth, a dual layer can be deposited and then patterned as before, to form the second—phase set of gate electrodes. Industrial Applicability and Advantages
Other techniques are available for forming the desired dual layer polycide electrodes, particu¬ larly if the material of the silicide layer is not readily amenable to sputtering. In such instances, after deposit of the polysilicon film and patterning it to serve as the first—phase set of electrodes, there is deposited non—selectively a layer of the metal component of the desired silicide, for example, cobalt for cobalt silicide, or titanium for titanium silicide. Then the metal on polysilicon is heated at a temperature sufficient to form the metal silicide at regions of overlap by partial reaction of the polysilicon. The unreacted metal is removed selectively by a suitable etchant, leaving the dual layer of silicide and polysilicon at the original region of overlap.
Claims
1. A charge—coupled device using a two—phase gate electrode system having a first—phase set of gate electrodes interleaved with an over— lapping second— hase set of gate electrodes, characterized in that both the first—phase set of electrodes and the second—phase set of electrodes are opaque and have a dual layer structure in which the lower layer is of polysilicon doped to be conductive and the upper layer is of an opaque silicide, and the two sets are separated by an isolation oxide grown from the silicide.
2. The device of claim 1 in which the silicide is tungsten silicide.
3. The device of claim 2 in which the polysilicon and the silicide layers are each about several thousand Angstroms thick.
4. The device of claim 3 in which the isolation oxide is about 1000 Angstroms thick.
5. In the manufacture of a two—phase CCD, the process of forming the two sets of gate elec¬ trodes comprising forming in turn each set of gate electrodes by depositing non—selectively a layer of polysilicon and a layer of tungsten silicide and then plasma etching selectively the two layers aniso— tropically to form the desired set of gate electrodes.
6. In the process of claim 5, the step of oxidizing the silicide layer of the first set of gate electrodes to form an isolation oxide before forming the second set of gate electrodes.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3196987A | 1987-03-30 | 1987-03-30 | |
| US31969 | 2005-01-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0309542A1 true EP0309542A1 (en) | 1989-04-05 |
Family
ID=21862395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP19880903574 Withdrawn EP0309542A1 (en) | 1987-03-30 | 1988-03-21 | Charge-coupled device with dual layer electrodes |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0309542A1 (en) |
| JP (1) | JPH01503102A (en) |
| WO (1) | WO1988007767A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5286669A (en) * | 1989-07-06 | 1994-02-15 | Kabushiki Kaisha Toshiba | Solid-state imaging device and method of manufacturing the same |
| DE69030533T2 (en) * | 1989-07-06 | 1997-09-18 | Toshiba Kawasaki Kk | Method of manufacturing a solid-state imaging device |
| KR920010433B1 (en) * | 1990-07-10 | 1992-11-27 | 금성일렉트론 주식회사 | Charge coupled device manufacturing method using self-align process |
| JP2853785B2 (en) * | 1992-01-30 | 1999-02-03 | 松下電子工業株式会社 | Solid-state imaging device and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4290187A (en) * | 1973-10-12 | 1981-09-22 | Siemens Aktiengesellschaft | Method of making charge-coupled arrangement in the two-phase technique |
| US4640844A (en) * | 1984-03-22 | 1987-02-03 | Siemens Aktiengesellschaft | Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon |
| FR2571177B1 (en) * | 1984-10-02 | 1987-02-27 | Thomson Csf | PROCESS FOR PRODUCING SILICIDE OR SILICON GRIDS FOR INTEGRATED CIRCUIT COMPRISING GRID - INSULATOR - SEMICONDUCTOR ELEMENTS |
-
1988
- 1988-03-21 WO PCT/US1988/000858 patent/WO1988007767A1/en not_active Application Discontinuation
- 1988-03-21 EP EP19880903574 patent/EP0309542A1/en not_active Withdrawn
- 1988-03-21 JP JP50321088A patent/JPH01503102A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| See references of WO8807767A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01503102A (en) | 1989-10-19 |
| WO1988007767A1 (en) | 1988-10-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 19881212 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB |
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| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
| 18W | Application withdrawn |
Withdrawal date: 19901002 |