Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42396—Gate electrodes for field effect devices for charge coupled devices

Definitions

• the present invention relates to charge coupled devices (CCDs) and more particularly to interline transfer CCDs.
• Interline transfer CCDs are used in imaging apparatus of the kind which comprises an array of photodetectors aligned in a plurality of rows each o which includes a plurality of photodetectors and in which the interline transfer CCDs are. interleaved between the rows of photodetectors.
• the currents detected by the individual photo ⁇ detectors in one row after integration in associate storage capacitors, are periodically transferred in parallel for storage as charges in individual cells of an adjacent interline transfer CCD and then such charges are read out serially from the CCD as currents into an output line for transmission to a utilization site.
• the interline transfer CCD itself be unaffected directly by the light used to excite the array of photocells and it is the usual practice to utilize a light shield over the CCD for this purpose, generally in the form of a layer of metal, deposited over the surface of the common silicon substrate in which have been formed the array of photodetectors and the interline transfer CCDs, and suitably patterned to permit light to reach the photodetectors but not to reach the critical gate electrode regions of the CCD.
• the gate electrodes typically are of doped polysilicon, which does not exhibit the desired opaqueness.
• a dual layer including a lower layer of doped polysilicon and an upper layer of silicide Such a dual layer will be referred to hereinafter as a polycide layer.
• tungsten silicide as the silicide has proven particularly advantageous, since it results in a polycide gate electrode which is both opaque and highly conductive.
• a silicide layer is uniformly deposited in turn over each of the two polysilicon layers usually deposited for forming the first—phase and second—phase set of gate electrodes, respectively, and the polysilicon and silicide layers are etched by reactive ion etching using a common mask to achieve automatic alignment of the two layers.
• the polycide process permits a high resistance oxide layer to be grown over the first—phase set of gate electrodes to provide electrical isolation from the overlapping second—phase set of gate electrodes.
• this invention is directed to a charge—coupled device using a two—phase gate electrode system having a first—phase set of gate electrodes interleaved with an overlapping second- phase set of gate electrodes in which both the first—phase set of electrodes and the second—phase set of electrodes are opaque and have a dual layer structure in which the lower layer is of polysilicon doped to be conductive and the upper layer is of an opaque silicide, and the two sets are separated by an isolation oxide grown from the silicide.
• FIG. 1 shows a section taken longitudinally along the channel region of one stage of a CCD which includes polycide first—phase and second—phase gate electrodes in accordance with the invention.
• the silicon wafer 10 whose bulk is p—type, includes at its upper surface a buried channel in which the signal charge transfer will be localized. This channel is formed by the implanta ⁇ tion of donor ions, represented schematically by the upper row of + signs 12.
• a silicon oxide layer 13 overlies the channel at the upper surface of the wafer. Overlying the oxide layer are the gate electrodes including the first—phase set of elec ⁇ trodes 1 of which only two are shown. Overlapping the first—phase set of electrodes is the second—phase set of electrodes 16, of which only one is shown.
• a clock source (not shown) will be connected between the two sets of electrodes to apply a voltage difference therebetween which varies periodically to transfer the signal packet of charges between successive potential wells in the buried channel set up by the two sets of gate electrodes.
• additional donor ions are impla'nted asymmetrically under each gate electrode, as shown denoted by the lower row + signs 18.
• this CCD is conventional.
• both sets of electrodes 1 and 16 include two layers.
• the lower layer 14A, 16A which contacts the gate oxide layer 13 is of polysilicon doped to be of low resistivity and is several thousand Angstroms thick, for example, about 3000 Angstroms thick. This layer is important because polysilicon is uniquely suited for serving as the control metal to the silicon oxide gate insulation.
• the upper level 14B, 16B is of a silicide, advantageously tungsten silicide of sufficient thickness to be opaque to ambient light and to have low resistance. A thickness of several thousand Angstroms, for example, 3000, is suffi ⁇ cient.
• a silicon oxide layer 20 provides electrical isolation between electrodes 14 and 16 in the regions of overlap.
• a preferred technique involves first depositing non—selectively a uniform layer of polysilicon of appropriate doping and thickness in conventional fashion, for example, chemical vapor deposition, and then sputter deposit ⁇ ing thereover non—selectively a layer of tungsten silicide of appropriate thickness, using a tungsten silicide source.
• the resulting two—layer structure is then masked in the pattern desired and plasma etched anisotropically to provide the desired substantially vertical side walls to the two—layer structure.
• the wafer before depositing the dual layer structure for use in forming the second—phase set of electrodes, the wafer is heated in an oxidizing ambient to grow a silicon oxide layer over the surface of the first—phase set of sufficient thickness to provide the desired isolation, for example, about a thousand Angstroms thick. After such growth, a dual layer can be deposited and then patterned as before, to form the second—phase set of gate electrodes.
• the desired dual layer polycide electrodes particu ⁇ larly if the material of the silicide layer is not readily amenable to sputtering.
• the metal component of the desired silicide for example, cobalt for cobalt silicide, or titanium for titanium silicide.
• the metal on polysilicon is heated at a temperature sufficient to form the metal silicide at regions of overlap by partial reaction of the polysilicon.
• the unreacted metal is removed selectively by a suitable etchant, leaving the dual layer of silicide and polysilicon at the original region of overlap.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Solid State Image Pick-Up Elements (AREA)

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• 1988
  • 1988-03-21 JP JP50321088A patent/JPH01503102A/ja active Pending
  • 1988-03-21 WO PCT/US1988/000858 patent/WO1988007767A1/en not_active Application Discontinuation
  • 1988-03-21 EP EP19880903574 patent/EP0309542A1/de not_active Withdrawn

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