JP2011228733A - Photosensor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photosensor capable of restraining an increase in leak current and a method of manufacturing the same.SOLUTION: A photosensor related to the present invention includes a photodiode 100 having a semiconductor active layer, a photodiode electrode 12 made up of a transparent conductive film, and diffusion prevention layer 12a which is formed between the semiconductor active layer and the photodiode electrode 12 and prevents the components of the photodiode electrode 12 from diffusing to the semiconductor active layer. The oxygen composition ratio of the diffusion prevention layer 12a is higher than that of the photodiode electrode 12 in the center of a film thickness direction, or the zinc composition ratio of the diffusion prevention layer 12a is higher than that of the photodiode electrode 12 in the center in the film thickness direction.

Description

  The present invention relates to a photosensor and a manufacturing method thereof.

  A photosensor which is a flat panel including a TFT array substrate on which a photodiode for photoelectrically converting visible light and a TFT is disposed is widely used by being applied to a contact image sensor, an X-ray imaging display device, and the like. In particular, a flat panel X-ray imaging display device (hereinafter referred to as FPD) configured by providing a scintillator for converting X-rays into visible light on a TFT array substrate is a promising device for application to the medical industry and the like. .

  In the field of X-ray image diagnosis, precision images (still images) and real-time image observation (moving images) are properly used. X-ray film is still used mainly for still image shooting. On the other hand, an imaging tube (image intensifier) in which a photomultiplier tube and a CCD are combined is used for shooting a moving image. X-ray film has high spatial resolution, but it has low sensitivity and can only shoot a still image, and requires development processing after shooting, and lacks immediacy. On the other hand, the imaging tube has high sensitivity and can shoot a moving image, but has a drawback that it has a low spatial resolution and is limited in size because it is a vacuum device.

  The FPD has an indirect conversion method in which X-rays are converted into light by a scintillator such as CsI and then converted into charges by a photodiode, and a direct conversion method in which X-rays are converted directly into charges by an X-ray detection element typified by Se is there. The indirect conversion method has higher quantum efficiency, better signal / noise ratio, and enables fluoroscopy and imaging with a small exposure dose. A structure and manufacturing method related to an indirect conversion type FPD array substrate have been disclosed (see, for example, Patent Document 1).

JP 2000-101920 A

  In an FPD array substrate, it is important to form a photodiode that affects the sensitivity and noise of the photosensor. For example, as in Patent Document 1, the photosensor includes an amorphous silicon layer formed on an electrode and a transparent conductive film. When ITO generally used as the transparent conductive film is used, In diffuses into silicon. Due to this influence, there is a problem that when the bias voltage is increased, the rectification property formed between the i layer and the p layer is easily lost, and the leakage current of the photodiode is increased.

  The present invention has been made to solve the above problems, and an object thereof is to provide a photosensor capable of suppressing an increase in leakage current and a method for manufacturing the photosensor.

The photosensor according to the present invention is
A photodiode having a semiconductor active layer;
A photodiode electrode formed from a transparent conductive film;
A diffusion prevention layer that is formed between the semiconductor active layer and the photodiode electrode and prevents components of the photodiode electrode from diffusing into the semiconductor active layer;
The diffusion preventing layer has a higher oxygen composition ratio than the center oxygen composition ratio in the film thickness direction of the photodiode electrode, or a zinc composition higher than the center zinc composition ratio in the film thickness direction of the photodiode electrode. Have a ratio.

In addition, a method of manufacturing a photosensor according to the present invention includes
A method for producing the photosensor of the present invention as described above,
Depositing the semiconductor active layer constituting the photodiode;
Forming the transparent conductive film constituting the photodiode electrode disposed opposite to the semiconductor active layer with the diffusion preventing layer interposed therebetween.

    ADVANTAGE OF THE INVENTION According to this invention, the photosensor which can suppress the increase in leak current, and its manufacturing method can be provided.

1 is a schematic diagram illustrating a configuration of an X-ray imaging apparatus according to a first embodiment. 1 is a plan view showing a configuration of a TFT substrate according to a first embodiment. 2 is a plan view showing a configuration of a pixel of a TFT substrate according to the first embodiment; It is sectional drawing in the part shown by IV-IV in FIG. FIG. 3 is a cross-sectional view illustrating a configuration of a terminal portion of the TFT substrate according to the first embodiment. FIG. 6 is a cross-sectional view showing another configuration of the terminal portion of the TFT substrate according to the first embodiment. 2 is a cross-sectional view showing a configuration of a TFT substrate used in the X-ray imaging apparatus according to Embodiment 1. FIG. FIG. 6 is a cross-sectional view showing a manufacturing step of the TFT substrate in the pixel according to the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the TFT substrate in the pixel according to the first embodiment. 6 is a cross-sectional view showing a manufacturing process of the TFT substrate in the terminal portion according to the first embodiment; FIG. FIG. 6 is a cross-sectional view illustrating a configuration of a TFT substrate according to a second embodiment. FIG. 6 is a cross-sectional view illustrating a configuration of a TFT substrate according to a third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the TFT substrate according to the third embodiment. FIG. 6 is a plan view illustrating a configuration of a pixel of a TFT substrate according to a fourth embodiment. FIG. 10 is a plan view illustrating another configuration of a pixel on a TFT substrate according to a fourth embodiment.

Embodiment 1
Hereinafter, the present invention will be specifically described with reference to the drawings illustrating embodiments of the present invention. The photosensor according to the present embodiment is used in, for example, an X-ray imaging apparatus. First, an X-ray imaging apparatus will be described with reference to FIG. FIG. 1 is a schematic diagram illustrating a configuration of an X-ray imaging apparatus.

    As shown in FIG. 1, the X-ray imaging apparatus includes an image processing apparatus 200, a photo sensor 201, and an X-ray source 202. The photo sensor 201 that is a flat panel and the X-ray source 202 are disposed to face each other. The photo sensor 201 outputs a signal corresponding to the intensity of incident light. The photosensor 201 has a scintillator that converts X-rays into visible light. The photo sensor 201 is connected to the image processing apparatus 200. The image processing apparatus 200 is an information processing apparatus such as a personal computer. Then, a predetermined calculation process is performed on the output from the photosensor 201. The image processing apparatus 200 is provided with a display, and an X-ray image is displayed on the display.

    Next, a TFT substrate provided in the photosensor 201 according to the present embodiment will be described with reference to FIG. FIG. 2 is a plan view showing the configuration of the TFT substrate.

    The TFT substrate is, for example, an active matrix TFT array substrate in which photodiodes 100 and thin film transistors (TFTs) 107 are arranged in a matrix. The TFT substrate is provided with a detection region 101 and a frame region 102 provided so as to surround the detection region 101. A plurality of gate lines 27, a plurality of data lines 14, and a plurality of bias lines 15 are formed in the detection region 101.

    The plurality of gate wirings 27 are provided in parallel. The plurality of data lines 14 and the plurality of bias lines 15 are provided in parallel. The bias line 15 is provided between the adjacent data lines 14. That is, the data lines 14 and the bias lines 15 are alternately arranged. The gate wiring 27 and the data wiring 14 are formed so as to cross each other. Similarly, the gate wiring 27 and the bias wiring 15 are formed so as to cross each other. The gate wiring 27 and the data wiring 14 are orthogonal to each other. Similarly, the gate wiring 27 and the bias wiring 15 are orthogonal to each other. A region surrounded by the adjacent gate wiring 27 and the adjacent data wiring 14 becomes the pixel 103. In the TFT substrate, the pixels 103 are arranged in a matrix.

    Further, a gate drive circuit 104, a digital circuit 105, and a charge readout circuit 106 are provided in the frame region 102 of the TFT substrate. The gate wiring 27 extends from the detection area 101 to the frame area 102. The gate wiring 27 is connected to the gate drive circuit 104 at the end of the TFT substrate. Similarly, the data wiring 14 extends from the detection area 101 to the frame area 102. The data wiring 14 is electrically connected to the charge readout circuit 106 via a low noise amplifier at the end of the TFT substrate. The digital circuit 105 is electrically connected to the charge reading circuit 106. Note that the low noise amplifier may be provided between the charge readout circuit 106 and the digital circuit 105.

    Various signals from the outside are supplied to the gate drive circuit 104 via, for example, a wiring board. The gate driving circuit 104 supplies a gate signal (scanning signal) to the gate wiring 27 based on an external control signal. The gate wiring 27 is sequentially selected by this gate signal. The output from the data wiring 14 is supplied to a low noise amplifier and amplified. The amplified signal is supplied to the charge readout circuit 106. The charge readout circuit 106 includes, for example, an integrator, a sample hold, and a multiplexer amplifier. The charge readout circuit 106 reads out the output from the data wiring 14. Specifically, the charge readout circuit 106 sequentially selects outputs from the plurality of data lines 14 and sends them to the digital circuit 105.

    The digital circuit 105 includes at least an A / D converter. The digital circuit 105 may include a correction arithmetic circuit, a conversion circuit, and the like. The signal from the readout circuit 106 is A / D converted by an A / D converter. The A / D converted signal is corrected and calculated by a correction calculation circuit. The correction calculation may be performed by the image processing apparatus 200. Further, the A / D converted signal is converted by the conversion circuit into a signal in accordance with a format for sending to the image processing apparatus 200 for the purpose of reducing the number of output signals. Note that the gate driving circuit 104, the digital circuit 105, and the charge readout circuit 106 are not limited to the configuration arranged on the TFT substrate.

    One TFT 107 and one photodiode 100 are formed in the pixel 103. Within the pixel 103, the TFT 107 and the photodiode 100 are connected in series. The TFT 107 is disposed near the intersection of the gate line 27 and the data line 14. The TFT 107 serves as a switching element for supplying the output from the photodiode 100 to the data wiring 14.

    The gate electrode of the TFT 107 is connected to the gate wiring 27, and the TFT 107 is turned on and off by a gate signal input from the gate terminal. The source electrode of the TFT 107 is connected to the data line 14. The drain electrode of the TFT 107 is connected to the photodiode 100. When a voltage is applied to the gate electrode and the TFT 107 is turned on, a current flows from the drain electrode to the source electrode. That is, the charge converted by the photodiode 100 flows through the data wiring 14 via the TFT 107. The charge from the data wiring 14 is A / D converted by the digital circuit 105 through the charge reading circuit 106 and the like. The TFT substrate is configured as described above.

    When X-ray imaging is performed, the subject 203 is moved between the photosensor 201 and the X-ray source 202. Then, the X-ray 204 is irradiated from the X-ray source 202 toward the subject 203. X-rays 204 that have passed through the subject 203 are converted into visible light by the scintillator of the photosensor 201. Then, visible light enters the photodiode 100 and undergoes photoelectric conversion. As a result, the charge converted by the photodiode 100 flows to the data line 14 via the TFT 107. The electric charge from the data line 14 is supplied to the low noise amplifier and amplified. The amplified signal is A / D converted by the digital circuit 105 through the reading circuit 106. Then, after the A / D conversion, a signal that has been formatted in a specific format by the conversion circuit is sequentially sent to the image processing apparatus 200. The image processing apparatus 200 performs a predetermined calculation process based on the input signal. Thereby, an X-ray image can be obtained.

    Next, the TFT substrate will be described in detail. First, the configuration of the pixel 103 on the TFT substrate will be described with reference to FIGS. FIG. 3 is a plan view showing the configuration of the pixel 103 of the TFT substrate according to this embodiment. That is, the configuration of the TFT substrate in a region surrounded by the adjacent data wiring 14 and the adjacent gate wiring 27 is shown. 4 is a cross-sectional view taken along the line IV-IV in FIG.

    As shown in FIG. 4, the gate electrode 2 is formed on the insulating substrate 1. The gate electrode 2 is formed integrally with the gate wiring 27. As the insulating substrate 1, a transparent insulating substrate such as a glass substrate can be used. The gate electrode 2 and the gate wiring 27 are formed of a low resistance metal material. In the present embodiment, the gate electrode 2 and the gate wiring 27 contain a metal whose main component is aluminum (Al). As the metal mainly composed of Al, an Al alloy containing Ni such as AlNiNd, AlNiSi, AlNiMg, that is, an Al—Ni alloy is used. Of course, as the metal mainly composed of Al, other Al alloys may be used. In addition to Al, Cu or the like may be used as a low resistance metal material.

A gate insulating film 3 is formed so as to cover the gate electrode 2 and the gate wiring 27. Then, the semiconductor layer 4 is formed on the gate insulating film 3 so as to face the gate electrode 2. The semiconductor layer 4 is an amorphous silicon (a-Si: H) layer to which hydrogen atoms are added. An ohmic contact layer 5 is formed on the semiconductor layer 4. The ohmic contact layer 5 is a semiconductor layer containing impurities and has a reduced resistance. Specifically, the ohmic contact layer 5 is an n ⁺ a-Si: H layer in which phosphorus (P) is doped as an impurity in the a-Si: H layer.

    As shown in FIG. 4, the ohmic contact layer 5 does not exist on the central portion of the semiconductor layer 4 on the gate electrode 2. The region of the semiconductor layer 4 where the ohmic contact layer 5 does not exist is a channel region. The ohmic contact layer 5 is formed at both ends of the semiconductor layer 4. One ohmic contact layer 5 constitutes a source region, and the other ohmic contact layer 5 constitutes a drain region. That is, the source region and the drain region are disposed to face each other with the channel region interposed therebetween.

    A source electrode 6 and a drain electrode 7 are formed on the ohmic contact layer 5. The source electrode 6 and the drain electrode 7 are connected to the semiconductor layer 4 through the ohmic contact layer 5. The source electrode 6 is formed on the source region. The drain electrode 7 is formed on the drain region. As shown in FIG. 3, the source electrode 6 is formed to extend from the semiconductor layer 4 to the data wiring 14. The drain electrode 7 is formed to extend from the semiconductor layer 4 to the lower electrode 25 of the photodiode 100.

    A first passivation film 8 is formed so as to cover the source electrode 6 and the drain electrode 7. A contact hole CH <b> 1 is formed in the first passivation film 8 on the drain electrode 7. That is, the first passivation film 8 does not exist on a part of the drain electrode 7. The lower electrode 25 is formed on substantially the entire pixel. That is, the lower electrode 25 is formed in a region surrounded by the adjacent gate line 27 and the adjacent data line 14. The lower electrode 25 is embedded in the contact hole CH1. The lower electrode 25 and the drain electrode 7 are electrically connected via the contact hole CH1.

A photodiode 100 is formed on substantially the entire lower electrode 25. In this embodiment, a photodiode having a pin structure is used as the photodiode 100. That is, the photodiode 100 has a structure in which an intrinsic semiconductor layer (intrinsic layer) with few carriers and high resistance is provided in the middle of the pn junction. Specifically, the photodiode 100 includes a semiconductor active layer having a three-layer structure in which an n-type semiconductor layer 9, an i-type semiconductor layer 10, and a p-type semiconductor layer 11 are sequentially stacked from the lower electrode 25 side. The n-type semiconductor layer 9 is, for example, an n-type amorphous silicon (n ⁺ a-Si) layer doped with phosphorus (P). The i-type semiconductor layer 10 is, for example, an intrinsic amorphous silicon (ia-Si) layer. The p-type semiconductor layer 11 is, for example, a p-type amorphous silicon (p ⁺ a-Si) layer doped with boron (B).

    A nitrogen-containing semiconductor layer 11 a is formed on the p-type semiconductor layer 11. In other words, the nitrogen-containing semiconductor layer 11 a is formed on the transparent electrode 12 side of the semiconductor active layer of the photodiode 100. The p-type semiconductor layer 11 and the nitrogen-containing semiconductor layer 11a are formed so as to substantially coincide with each other when viewed from above. The nitrogen-containing semiconductor layer 11a is a p-type semiconductor layer containing nitrogen, and is a diffusion prevention layer that can suppress diffusion of In or the like from the upper transparent electrode 12 to silicon of the semiconductor active layer.

    A transparent electrode 12 as a photodiode electrode is formed on the photodiode 100. Specifically, the transparent electrode 12 is formed on the nitrogen-containing semiconductor layer 11a. In other words, the nitrogen-containing semiconductor layer 11 a is formed between the semiconductor active layer of the photodiode 100 and the transparent electrode 12. That is, the semiconductor active layer of the photodiode 100 and the transparent electrode 12 are disposed to face each other through the nitrogen-containing semiconductor layer 11a that is a diffusion preventing layer. The nitrogen-containing semiconductor layer 11a and the transparent electrode 12 are in direct contact. The transparent electrode 12 is formed from a transparent conductive film that is a metal oxide film. The transparent electrode 12 contains indium oxide.

    The photodiode 100 is sandwiched between opposing electrodes. That is, the transparent electrode 12 is an anode electrode of the photodiode 100. The lower electrode 25 is a cathode electrode of the photodiode 100. With such a configuration, visible light transmitted through the transparent electrode 12 is incident on the photodiode 100. The visible light is converted into electric charges by the photodiode 100, and a current flows from the lower electrode 25.

    A second passivation film 13 is formed on the transparent electrode 12 so as to cover them. Here, the second passivation film 13 may be a single coating-type transparent insulating film, or may have a coating-type transparent insulating film as an upper layer of the transparent insulating film formed by CVD or the like.

    A contact hole CH2 is formed in the first passivation film 8 and the second passivation film 13 on the source electrode 6. That is, the first passivation film 8 and the second passivation film 13 do not exist on a part of the source electrode 6. Further, a contact hole CH3 is formed in the second passivation film 13 on the transparent electrode 12. That is, the second passivation film 13 does not exist on a part of the transparent electrode 12.

    On the second passivation film 13, a data line 14, a bias line 15, and a light shielding layer 16 are formed. As shown in FIG. 3, the data line 14 extends linearly so as to pass through the contact hole CH2. The data wiring 14 is embedded in the contact hole CH2. Then, the source electrode 6 and the data wiring 14 are electrically connected through the contact hole CH2. The data line 14 extends over the plurality of pixels 103, and reads out the charges converted by the photodiode 100 from the source electrode 6 of each pixel 103.

    As shown in FIG. 3, the bias wiring 15 extends linearly so as to pass through the contact hole CH3. The bias wiring 15 is embedded in the contact hole CH3. Then, the transparent electrode 12 and the bias wiring 15 are electrically connected through the contact hole CH3. The bias wiring 15 extends over the plurality of pixels 103 and applies a reverse bias to the transparent electrode 12 of each pixel 103. Thus, the photodiode 100 is turned off when no light is applied.

    The light shielding layer 16 is formed on the TFT 107. The light shielding layer 16 is formed in a rectangular shape. The bias wiring 15 and the light shielding layer 16 are integrally formed. Of course, the present invention is not limited to this, and the bias wiring 15 and the light shielding layer 16 may be formed individually. Further, the width of the light shielding layer 16 is larger than the width of the bias wiring 15. Note that the data wiring 14 and the bias wiring 15 are formed of a conductive film containing an Al alloy, and desirably have an Al—Ni alloy film in the uppermost layer or the lowermost layer. The data wiring 14 and the bias wiring 15 may be formed of a single layer of an Al—Ni alloy film. When the uppermost layer has an Al—Ni alloy film, the surface may be a nitride layer.

    And the 3rd passivation film 17 and the 4th passivation film 18 are formed in order so that these may be covered. The fourth passivation film 18 has a flat surface. The fourth passivation film 18 is made of, for example, an organic resin. The pixel 103 on the TFT substrate is configured as described above.

    Next, the configuration of the terminal portion of the TFT substrate will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the configuration of the terminal portion of the TFT substrate.

    In the terminal portion, the gate insulating film 3 and the first passivation film 8 are sequentially formed on substantially the entire surface of the insulating substrate 1. A wiring conversion pattern 23 is formed on the first passivation film 8. The wiring conversion pattern 23 is a pattern for electrically connecting the wiring and the terminal. Further, the wiring conversion pattern 23 may be connected to a short ring formed outside the panel. The short ring is a wiring provided to suppress destruction of elements such as the TFT 107 due to static electricity generated during the manufacturing process of the TFT substrate. A second passivation film 13 is formed so as to cover them. On the wiring conversion pattern 23, contact holes CH4 and CH7 are formed in the second passivation film 13. That is, the second passivation film 13 does not exist in a part on the wiring conversion pattern 23.

    A wiring 24 is formed on the second passivation film 13. For example, the wiring 24 may extend from the data wiring 14 or the bias wiring 15. Further, the wiring 24 may be electrically connected to the gate wiring 27 through, for example, a contact hole CH6 (not shown). An end portion of the wiring 24 is embedded in the contact hole CH7. Then, the wiring 24 and the wiring conversion pattern 23 are electrically connected through the contact hole CH7. And the 3rd passivation film 17 and the 4th passivation film 18 are formed in order so that the wiring 24 may be covered. Further, the contact hole CH5 is formed in the third passivation film 17 and the fourth passivation film 18 on the contact hole CH4. The contact hole CH5 is formed larger than the contact hole CH4. In other words, the contact hole CH4 is formed inside the contact hole CH5.

    A terminal 22 is formed on the fourth passivation film 18. The terminal 22 is embedded in the contact holes CH4 and CH5. Then, the terminal 22 and the wiring conversion pattern 23 are electrically connected through the contact holes CH4 and CH5. That is, the wiring 24 and the terminal 22 are electrically connected by connecting the wiring conversion pattern 23 to the wiring 24 and the terminal 22. The terminal portion is configured as described above.

    Moreover, a terminal part is good also as not only said structure but the structure shown by FIG. 6, for example. FIG. 6 is a cross-sectional view showing another configuration of the terminal portion. As shown in FIG. 6, the terminal 22 is not formed on the fourth passivation film 18 but formed on the third passivation film 17. That is, the terminal 22 is formed only inside the contact hole CH5.

    In the present embodiment, the wiring conversion pattern 23 is disposed in the upper layer of the first passivation film 8, but may be disposed between the gate insulating film 3 and the first passivation film 8. Furthermore, in FIGS. 5 and 6, the data wiring 14, the bias wiring 15, and the gate wiring 27 are electrically connected to the wiring conversion pattern 23 through the contact hole CH 7 or the like, but this is not restrictive. For example, the wiring 24 such as the data wiring 14, the bias wiring 15, and the gate wiring 27 may be directly used as the wiring conversion pattern 23 without using the contact hole CH 7 or the like. That is, the data line 14, the bias line 15, and the gate line 27 may be directly connected to the terminal 22.

    The TFT substrate provided in the photosensor according to this embodiment is configured as described above. Here, a nitrogen-containing layer 11a as a diffusion preventing layer is formed on the p-type semiconductor layer 11 on the transparent electrode 12 side. For this reason, In diffusion from the anode electrode of the photodiode 100 to the Si layer can be suppressed. That is, In diffusion from the transparent electrode 12 to the semiconductor active layer composed of the n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 can be suppressed. Therefore, the leakage current of the photodiode 100 under a high bias can be suppressed, and a photosensor with less afterimage can be realized.

    As already described, a scintillator is provided in the photosensor used in the X-ray imaging apparatus. Specifically, a scintillator is provided on a TFT substrate provided in the photosensor. FIG. 7 is a cross-sectional view showing a configuration of a TFT substrate used in the X-ray imaging apparatus. As shown in FIG. 7, a scintillator 26 is formed on the fourth passivation film 18. The scintillator 26 is provided on the light incident side of the photodiode 100. That is, the scintillator 26 is provided on the transparent electrode 12 side of the photodiode 100. The scintillator 26 is made of, for example, CsI and converts X-rays into visible light. The configuration other than the scintillator 26 is the same as that of the TFT substrate shown in FIG.

    Next, a manufacturing method of a TFT substrate provided in the photosensor according to the present embodiment will be described with reference to FIGS. 8 and 9 are cross-sectional views showing the manufacturing process of the TFT substrate in the pixel. 8 and 9 are cross-sectional views showing the manufacturing process of the TFT substrate at the location corresponding to FIG. FIG. 10 is a cross-sectional view showing the manufacturing process of the TFT substrate in the terminal portion. That is, FIG. 10 is a cross-sectional view showing a manufacturing process of a TFT substrate at a location corresponding to FIG. 5 or FIG.

First, a first conductive thin film is formed on the insulating substrate 1 by sputtering. It is preferable to use a low-resistance metal material as the material for the first conductive thin film. Specifically, a metal containing Al as a main component, for example, an Al alloy containing Ni can be used as the material for the first conductive thin film. In this embodiment, AlNiNd is used as the material for the first conductive thin film. The film formation conditions are as follows: pressure is 0.2 to 0.5 Pa, DC power is 1.0 to 2.5 kW (in terms of power density, 0.17 to 0.43 W / cm ² ), and film formation temperature is from room temperature to room temperature. A range of about 180 ° C is applied. The film thickness is 150 to 300 nm.

    In order to suppress the reaction with the developer, a nitrided AlNiNd layer may be formed on the AlNiNd. Further, AlNiSi or AlNiMg may be used instead of AlNiNd. Furthermore, the same material may be used for the data wiring 14 and the bias wiring 15, and in that case, the production efficiency is improved. In addition to Al, Cu or a Cu alloy can be used as a low-resistance metal material, and in this case as well, Al can be formed by sputtering.

    In the present embodiment, the gate electrode 2 and the gate wiring 27 are not exposed when the photodiode 100 is formed. Thereby, as the gate electrode 2 and the gate wiring 27, a metal mainly composed of Al or Cu, which is not so strong against damage, can be used. For this reason, low resistance wiring can be formed, so that a large photosensor can be formed.

    Then, a resist (not shown), which is a photosensitive resin, is applied onto the first conductive thin film by spin coating, and a first photolithography process (photoengraving process) is performed in which the applied resist is exposed and developed. Thereby, the resist is patterned into a desired shape. Thereafter, using the resist as a mask, the first conductive thin film is etched and patterned into a desired shape. Thereafter, the resist is removed. Thereby, the gate electrode 2 and the gate wiring 27 are formed.

    Etching is performed, for example, by wet etching using a mixed acid etching solution of phosphoric acid, nitric acid, and acetic acid. The etching solution is not limited to a mixed acid of phosphoric acid, nitric acid, and acetic acid, and other etching solutions can also be used. Further, not only wet etching but dry etching may be used. Note that the cross-sectional shapes of the gate electrode 2 and the gate wiring 27 are preferably tapered. By adopting the tapered shape, defects such as disconnection in subsequent film formation can be reduced. And there exists an effect that an insulation film proof pressure improves.

Next, the gate insulating film 3, the semiconductor layer 4, and the ohmic contact layer 5 are sequentially formed so as to cover the gate electrode 2 and the gate wiring 27 by plasma CVD. The semiconductor layer 4 can be an a-Si: H layer, and the ohmic contact layer can be an n ⁺ a-Si: H layer. The film thicknesses of the gate insulating film 3 are 200 to 400 nm, the semiconductor layer 4 is 100 to 200 nm, and the ohmic contact layer 5 is 20 to 50 nm, for example.

    Note that since the photosensor is required to have a high charge readout efficiency and a TFT having a high driving capability, the semiconductor layer 4 may be divided into two steps to form a TFT to improve the performance of the TFT. As the film forming conditions in that case, the first layer is formed with a good quality film at a low rate of 5 to 20 nm / min, and the remaining film is formed with a deposit rate of 30 nm / min or more. Further, the gate insulating film 3, the semiconductor layer 4, and the ohmic contact layer 5 are formed at a film formation temperature of 250 to 350 ° C.

Next, an island-shaped resist (not shown) is formed on the gate electrode 2 by a second photolithography process. Then, the semiconductor layer 4 and the ohmic contact layer 5 are etched using the resist as a mask. Etching is performed, for example, by dry etching using plasma of a mixed gas of SF ₆ and HCl. Further, the etching gas is not limited to the mixed gas of SF ₆ and HCl, and other etching gases can be used. Thereafter, the resist is removed. Thereby, the semiconductor layer 4 and the ohmic contact layer 5 are patterned in an island shape. At this time, the ohmic contact layer 5 remains on the channel region to be formed later.

Next, a resist (not shown) that opens only around the substrate is formed on the gate insulating film 3 by a third photolithography process. Then, the gate insulating film 3 is etched using the resist as a mask. Etching is performed by dry etching using plasma of a mixed gas of CF ₄ and O ₂ , for example. Further, the etching gas is not limited to the mixed gas of CF ₄ and O ₂ , and other etching gases can be used.

    Next, a second conductive thin film is formed so as to cover the ohmic contact layer 5 using a sputtering method. A refractory metal film such as Cr can be used as the second conductive thin film. The film thickness is 50 to 300 nm. In addition to Cr, the second conductive thin film may be a metal capable of making ohmic contact with Si.

Next, a resist (not shown) corresponding to the source electrode 6 and the drain electrode 7 is formed on the second conductive thin film by a fourth photolithography process. Then, using the resist as a mask, the second conductive thin film is etched to form the source electrode 6 and the drain electrode 7. Etching is performed, for example, by wet etching using a mixed acid of ceric ammonium nitrate and nitric acid. Thereafter, the ohmic contact layer 5 is etched using the formed electrode as a mask. Thereby, a channel is formed, and the TFT 107 is formed. The etching here is performed by dry etching using plasma of a mixed gas of SF ₆ and HCl, for example.

The etching solution is not limited to a mixed acid of cerium ammonium nitrate and nitric acid, and other etching solutions can also be used. The etching gas is not limited to a mixed gas of SF ₆ and HCl, and other etching gases can be used.

    In the terminal portion, the first conductive thin film, the semiconductor layer 4, the ohmic contact layer 5, and the second conductive thin film are removed by the first, second, and fourth photolithography processes and etching. A gate insulating film 3 is formed on substantially the entire insulating substrate 1. Through the above steps, the structure shown in FIGS. 8A and 10A is obtained.

    In order to improve the characteristics of the TFT 107, plasma processing using hydrogen gas may be performed thereafter before the first passivation film 8 is formed to roughen the back channel side, that is, the surface of the semiconductor layer 4. .

And the 1st passivation film 8 is formed into a film so that these may be covered using methods, such as plasma CVD. In the present embodiment, a silicon oxide (SiO ₂ ) film having a low dielectric constant is used as the first passivation film 8. Then, a SiO ₂ film is formed to a thickness of 200 to 400 nm. The film formation conditions of the SiO ₂ film are as follows: the SiH ₄ flow rate is 1.69 × 10 ^{−2 to} 8.45 × 10 ⁻² Pa · m ³ / s (= 10 to 50 sccm), and the N ₂ O flow rate is 3.38 ×. 10 ^{−1 to} 8.45 × 10 ⁻¹ Pa · m ³ / s (200 to 500 sccm), film forming pressure 50 Pa, RF power 50 to 200 W (in terms of power density, 0.015 to 0.67 W / cm ² ) and a film forming temperature in the range of about 200 to 300 ° C. is applied. The first passivation film 8 is not limited to the SiO ₂ film, but may be SiN, SiON, or a laminate of the films. In this case, hydrogen, nitrogen, and NH ₃ are added to the gas to form a film.

Next, a resist (not shown) for forming the contact hole CH1 is formed by a fifth photolithography process. Next, the first passivation film 8 is etched using the resist as a mask. Etching is performed, for example, by dry etching using plasma of a mixed gas of CF ₄ and O ₂ . Further, the etching gas is not limited to the mixed gas of CF ₄ and O ₂ , and other etching gases can be used. Then, the resist is removed. Thereby, the contact hole CH1 is formed. Specifically, the first passivation film 8 on the drain electrode 7 is removed, and the contact hole CH1 is formed. That is, the drain electrode 7 is exposed in the contact hole CH1. In the terminal portion, the first passivation film 8 is formed on substantially the entire gate insulating film 3. Through the above steps, the configuration shown in FIGS. 8B and 10B is obtained.

    Next, a third conductive thin film 28 to be the lower electrode 25 is formed on the first passivation film 8 by using a sputtering method or the like. A third conductive thin film 28 is embedded in the contact hole CH1. As the third conductive thin film 28, a refractory metal film such as Cr can be used.

Subsequently, an n-type semiconductor layer 9, an i-type semiconductor layer 10, and a p-type semiconductor layer 11 are sequentially formed on the third conductive thin film 28 by using a plasma CVD method. These constitute the photodiode 100. In addition, these films are sequentially formed in the same film forming chamber without breaking the vacuum. In the present embodiment, an n ⁺ a-Si layer doped with P as the n-type semiconductor layer 9, an ia-Si layer as the i-type semiconductor layer 10, and a p ⁺ doped with B as the p-type semiconductor layer 11. An a-Si layer is formed. The n ⁺ a-Si layer has a thickness of 5 to 100 nm, the i-a-Si layer has a thickness of 0.5 to 2.0 μm, and the p ⁺ a-Si layer has a thickness of 10 to 80 nm.

The film formation conditions for the ia-Si layer are, for example, that the SiH ₄ flow rate is 1.69 × 10 ^{−1 to} 3.38 × 10 ⁻¹ Pa · m ³ / s (= 100 to 200 sccm), and the H ₂ flow rate is 1. 69 × 10 ^{−1 to} 5.07 × 10 ⁻¹ Pa · m ³ / s (= 100 to 300 sccm), a film forming pressure of 100 to 300 Pa, and an RF power of 30 to 150 W (in terms of power density, 0. 01 to 0.05 W / cm ² ) and a film forming temperature in the range of about 200 to 300 ° C. is applied. The n ⁺ a-Si layer doped with P and the p ⁺ a-Si layer doped with B are each 0.2 to 1.0% of PH ₃ or B ₂ H ₆ as a gas for the above film formation conditions. A film is formed with a mixed film forming gas.

The p ⁺ a-Si layer may be formed by implanting B into the upper layer portion of the i-type semiconductor layer 10 by an ion shower doping method or an ion implantation method. Note that when the p ⁺ a-Si layer is formed by ion implantation, a 5 to 40 nm thick SiO ₂ film may be formed on the surface of the ia-Si layer prior to the formation. This is to reduce damage when B is injected. In that case, the SiO ₂ film may be removed by BHF or the like after ion implantation.

After forming the p-type semiconductor layer 11, a nitrogen-containing semiconductor layer 11a is formed. The nitrogen-containing semiconductor layer 11a has a thickness of 1 to 5 nm. In the nitrogen-containing semiconductor layer 11a, NH ₄ is added to a film forming gas for the p ⁺ a-Si layer by adding 1.69 × 10 ^{−2 to} 1.67 × 10 ⁻¹ Pa · m ³ / s (= several tens sccm). Form a film. In other words, at a later stage of the formation of the p-type semiconductor layer 11, a film containing nitrogen is added to form a film, and the nitrogen-containing semiconductor layer 11 a is formed on the p-type semiconductor layer 11. The formed nitrogen-containing semiconductor layer 11a is in a state in which silicon is more than the composition ratio of quantum silicon nitride. Thereby, the p-type semiconductor layer 11 having the nitrogen-containing semiconductor layer 11a as an upper layer is formed.

    Although the case where the nitrogen-containing semiconductor layer 11a is formed by a film formation method has been described here, the present invention is not limited to this. For example, after the deposition of the p-type semiconductor layer 11, the surface treatment of the deposited p-type semiconductor layer 11 is performed in an atmosphere containing nitrogen plasma. Thereby, the silicon on the surface of the p-type semiconductor layer 11 may be transformed into nitrogen-containing silicon, and the nitrogen-containing semiconductor layer 11 a may be formed on the p-type semiconductor layer 11. In this case, the n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 are preferably formed in the same apparatus as the nitrogen-containing semiconductor layer 11a. That is, it is preferable to form the nitrogen-containing semiconductor layer 11a by forming an atmosphere containing nitrogen plasma in a silicon film forming apparatus for forming these semiconductor layers. Thereby, a manufacturing process can be simplified.

    Furthermore, surface treatment may be performed by an apparatus such as atmospheric pressure plasma after the film formation process of the three-layer silicon. That is, after the n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 are sequentially formed, surface treatment may be performed to form the nitrogen-containing semiconductor layer 11a on the surface of the p-type semiconductor layer 11. . Through the above steps, the third conductive thin film 28, the n-type semiconductor layer 9, the i-type semiconductor layer 10, the p-type semiconductor layer 11, and the nitrogen-containing semiconductor layer 11a are sequentially formed on the first passivation film 8. 8 (c) and 10 (c).

    Then, a fourth conductive thin film is formed on the nitrogen-containing semiconductor layer 11a. The fourth conductive thin film is formed by forming a transparent conductive film such as ITO using a sputtering method, for example. The film thickness is 50 to 300 nm. In this film formation, it is desirable that the substrate is not heated. After forming the fourth conductive thin film, a resist (not shown) having a pattern smaller than the pattern to be the photodiode 100 by a processing margin is formed by a sixth photolithography process. Then, the fourth conductive thin film is etched using the resist as a mask. Thereafter, the resist is removed. Thereby, the transparent electrode 12 is formed.

Next, a resist (not shown) for the photosensitive region of the photodiode 100 is formed on the transparent electrode 12 in a seventh photolithography process. Then, the a-Si layer is etched using the resist as a mask. That is, three layers of the n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 are etched. Etching is performed, for example, by dry etching using plasma of a mixed gas of SF ₆ and HCl. Further, the etching gas is not limited to the mixed gas of SF ₆ and HCl, and other etching gases can be used. Thereafter, the resist is removed. Thereby, the photodiode 100 having a three-layer structure is formed.

    Next, a resist (not shown) corresponding to the lower electrode 25 is formed in an eighth photolithography process. The resist here has a pattern that is slightly larger than the pattern of the photodiode 100. Then, the third conductive thin film 28 is etched using the resist as a mask. Thereafter, the resist is removed. Thereby, the lower electrode 25 is formed. The lower electrode 25 is also formed in the contact hole CH1, and the lower electrode 25 and the drain electrode 7 are electrically connected via the contact hole CH1.

    In the terminal portion, the fourth conductive thin film and the a-Si layer are removed by the sixth and seventh photolithography processes and the etching process. Then, the third conductive thin film 28 is patterned by an eighth photolithography process and etching. Thereby, the wiring conversion pattern 23 is formed. Here, the wiring conversion pattern 23 is formed by the third conductive thin film 28, but is not limited thereto. Separately, a conductive thin film may be formed and patterned to form the wiring conversion pattern 23, or the second conductive thin film may be used as the wiring conversion pattern 23. Through the above steps, the structure shown in FIGS. 9D and 10D is obtained.

Next, a second passivation film 13 for protecting the photodiode 100 is formed on the transparent electrode 12. The second passivation film 13 is formed in order to reduce the additional capacitance applied to the data wiring 14 and the bias wiring 15. For this reason, as the second passivation film 13, for example, a silicon oxide (SiO ₂ ) film having a low dielectric constant and formed with a thick film of 0.5 to 1.5 μm is used.

The film formation conditions of the SiO ₂ film are as follows: the SiH ₄ flow rate is 1.69 × 10 ^{−2 to} 8.45 × 10 ⁻² Pa · m ³ / s (= 10 to 50 sccm), and the N ₂ O flow rate is 3.38 ×. 10 ^{−1 to} 8.45 × 10 ⁻¹ Pa · m ³ / s (200 to 500 sccm), film forming pressure 50 Pa, RF power 50 to 200 W (in terms of power density, 0.015 to 0.67 W / cm ² ) and a film forming temperature in the range of about 200 to 300 ° C. is applied. Although cited SiO ₂ film as the second passivation film 13 is not limited to this. The second passivation film 13 may be a laminated film such as SiO ₂ / SiN / SiO ₂ , and further a SOG (spin coating on glass) film single film or a laminated film of a CVD formed film and an SOG film to reduce the level difference. But you can.

Then, a resist (not shown) for forming the contact holes CH2 and CH3 is formed by a ninth photolithography process. Next, the second passivation film 13 and the first passivation film 8 are etched using the resist as a mask. Etching is performed, for example, by dry etching using plasma of a mixed gas of CF ₄ and Ar. Further, the etching gas is not limited to the mixed gas of CF ₄ and Ar, and other etching gases can be used. Thereafter, the resist is removed. Thereby, contact holes CH2 and CH3 are formed.

    Specifically, the first passivation film 8 and the second passivation film 13 on the source electrode 6 are removed to form the contact hole CH2. That is, the source electrode 6 is exposed in the contact hole CH2. Then, the second passivation film 13 on the transparent electrode 12 is removed, and a contact hole CH3 is formed. That is, the transparent electrode 12 is exposed in the contact hole CH3. In the terminal portion, the second passivation film 13 on the wiring conversion pattern 23 is removed, and contact holes CH4 and CH7 are formed. That is, the wiring conversion pattern 23 is exposed in the contact holes CH4 and CH7. In the present embodiment, the contact hole CH4 is formed simultaneously with the formation of the contact hole CH7, but it may be formed in a separate process. Further, when the contact holes CH2, CH3, CH4, CH6, and CH7 are formed, if the cross section is processed into a tapered shape, the coverage of the upper layer is improved, and disconnection or the like can be reduced. Through the above steps, the structure shown in FIGS. 9E and 10E is obtained.

    Next, a fifth conductive thin film to be the data wiring 14, the bias wiring 15, and the light shielding layer 16 is formed on the second passivation film 13. A fifth conductive thin film is buried in the contact holes CH2 and CH3. As the fifth conductive thin film, an Al alloy containing Ni having low resistance, excellent heat resistance, and excellent contact characteristics with the transparent conductive film is used. For example, an AlNiNd film is used as the fifth conductive thin film. Then, an AlNiNd film is formed to a thickness of 0.5 to 1.5 μm. The fifth conductive thin film may be an AlNiNd single layer or a laminate of AlNiNd and Mo, Mo alloy, or a refractory metal such as Cr. Further, in order to suppress reaction with the developer, nitrided AlNiNdN may be formed on AlNiNd.

For example, a Mo alloy is formed as a base by sputtering, and AlNiNd is continuously formed thereon. The film formation conditions are as follows: pressure is 0.2 to 0.5 Pa, DC power is 1.0 to 2.5 kW (in terms of power density, 0.17 to 0.43 W / cm ² ), and film formation temperature is from room temperature to room temperature. A range of about 180 ° C is applied.

    Next, a resist (not shown) corresponding to the data wiring 14, the bias wiring 15, and the light shielding layer 16 is formed in a tenth photolithography process. Then, the fifth conductive thin film is etched using the resist as a mask. When a multilayer film of AlNiNd and Mo is used as the fifth conductive thin film, the etching is performed, for example, by wet etching using a mixed solution of phosphoric acid, nitric acid, and acetic acid. Further, the etching solution is not limited to a mixed solution of phosphoric acid, nitric acid, and acetic acid, and other etching solutions can be used. Thereafter, the resist is removed. Thereby, the data wiring 14, the bias wiring 15, and the light shielding layer 16 are formed.

    Further, the data line 14 is formed in the contact hole CH2, and the data line 14 and the source electrode 6 are connected through the contact hole CH2. A bias wiring 15 is formed in the contact hole CH3, and the bias wiring 15 and the transparent electrode 12 are connected through the contact hole CH3. Further, the fifth conductive thin film is removed from the terminal portion. Through the above steps, the configuration shown in FIG.

    Thereafter, in order to protect the data wiring 14 and the bias wiring 15, a third passivation film 17 and a fourth passivation film 18 are sequentially formed so as to cover them. For example, a SiN film is used as the third passivation film 17 and a planarization film is used as the fourth passivation film 18.

    Next, a resist (not shown) for forming the contact hole CH5 is formed by an eleventh photolithography process. Then, using the resist as a mask, the third passivation film 17 and the fourth passivation film 18 are etched. Thereafter, the resist is removed. Thereby, the third passivation film 17 and the fourth passivation film 18 on the wiring conversion pattern 23 are removed, and the contact hole CH5 is formed. In the contact hole CH5, the second passivation film 13 and the wiring conversion pattern 23 are exposed. Further, the wiring conversion pattern 23 is exposed in the contact hole CH4 inside the contact hole CH5.

Here, the etching is performed by dry etching using plasma of a mixed gas of CF ₄ and O ₂ . Further, the etching gas is not limited to the mixed gas of CF ₄ and O ₂ , and other etching gases can be used. Note that a planarizing film having photosensitivity may be used as the fourth passivation film 18. Thereby, in the eleventh photolithography process, the fourth passivation film 18 can be patterned by exposure / development processing without using a resist.

    Next, a sixth conductive thin film to be the terminal 22 is formed on the fourth passivation film 18. A sixth conductive thin film is buried in the contact holes CH4 and CH5. As the sixth conductive thin film, a transparent conductive film such as amorphous ITO is used to ensure reliability. In the present embodiment, a transparent conductive film is used as the terminal 22, but two layers of a conductive film and a transparent conductive film may be used in order to obtain good contact with the wiring conversion pattern 23 and the like.

    Next, a terminal-shaped resist (not shown) is formed by a twelfth photolithography process. Then, the sixth conductive thin film is etched using the resist as a mask. Here, the etching is performed by, for example, wet etching using oxalic acid. Thereafter, the resist is removed. Thereby, the terminal 22 is formed. Further, terminals 22 are formed in the contact holes CH4 and CH5, and the wiring conversion pattern 23 and the terminals 22 are electrically connected through the contact holes CH4 and CH5. Thereafter, the ITO is crystallized by annealing. Through the above steps, the structure shown in FIG. 4 and FIG. 5 or FIG. 6 is obtained, and the TFT substrate is completed.

    In the method for manufacturing a TFT substrate provided in the photosensor according to the present embodiment, the nitrogen-containing semiconductor layer 11 a is formed on the p-type semiconductor layer 11. Thereby, it is possible to suppress diffusion of In or the like of the transparent conductive film forming the transparent electrode 12 into the semiconductor active layer constituting the photodiode 100. In addition, it is possible to realize a large photosensor with a good S / N ratio even in a state where the amount of incident light is small while suppressing a decrease in quantization efficiency of the photodiode 100.

    In the present embodiment, the nitrogen-containing semiconductor layer 11a is formed as the diffusion preventing layer. However, a layer containing oxygen may be formed. That is, oxygen may be contained on the transparent electrode 12 side of the p-type semiconductor layer 11. In this case, for example, surface treatment of the formed p-type semiconductor layer 11 is performed in an atmosphere containing oxygen plasma to form a diffusion prevention layer. Of course, like the nitrogen-containing semiconductor layer 11a, the formation of the semiconductor active layer and the formation of the diffusion prevention layer may be performed in the same apparatus.

    In this embodiment, the TFT substrate is manufactured by twelve photolithography processes, but the TFT substrate can be manufactured by eleven photolithography processes. Specifically, the second and fourth photolithography processes can be performed by one photolithography process, and the photolithography process can be reduced by one time. That is, the island formation of the semiconductor layer 4 and the ohmic contact layer 5 and the formation of the source electrode 6, the drain electrode 7, and the ohmic contact layer 5 can be performed by one photolithography process.

    In this case, first, the ohmic contact layer 5 is formed, and then the second conductive thin film is formed thereon. Then, a resist having a two-stage film thickness is formed on the second conductive thin film. Specifically, a thick film resist pattern is formed on the source electrode 6 and the drain electrode 7 to be formed later. Then, a thin film resist pattern is formed on the channel region to be formed later. A resist is not formed on other regions. Then, using the resist as a mask, the semiconductor layer 4, the ohmic contact layer 5, and the second conductive thin film are etched. Thereafter, the thin film resist pattern is removed, and the ohmic contact layer 5 is etched using the thick film resist pattern as a mask. Thereafter, the thick film resist pattern is removed. Thereby, the source electrode 6, the drain electrode 7, and the channel region are formed.

    Note that a multi-tone mask capable of realizing three levels of exposure levels of an exposed area, an intermediate exposed area, and an unexposed area may be used for forming a resist having a two-stage film thickness. The multi-tone mask includes a halftone mask and a gray tone mask. By using a multi-tone mask, a resist having the above two-stage film thickness can be formed by one exposure.

    In the present embodiment, the gate insulating film 3 around the substrate is removed using the resist pattern formed in the third photolithography process, but the present invention is not limited to this. For example, the peripheral gate insulating film 3 may be removed after the source electrode 6 and the drain electrode 7 are formed. Further, after the ohmic contact layer 5 is formed, the ohmic contact layer 5, the semiconductor layer 4, and the gate insulating film 3 around the substrate may be removed simultaneously. Further, in the step of forming the contact hole CH1, the first passivation film 8 and the gate insulating film 3 may be removed. It is desirable that the etching be performed under etching conditions that reduce dry etching damage to the drain electrode 7.

    In the present embodiment, the third conductive thin film 28 is formed as the lower electrode 25 on the contact hole CH1, and the photodiode 100 is formed thereon. However, the present invention is not limited to this. For example, the drain electrode 7 may be shared with the lower electrode 25, and the photodiode 100 may be formed in the contact hole CH1 opened on the drain electrode 7. Furthermore, the third conductive thin film 28 may be formed as the lower electrode 25 on the contact hole CH1 opened in the drain electrode 7, and the photodiode 100 may be formed in the contact hole CH1.

Embodiment 2
Hereinafter, the present invention will be specifically described with reference to the drawings illustrating embodiments of the present invention. In the present embodiment, a high-concentration oxygen-containing conductor layer 12a is provided as a diffusion prevention layer instead of the nitrogen-containing semiconductor layer 11a. Other configurations, manufacturing methods, and the like are the same as those in the first embodiment, and thus description thereof is omitted or simplified as appropriate. FIG. 11 is a cross-sectional view showing a configuration of a TFT substrate provided in the photosensor according to the present embodiment. 11 is a cross-sectional view taken along the line IV-IV in FIG. That is, FIG. 11 is a cross-sectional view at the same location as FIG.

    Since the structure below the lower electrode 25 of the photodiode 100 is the same as that of the first embodiment, the description thereof is omitted. On the lower layer of the lower electrode 25, a photodiode 100 having a three-layer structure in which an n-type semiconductor layer 9, an i-type semiconductor layer 10, and a p-type semiconductor layer 11 are sequentially stacked is formed. A transparent electrode 12 is formed on the photodiode 100.

    The transparent electrode 12 has a high-concentration oxygen-containing conductor layer 12 a as a diffusion prevention layer at the interface with the p-type semiconductor layer 11. That is, the high-concentration oxygen-containing conductor layer 12a is formed on the p-type semiconductor layer 11 side of the transparent electrode 12. The high-concentration oxygen-containing conductor layer 12a is a layer that contains more oxygen than the vicinity of the center of the film thickness of the transparent electrode 12. In other words, the high-concentration oxygen-containing conductor layer 12 a is a layer having an oxygen composition ratio higher than the central oxygen composition ratio in the film thickness direction of the transparent electrode 12. The layers above the second passivation film 13 are the same as those in the first embodiment, and the description thereof is omitted.

    In the TFT substrate provided in the photosensor according to the present embodiment, the transparent electrode 12 has a high-concentration oxygen-containing conductor layer 12 a at the interface with the p-type semiconductor layer 11. For this reason, diffusion of In or the like into the p-type semiconductor layer 11 can be suppressed. In addition, it is possible to realize a large photosensor with a good S / N ratio even in a state in which the quantization efficiency of the photodiode 100 is suppressed and the amount of incident light is small.

    In the present embodiment, the high concentration oxygen-containing conductor layer 12a containing a large amount of oxygen is taken as an example of the diffusion preventing layer, but a layer containing a large amount of nitrogen may be used. That is, a layer containing nitrogen may be formed on the transparent electrode 12 on the p-type semiconductor layer 11 side. Furthermore, a layer containing a large amount of zinc may be used as the diffusion preventing layer. Specifically, a layer having a zinc composition ratio higher than the central zinc composition ratio in the film thickness direction of the transparent electrode 12 may be formed on the p-type semiconductor layer 11 side of the transparent electrode 12.

    Next, a method for manufacturing a TFT substrate provided in the photosensor according to this embodiment will be described.

The n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 constituting the photodiode 100 are formed in the same manner as in the first embodiment. Then, a transparent conductive film is formed as a fourth conductive thin film on the p-type semiconductor layer 11. Here, an amorphous transparent conductive film is formed as the transparent conductive film. The amorphous transparent conductive film is formed by a sputtering method using a target such as IZO, ITZO, ITO, ITSO, for example. The film forming conditions are as follows: the pressure is 0.3 to 0.6 Pa, the DC power is 3 to 10 kW (in terms of power density, 0.65 to 2.3 W / cm ² ), and the Ar flow rate is 8.45 × 10 ^−2. ˜2.535 × 10 ⁻¹ Pa · m ³ / s (= 50 to 150 sccm) and oxygen flow rate of 1.69 × 10 ^{−3 to} 3.38 × 10 ⁻³ Pa · m ³ / s (= 1 to 2 sccm) ), The film forming temperature is in the range of room temperature to about 180 ° C.

    During the formation of the amorphous transparent conductive film, the oxygen flow rate changes. Specifically, the oxygen flow rate at the initial stage of film formation is set higher than the oxygen flow rate in the middle of the film formation of the amorphous transparent conductive film. For example, a large oxygen flow rate is set until the film thickness reaches about 5 nm to 10 nm. In this manner, the oxygen content is increased, and the high-concentration oxygen-containing conductor layer 12a is formed under the amorphous transparent conductive film. The change in the oxygen flow rate may be a step change or a ramp change. Moreover, the change of oxygen content is not limited to the case where it changes with oxygen flow rates.

    Next, a resist (not shown) is formed by a sixth photolithography process, and is etched and patterned using, for example, oxalic acid. Thereby, the transparent electrode 12 having the high-concentration oxygen-containing conductor layer 12a is formed. Since the subsequent manufacturing steps are the same as those in the first embodiment, the description thereof is omitted.

In the present embodiment, varying the oxygen flow rate, etc. in order to increase the oxygen content of the p-type semiconductor layer 11 side of the transparent electrode 12, in addition to O ₂ in the initial stage of deposition to the nitrogen-containing N ₂ may be added. That is, a transparent conductive film that becomes the transparent electrode 12 may be formed by adding a gas containing nitrogen at the initial stage of film formation. Furthermore, when forming a layer containing a large amount of zinc, a film containing a material containing more zinc than in the middle of the film formation is formed at the initial stage of film formation to prevent diffusion under the transparent conductive film serving as the transparent electrode 12. A layer may be formed. Specifically, in order to increase the zinc content in the initial layer, the film is formed to a thickness of 5 nm to 10 nm using a target containing a large amount of zinc such as IZO or ITZO. Thereafter, a film may be formed using another target such as ITO to form a laminated film. Furthermore, two types of targets may be provided in one film formation chamber.

Embodiment 3
Hereinafter, the present invention will be specifically described with reference to the drawings illustrating embodiments of the present invention. In the present embodiment, a silicide layer 20 is provided as a diffusion prevention layer instead of the nitrogen-containing semiconductor layer 11a. Other configurations, manufacturing methods, and the like are the same as those in the first embodiment, and thus description thereof is omitted or simplified as appropriate. FIG. 12 is a cross-sectional view showing a configuration of a TFT substrate provided in the photosensor according to the present embodiment. 12 is a cross-sectional view taken along the line IV-IV in FIG. That is, FIG. 12 is a cross-sectional view at the same location as FIG.

    Since the structure below the lower electrode 25 of the photodiode 100 has the same shape as that of the first embodiment, the description thereof is omitted. A photodiode 100 having a three-layer stacked structure in which an n-type semiconductor layer 9, an i-type semiconductor layer 10, and a p-type semiconductor layer 11 are sequentially stacked is formed on the lower electrode 25. A silicide layer 20 is formed on the p-type semiconductor layer 11. The silicide layer 20 is a reaction product layer of a refractory metal and a semiconductor layer material. A transparent electrode 12 is formed on the silicide layer 20. That is, the silicide layer 20 is formed between the semiconductor active layer constituting the photodiode 100 and the transparent electrode 12. The layers above the second passivation film 13 are the same as those in the first embodiment, and the description thereof is omitted.

    In the TFT substrate provided in the photosensor according to the present embodiment, a silicide layer 20 is formed between the transparent electrode 12 and the p-type semiconductor layer 11. Thereby, diffusion of In or the like from the transparent electrode 12 to the p-type semiconductor layer 11 can be suppressed. In addition, it is possible to realize a large photosensor with a good S / N ratio even in a state in which the quantization efficiency of the photodiode 100 is suppressed and the amount of incident light is small.

    Next, with reference to FIG. 13, a method for manufacturing a TFT substrate provided in the photosensor according to the present embodiment will be described. FIG. 13 is a cross-sectional view showing a method for manufacturing a TFT substrate.

    The n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 constituting the photodiode 100 are formed in the same manner as in the first embodiment. Then, a refractory metal film 19 is formed on the p-type semiconductor layer 11 by sputtering. For example, a Cr film is used as the refractory metal film 19. Then, a Cr film is formed to 100 nm. By the above process, the configuration shown in FIG.

    Then, heat treatment is performed in a state where the p-type semiconductor layer 11 and the refractory metal film 19 are in contact with each other, and a silicide layer 20 is formed between the p-type semiconductor layer 11 and the refractory metal film 19. The heat treatment temperature is set to 250 ° C., for example. Thereafter, the refractory metal film 19 is removed by etching. Etching is performed, for example, by wet etching using a mixed solution of nitric acid and cerium ammonium nitrate. Thereby, the silicide layer 20 is exposed to the surface. Further, the etching solution is not limited to a mixed solution of nitric acid and cerium ammonium nitrate, and other etching solutions can be used. In addition to wet etching, other etching methods can also be used. By the above process, the configuration shown in FIG.

    Next, a transparent conductive film is formed as a fourth conductive thin film on the silicide layer 20. Here, an amorphous transparent conductive film is formed as the transparent conductive film. Then, a resist (not shown) is formed by a sixth photolithography process, and etching is performed using, for example, oxalic acid, and patterning is performed. Thereby, the transparent electrode 12 is formed.

    Next, a resist (not shown) for the photosensitive region of the photodiode 100 is formed on the transparent electrode 12 in a seventh photolithography process. Then, using the resist as a mask, the silicide layer 20, the n-type semiconductor layer 9, the i-type semiconductor layer 10, and the p-type semiconductor layer 11 are patterned by dry etching. Since the subsequent manufacturing steps are the same as those in the first embodiment, the description thereof is omitted.

    In the present embodiment, Cr is used as the refractory metal film 19, but any refractory metal that forms silicide such as W, Ti, or Mo can be used. Also, the heat treatment may be changed by a silicide formation process. Further, depending on the film formation conditions of the semiconductor layer surface and the refractory metal film 19, there is a case where the heat treatment may not be performed.

Embodiment 4
Hereinafter, the present invention will be specifically described with reference to the drawings illustrating embodiments of the present invention. In the present embodiment, the shape of the transparent electrode 12 is different from that of the first embodiment. Other configurations, manufacturing methods, and the like are the same as those in the first embodiment, and thus description thereof is omitted or simplified as appropriate. FIG. 14 is a plan view showing a configuration of a pixel of the TFT substrate according to the present embodiment. Since the cross-sectional structure is substantially the same as the above embodiment, only the portion related to the planar structure will be described below.

    An opening 21 is formed in the transparent electrode 12 formed on the photodiode 100. A plurality of openings 21 are formed for the transparent electrode 12 formed in one pixel. In other words, a plurality of openings 21 are formed for one transparent electrode 12 pattern. In a region connected to the bias wiring 15 through the contact hole CH3, a pattern larger than the formation margin of the contact hole CH3 is formed. In FIG. 14, the transparent electrode 12 has a rectangular pattern at a substantially central portion. A contact hole CH3 is formed inside the rectangular pattern and substantially in the center.

    In other areas, the transparent electrode 12 has a mesh pattern. That is, the transparent electrode 12 is provided with rectangular openings 21 in an array. The shape of the transparent electrode 12 is not limited to a mesh shape. For example, as shown in FIG. 15, the transparent electrode 12 may have a web shape, or may have a honeycomb shape or a radial shape. That is, the opening 21 may have a rectangular shape, a polygonal shape such as a trapezoidal shape, or a circular shape.

    In the TFT substrate provided in the photosensor according to the present embodiment, the transparent electrode 12 has a plurality of openings 21. By providing the opening 21, In or the like can be diffused in the lateral direction. Thus, by providing the diffusible region in the horizontal direction, the diffusion in the vertical direction can be suppressed. Then, diffusion of In or the like into the i-type semiconductor layer 10 beyond the p-type semiconductor layer 11 can be suppressed. As a result, it is possible to realize a large photosensor with a good S / N ratio even in a state in which the decrease in the quantization efficiency of the photodiode 100 is suppressed and the amount of incident light is small. Furthermore, in the incident light to the photodiode 100, different wavelength distributions can be set for the transparent electrode 12 and the opening 21, respectively, so that it is possible to suppress a sudden deterioration in quantization efficiency due to process variations such as film thickness.

1 insulating substrate, 2 gate electrode, 3 gate insulating film, 4 semiconductor layer,
5 ohmic contact layer, 6 source electrode, 7 drain electrode,
8 first passivation film, 9 n-type semiconductor layer, 10 i-type semiconductor layer,
11 p-type semiconductor layer, 11a nitrogen-containing semiconductor layer, 12 transparent electrode,
12a High-concentration oxygen-containing conductor layer, 13 Second passivation film,
14 data wiring, 15 bias wiring, 16 light shielding layer,
17 Third passivation film, 18 Fourth passivation film,
19 refractory metal film, 20 silicide layer, 21 opening, 22 terminal,
23 wiring conversion pattern, 24 wiring, 25 lower electrode, 26 scintillator,
27 gate wiring, 28 third conductive thin film,
CH1-CH5, CH7 contact hole, 100 photodiode,
101 detection area, 102 frame area, 103 pixels, 104 gate drive circuit,
105 digital circuit, 106 readout circuit, 107 TFT,
200 image processing apparatus, 201 photosensor, 202 X-ray source, 203 subject,
204 X-ray

Claims (7)

A photodiode having a semiconductor active layer;
A photodiode electrode formed from a transparent conductive film;
A diffusion prevention layer that is formed between the semiconductor active layer and the photodiode electrode and prevents components of the photodiode electrode from diffusing into the semiconductor active layer;
The diffusion preventing layer has a higher oxygen composition ratio than the center oxygen composition ratio in the film thickness direction of the photodiode electrode, or a zinc composition higher than the center zinc composition ratio in the film thickness direction of the photodiode electrode. Photosensor with a ratio.   The photosensor according to claim 1, wherein the photodiode electrode has a plurality of openings for one pattern. A thin film transistor electrically connected to the photodiode;
A data line electrically connected to a source electrode of the thin film transistor;
A readout circuit that is electrically connected to the data wiring and reads out charges from the data wiring;
A digital circuit electrically connected to the readout circuit and having at least an A / D converter;
The photosensor according to claim 1, further comprising: a gate driving circuit that is electrically connected to a gate electrode of the thin film transistor and drives the thin film transistor.   The photosensor according to claim 1, further comprising a scintillator formed on a light incident side of the photodiode. A method of manufacturing a photosensor according to any one of claims 1 to 4,
Depositing the semiconductor active layer constituting the photodiode;
Forming a transparent conductive film that constitutes the photodiode electrode disposed opposite to the semiconductor active layer with the diffusion preventing layer interposed therebetween.   In the step of forming the transparent conductive film, the oxygen flow rate at the initial stage of film formation is increased on the semiconductor active layer compared to the oxygen flow rate in the middle of the film formation, and diffusion prevention is performed below the transparent conductive film. The method for producing a photosensor according to claim 5, wherein the layer is formed.   In the step of forming the transparent conductive film, on the semiconductor active layer, a film containing a material containing more zinc than in the middle of the film formation is formed at the initial stage of film formation, and the diffusion is performed below the transparent conductive film. The method for producing a photosensor according to claim 5, wherein a prevention layer is formed.

Images