JPH04206949A - Manufacture of soi substrate - Google Patents

Abstract

PURPOSE:To easily form a diffused layer into a buried layer formed already and positively form NPN or PNP transistor without increasing the processing time and man-hours by isolating elements after forming a P-type bufied layer on a P-type well formed previously. CONSTITUTION:For isolation, a polycrystalline silicon 8 is deposited deeper than buried layers 4, 6. A level-different part 12 is generated by the heat treatment at the surface of wafer. Before attaching a second silicon wafer 11, spin- on-glass 13 for burying the level-different part 12 is spin-coated to make flat the surface 14. The pin-on-glass 13 is sandwiched for attaching on a second wafer 11. Next, a composite wafer is placed upside down so that the wafer 1 is placed as the upper layer and the upper layer is ground and wrapped until the layer of polycrystalline silicon 8 appears and the prescribed thickness can be obtained. Islands 19 of PNP transistors having the P type buried layers can be formed without executing the diffusion process which requires accuracy such as formation of the P type buried layer into the N type buried layer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a method for forming n-type and p-type transistors for npn-type transistors and pnp-type transistors by bonding wafers together.
The present invention relates to a method for manufacturing a Sol substrate in which a bipolar active element having excellent heat resistance and high speed is formed by forming shaped buried layers respectively.

(Conventional technology) Bipolar transistors formed on silicon wafers are
If the emitter and collector of the pnp transistor are simultaneously diffused during the base diffusion (p-type diffusion) of the npn transistor 51, the collector region 52. The base region 53 and emitter region 54 are vertical, but the pnp transistor 55 has a collector region 56 . Base region 57. This results in a so-called lateral type transistor in which the emitter regions 58 are lined up horizontally. Due to the structure, such a transistor has a small current amplification factor hFE that determines high frequency characteristics, so it cannot be put to practical use. Therefore, if a pnp type transistor with good characteristics is required, the base region 53 of an n p 11 type transistor is Apart from p-type diffusion, p-type diffusion is performed for a buried layer of a pnp-type transistor to actively form a pnp-type transistor.

FIG. 8 shows a pnp type transistor with good characteristics as described in "2", in which a p-type buried layer 59 is formed by diffusion in an n-type buried layer. According to this, the base width becomes smaller,
H. can be made larger.

(Problem to be solved by the invention) However, 1. On the same chip, collectors and
(ηpn, pnp) in which the emitter and base regions are vertical
Forming a transistor increases the number of process steps, and requires forming a p-type diffusion for the buried layer of the pnp transistor on the second side of the already formed n-type buried layer, resulting in poor processing accuracy. required.

Also, triple diffused transistors are pnp type, n,
Although it can be made without distinction between p and n types, it has the disadvantage that it takes too much time.

The present invention makes it possible to easily form a diffusion layer in an already formed buried layer, and to actively form transistors for npn and I) np transistors without increasing processing time or man-hours. The purpose of the present invention is to provide a method for manufacturing SO■ substrates that makes it possible.

(Means for Solving the Problems) The present invention provides an n-type buried layer in the npn-type transistor forming area of a first silicon wafer, and a p-type buried layer with a p-type well as a lower layer in the pnp-type transistor forming area. The inter-element surface wafer of each buried layer is formed as an isolation region by a predetermined method, and spin-on glass is applied to the surface of the first silicon wafer on which each buried layer is formed, and then this is applied. After flattening, a second silicon wafer to be used as a substrate is pasted on the flattened surface, and the composite wafer after pasting is turned over so that the first silicon wafer is on the upper side, and the first silicon wafer is then pasted. (npn) by grinding the surface of the wafer and having an n-type region formed by the first silicon wafer as an upper layer and the n-type buried layer as a lower layer;
The present invention is characterized in that an island of transistors and an island of pnp transistors having the p-type region formed by the P well as an upper layer and the p-type buried layer as a lower layer are formed.

(Function) In an SOI substrate formed by bonding wells together, respective bonding regions are formed under the buried layers for the npn type and pnp transistors formed on the first wafer.

Therefore, when forming a transistor, treatments such as etching and oxidation must be performed on the buried layer which becomes the underlying layer by turning it over, and processing accuracy is required as in the case of forming the transistor by the growth method. According to the present invention, after forming a p-type buried layer below a p-type well (above the previously formed p-well) in the area where a pnp-type transistor is formed, isolation between elements is performed. Therefore, on the surface of the first wafer after pasting, an n-type region of the npn ) transistor and a p-type region of the p n p l□ transistor are already formed. Therefore, it is not necessary to form a well to match the buried layer that is the bottom layer of the well (and processing accuracy is not required. Also, by introducing a wafer-to-wafer bonding method, pre-formed wafers can be used. , the number of steps does not increase.

In addition, due to the heat treatment when forming each buried layer in the first silicon well, a step is created between the buried layer part and the oxide film part, and if this is attached to the second silicon wafer as it is, the inside of the wafer will be damaged. Since cavities are formed, in the present invention, a mirror finish is applied to improve the adhesion between both wafers.

(Example) Hereinafter, an example of the method for manufacturing an SOI substrate according to the present invention will be described in detail with reference to FIG. In addition, Figures 2 to 4
The figure is a more detailed 11° view for explaining FIG. 1 in detail, and FIG. 5 is an enlarged view of the completed board.

First, an n-type silicon wafer is prepared, and after forming an oxide film on the negative side, an opening 3 from which the oxide film is removed by photoetching is formed in the area where the pnp transistor will be formed, as shown in FIG. 1(a). do. In Figure 1(a), 1 is n
2 shows an oxide film.

Next, as shown in FIG. 1(b), the RL-type silicon wafer 1 is subjected to repeated processes such as photo-etching, impurity diffusion, and oxidation, which are detailed in FIG. Then, an n-type buried layer 4 is formed, and an impurity diffusion process is performed on the surface of the opening 3 to form a p-type buried layer 6 with a p-type well 5 as an underlying layer. An oxide film 7 is formed on the buried layer 4 and the p-type buried layer 6. The p-type buried layer 6 is formed by first forming a p-well 5 with a low impurity concentration, and then forming a p-type buried layer 6 with a high impurity concentration thereon.

Next, so-called separation is performed. The separation is made deeper than the buried layer 4°6 (polycrystalline silicon 8 is deposited).

This depth direction will determine the thickness of the subsequent transistor junction region. The separation process described in Section 2 is detailed in FIG.

Next, FIG. 1(d) shows a surface oxidation process for the next step. As a result, the oxide film 9 formed during the separation process is continuous with the oxide film 10 newly formed on the polycrystalline silicon 8, so that the entire silicon surface is covered with the oxide film.

Now, the wafer 1 on which the buried layer 4.6 is formed is shown in FIG.
The second silicon wafer 11 shown in f) is attached. However, on the wafer surface of FIG. 1(d),
In the process of forming the buried layers, a step portion 12 is formed between the buried portion and the oxide film portion due to heat treatment when forming each buried layer. Transfer this directly to the second silicon wafer 11
If the wafer is pasted, a cavity will be created inside the wafer, and when the diffusion layer is later formed, the distortion of the heat treatment will become large and the heat dissipation performance will be extremely deteriorated, causing characteristic deterioration.

Therefore, in this embodiment, before attaching the second silicon wafer 11 to the wafer 1 (FIG. 1d), the spin-on glass 13 filling the stepped portion 12 is spin-coded. The well 1 coated with the spin-on glass 13 is further assimilated with the underlying oxide films 9 and 10 by high-temperature annealing. The wafer 1 with the buried layer 4.6 formed thereon has its surface 1 coated with the spin-on glass 13.
4 is flattened. Subsequently, wafer 1 is spin-on
The glass 13 is sandwiched and attached to the second wafer 11.

In this pasting process, each wafer 1, 11 is first attached to H2O2-■
] Wash with 2SO4 solution to make it hydrophilic.

Thereafter, by heat treatment at 1100°C + 2 hr + N 2 , hydrogen bonding of the hydroxyl groups (-OH) is achieved (see Figure 1g). In addition, Fig. 1 (g)
In the figure, 15 is an oxide film with which the spin-on glass 13 is integrated.

Next, the composite wafer of FIG. 1(g) is turned over so that the wafer 1 is on the top layer, and is further ground and lapped from the top layer until a predetermined thickness is reached where the layer of polycrystalline silicon 8 appears. As a result, as shown in FIG. 1 (01), an npn l transistor island 18 having the n-type region 16 of the wafer 1 on the upper layer and the n-type buried layer 4 on the lower layer, and A pnp (pnp) transistor island 19 having the p-type region 17 in which the p-type well 5 formed in step 1) remains as an upper layer and the p-type buried layer 6 described above as a lower layer is formed.

The islands 18 formed as described above can create an npn type transistor. Furthermore, a pnp type transistor can be formed on the island j9.

In this embodiment, as described above, a p n p transistor island 19 having a p type buried layer is formed without performing a diffusion process that requires precision, such as forming a p type buried layer in an n type buried layer. form.

Next, the above wafer forming process will be explained in detail with reference to FIGS. 2 to 5.

FIG. 2 shows the process of forming the wafer 1 of FIG. 1(b). Figure 2 (a) is the same as Figure 1 (a);
- An opening 3 for a pnp (pnp) transistor has been formed in the oxide film 2 by etching. The wafer 1 with the openings 3 formed therein has a p-concentration as shown in FIG.
A shaped well 5 is formed. Once the p-type well 5 is formed to a sufficient thickness, the boron concentration is increased, and then the p-type buried layer 6 is formed.

The well 1 in which the p-type buried layer 6 has been formed is oxidized to eliminate the opening 3 portion. At this time, a stepped portion 12 is formed. Next, as shown in FIG. 2(d), an opening 2 is formed in the area where the npn transistor will be formed by photoetching.
1 is formed, and further, antimony is diffused into the wafer portion exposed through the opening 21 to form an n-swelled diffusion layer 4. The wafer 1 on which the n-swelled diffusion layer 4 is formed is oxidized to eliminate the openings 21.

Next, the separation process will be explained with reference to FIG.

In order to deposit polycrystalline silicon 8 (see FIG. 1C) deeper than each buried layer 4, 6,
Remove the surrounding area. For this reason, first, the oxide films other than the buried layers 4 and 6 are removed by silicon etching, leaving the oxide films 22 and 28 only on each of the buried layers 4 and 6 (the third
(See Figure C).

Next, by silicon anisotropic etching, as shown in FIG. 3(b).
As shown in FIG. 2, the n-type wafer 1 is removed to a predetermined depth. The surface of the wafer 1 in which the buried layers 4 and 6 have a +-1- shape is oxidized to form an oxide film 24 as shown in FIG. 3(c). Thereafter, by depositing polycrystalline silicon 8 in the valley portions, regions forming the basis of each island 18, 19 as shown in FIG. 1(C) are formed.

FIG. 4 shows the subsequent process of the composite wafer shown in FIG. 1 (5). The composite wafer in which each transistor island 18, 1.9 is formed forms a transistor junction region consisting of a base, emitter and collector, respectively.

FIG. 4(a) is the same as FIG. 1(5). The surface of the grinding and lapping is as shown in Fig. 4(b).
Surface oxidation is performed to form an oxide film 25. This oxide film 2
5 is an oxide film 1 with an integrated spin-on glass 13;
Integrate with 5. Next, on the oxide film 25, as shown in FIG.
As shown in FIG. 2, a predetermined opening is formed and, for example, by ion implantation, a p+ region 26 which becomes a base region is formed in the n-type region 16, and an n+ region which becomes a base region is formed in the p-type region 17.
Form region 27 (selective doping). Next, in the n-type region 16 an n p
n + region 2, which becomes the emitter region of the n t□ transistor
8 and an n+ region 29 which becomes a highly concentrated collector region, and a p-type region 27 formed in the p-type region 17 is formed.
A p+ region 30 is formed to serve as an emitter region of an np transistor. Furthermore, contact holes are formed as shown in FIG. 4(e), and the respective contacts are drawn out from these holes.

FIG. 5 shows the completed state of the bipolar transistor with each contact formed, and the npn transistor 18' is
n+ formed in the n-type region 16 constituting the collector region
A collector contact l-C is formed from the region 29, and a base contact B is formed from the p+ region 26 constituting the base region.
is formed, and an emitter contact E is formed from the n+ region 28 formed in the same p'' region 26. In addition, in the pnp transistor 19', the collector contact C is formed from the p-type region 17 forming the collector region. formed,
A base contact B is formed from the n+ region 27 constituting the base region formed in the p-type region 17, and
Emitter contacts l-E are formed from the p+ region 27 formed in the + region 27, respectively.

As described above, according to the method for manufacturing a Sol substrate according to this embodiment, vertical transistors can be formed without distinction between pnp type and npn type transistors.

Note that, as in the present invention, SOI by bonding wafers together
In the substrate manufacturing method, when forming the p-type buried layer 6 without forming the p-type well 5 in the step shown in FIG. will be formed by diffusion. However, in this case, during silicon etching (corresponding to FIG. 3a), an etching pattern as shown in FIG. , so extremely high precision is required. Therefore, = 1
4 = As in the embodiment, a p-type well 5 is provided below the p-type buried layer 6.
Patterning can be easily performed by using

Moreover, the p-type buried layer 6 can be formed without forming the p-type well 5.
In the case of forming a p-type well, there is a problem that the n-type buried layer 4 is diffused when the p-type well is formed later, but this problem does not arise in this embodiment.

(Effects of the Invention) As described above, according to the present invention, processing steps such as alignment with the buried layer are avoided, processing accuracy is not required,
It is possible to form vertical bipolar transistors with good high frequency characteristics (npn type and pnp type) in the same chip.

Furthermore, since it is formed by bonding wafers together, leakage current can be reduced due to its heat resistance.

[Brief explanation of the drawing]

FIG. 1 is a process diagram explaining the method for manufacturing a Sol substrate according to the present invention, FIGS. 2 to 5 are process diagrams illustrating the manufacturing process in FIG. 1 in further detail, and FIG. 6 is a process diagram different from this example. FIG. 7 is a block diagram showing a conventional bipolar transistor, and FIG. 8 is a block diagram showing another conventional bipolar transistor. 1-n-type silicon wafer, 4-n-type buried layer, 5-p-type well, 6-p-type buried layer, 8-.polycrystalline silicon, 1
1.--Second silicon wafer, 12-step portion, 13-
Spin-on-glass, 15-Oxide film, 16-N type region, 17-P type region, 18, 19-111 island. Patent applicant: Aisin Seiki Co., Ltd. Representative: Patent attorney Hiroshi Okawa Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] Using a first silicon wafer and a second silicon wafer serving as a substrate, an n-type buried layer is formed in the npn-type transistor formation area of the first silicon wafer, and a lower layer is formed in the pnp-type transistor formation area of the first silicon wafer. a first step of forming each p-type buried layer with a p-type well, and a second step of forming an inter-element surface wafer between the p-type buried layer and the n-type buried layer as an isolation region by a predetermined method. a third step of applying spin-on glass to the surface of the first silicon wafer on which each of the buried layers has been formed and then flattening it; and pasting a second silicon wafer on the flattened surface. A fourth step is to turn over the bonded composite wafer so that the first silicon wafer is on the upper side, and grind the surface of the first silicon wafer to remove the n-type region formed by the first silicon wafer. A fifth step of forming an island of npn transistors having the n-type buried layer as a lower layer in an upper layer, and an island of pnp transistors having the p-type region formed by the P well as an upper layer and the p-type buried layer as a lower layer. A method for manufacturing an SOI substrate, comprising: