JPH0420248B2 - - Google Patents
Info
- Publication number
- JPH0420248B2 JPH0420248B2 JP16976283A JP16976283A JPH0420248B2 JP H0420248 B2 JPH0420248 B2 JP H0420248B2 JP 16976283 A JP16976283 A JP 16976283A JP 16976283 A JP16976283 A JP 16976283A JP H0420248 B2 JPH0420248 B2 JP H0420248B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- forming
- laminate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 11
- 239000003985 ceramic capacitor Substances 0.000 claims description 10
- 238000001962 electrophoresis Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 description 10
- 238000007639 printing Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000725 suspension Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- DHEIAYDROZXXGS-UHFFFAOYSA-N ethanol;iodine Chemical compound [I].CCO DHEIAYDROZXXGS-UHFFFAOYSA-N 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
- ZFZQOKHLXAVJIF-UHFFFAOYSA-N zinc;boric acid;dihydroxy(dioxido)silane Chemical compound [Zn+2].OB(O)O.O[Si](O)([O-])[O-] ZFZQOKHLXAVJIF-UHFFFAOYSA-N 0.000 description 1
Description
【発明の詳細な説明】
本発明は積層セラミツクコンデンサの製造方
法、特にその内部電極の絶縁する方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer ceramic capacitor, and particularly to a method for insulating internal electrodes thereof.
積層セラミツクコンデンサは小形で大容量が得
られ、しかも信頼性の高いコンデンサとして実用
化が進んでいる。 Multilayer ceramic capacitors are small in size, have a large capacity, and are being put into practical use as highly reliable capacitors.
積層セラミツクコンデンサは一般にはセラミツ
ク生シート上に内部電極を印刷して、印刷したセ
ラミツク生シートを複数層積層圧着し、個別チヤ
ツプに分断した後、焼結するセラミツク生シート
法と誘電体ペーストと、内部電極ペーストを交互
に印刷して、積層し、個別チツプに分断した後焼
結する印刷法の二つの方法が行われている。 Multilayer ceramic capacitors generally use a ceramic raw sheet method in which internal electrodes are printed on a ceramic raw sheet, multiple layers of the printed ceramic raw sheet are laminated and crimped, separated into individual caps, and then sintered, and a dielectric paste. Two printing methods have been used in which internal electrode pastes are alternately printed, laminated, cut into individual chips, and then sintered.
いずれの方法でも、内部電極を印刷する際、対
向電極との絶縁および、内部電極が外部に露出し
ないように、内部電極を印刷する時に、第１図に
示すように外部および対向電極の間に空間がある
様な形状で印刷していた。 In either method, when printing the internal electrodes, in order to insulate them from the counter electrodes and prevent the internal electrodes from being exposed to the outside, as shown in Figure 1, between the external and counter electrodes, It was printed in a shape that seemed to have space.
この空間は印刷時の位置のバラツキ、積層時の
電極ズレ切断時の切断位置のバラツキ等を考慮す
ると、チツプの寸法に関係なく、最低でも400μm
が必要であつた。 This space should be at least 400 μm regardless of the chip size, considering variations in position during printing, electrode misalignment during stacking, and variations in cutting position when cutting.
was necessary.
従つてチツプの縦、横の寸法が小さくなると、
空間部分の割合が、電極面積に比らべて極端に小
さくなり、この結果、単位体積当りの容量を大き
くすることに限界が生生じていた。 Therefore, as the vertical and horizontal dimensions of the chip become smaller,
The proportion of the space becomes extremely small compared to the electrode area, and as a result, there is a limit to increasing the capacitance per unit volume.
すなわち、チツプの形状が１mm×２mmの場合、
内部電極の有効面積は0.2mm×1.2mm＝0.24mm2とな
り約25％程度になる。コンデンサの容量は、電極
面積に比例するため、単位体積当りの容量は極端
に低下することになる。 In other words, if the shape of the chip is 1 mm x 2 mm,
The effective area of the internal electrode is 0.2 mm x 1.2 mm = 0.24 mm 2 , which is about 25%. Since the capacitance of a capacitor is proportional to the electrode area, the capacitance per unit volume is extremely reduced.
このため、内部電極の面積を増加させ、第１図
のa1〜a3の距離を400μm以下にすると、対向電極
とのシート内部電極の外部への露出などが起り、
歩留を極端に低下させ、実用的でなくなつてしま
う。 For this reason, if the area of the internal electrode is increased and the distance between a 1 and a 3 in Fig. 1 is set to 400 μm or less, the sheet internal electrode may be exposed to the outside with respect to the counter electrode.
This will drastically reduce the yield and make it impractical.
本発明の目的はこのような問題を解決し、形状
が小さくても単位体積当りの容量を低下させるこ
となく、しかも、歩留り良く、量産性のある、積
層セラミツクコンデンサの製造方法を提供するも
のである。 The purpose of the present invention is to solve these problems and provide a method for manufacturing a multilayer ceramic capacitor that does not reduce the capacitance per unit volume even if the capacitor is small in size, has a high yield, and can be mass-produced. be.
すなわち本発明は誘電体材料と内部電極とが交
互に積層され、該内部電極と一層おきにそれぞれ
接続する２つの外部電極が形成された積層コンデ
ンサ型構造の積層体で積層方向に平行で、しかも
外部電極形成面と異なる２つの面に内部電極層が
露出している構造の積層焼結体を作製する工程
と、該積層体の一方の外部電極と該積層体の外側
に設置する電極板との間に直流電圧を印加し、電
気泳動法によつて前記内部電極露出面の一方の面
において、一層おきの内部電極層上とその近傍に
絶縁材料を形成する工程と、当該積層体の絶縁材
料を形成した面及び内部電極層と異なる内部電極
露出面及び内部電極層とその近傍に前記外部電極
と異なる外部電極と電極板との間に直流電圧を印
加し、電気泳動法によつて絶縁材料を形成する工
程と、当該絶縁材料が形成された積層体の外部電
極形成部近傍及び所定部分を積層方向に切断する
工程と、得られた積層体の絶縁材料が形成されて
いる２つの面に外部電極を形成する工程と、該積
層体の内部電極の露出している２つの面に絶縁層
を形成する工程とを具備することを特徴とする積
層セラミツクコンデンサの製造方法である。本方
法により単位体積当りの容量を低下させることな
く、また歩留りよく積層セラミツクコンデンサを
製造することができる。 That is, the present invention is a laminate having a multilayer capacitor type structure in which dielectric materials and internal electrodes are alternately laminated, and two external electrodes are connected to the internal electrodes at every other layer. A step of producing a laminated sintered body having a structure in which an internal electrode layer is exposed on two surfaces different from an external electrode forming surface, an external electrode on one side of the laminated body, and an electrode plate installed on the outside of the laminated body. applying a DC voltage between the steps and forming an insulating material on and in the vicinity of every other internal electrode layer on one of the exposed surfaces of the internal electrodes by electrophoresis; and insulating the laminate. A direct current voltage is applied between the electrode plate and the external electrode different from the external electrode to the exposed surface of the internal electrode different from the material formed surface and the internal electrode layer, and the internal electrode layer and its vicinity, and the insulation is insulated by electrophoresis. A step of forming the material, a step of cutting the laminate on which the insulating material is formed near the external electrode formation portion and a predetermined portion in the lamination direction, and two surfaces of the obtained laminate on which the insulating material is formed. This method of manufacturing a laminated ceramic capacitor is characterized by comprising the steps of: forming an external electrode on the laminate; and forming an insulating layer on two exposed surfaces of the internal electrode of the laminate. By this method, a multilayer ceramic capacitor can be manufactured with good yield without reducing the capacitance per unit volume.
次に本発明の詳細を図面と実施例によつて詳細
に説明する。 Next, details of the present invention will be explained in detail with reference to drawings and examples.
まず積層セラミツクコンデンサの製造方法とし
て一般的に行われている、グリーンシート法を用
いた場合の、本発明による積層コンデンサを製造
する工程について述べる。 First, a process for manufacturing a multilayer capacitor according to the present invention using the green sheet method, which is a commonly used method for manufacturing multilayer ceramic capacitors, will be described.
通常行われているように無機粉末と、有機バイ
ンダーと混合しスラリー化した後、ドクターブレ
ードなどの方法を用いて、グリーンシートを作
る。このグリーンシート上に内部電極をスクリー
ン印刷法などによつて形成する。 After mixing an inorganic powder with an organic binder to form a slurry as is commonly done, a green sheet is made using a method such as a doctor blade. Internal electrodes are formed on this green sheet by screen printing or the like.
内部電極を印刷したグリーンシートを所定の設
計に従つ積層圧着して、セラミツク生積層体を形
成する。 Green sheets on which internal electrodes are printed are laminated and pressure-bonded according to a predetermined design to form a raw ceramic laminate.
この生積層体第２図に示すような形状に切断す
る。第２図の中で１は印刷した内部電極、２はグ
リーンシート部分である。内部電極１は前後には
全面露出しているが、左右には一層毎に露出する
ように印刷、積層されている。 This green laminate is cut into a shape as shown in FIG. In FIG. 2, 1 is the printed internal electrode and 2 is the green sheet portion. The internal electrodes 1 are fully exposed on the front and back, but are printed and laminated so that they are exposed layer by layer on the left and right.
このように切断された積層体個片をセラミツク
の所定の条件で焼結した後、第３図に示すように
個片の左右に仮設電極３，３′を焼き付ける。 After the pieces of the laminate thus cut are sintered under predetermined ceramic conditions, temporary electrodes 3, 3' are baked on the left and right sides of the pieces, as shown in FIG.
この個片に対し、電気泳動法を適用し、第４図
に示すように、内部電極の一層毎に絶縁層４，
４′を形成する。 An electrophoresis method is applied to this individual piece, and as shown in FIG. 4, an insulating layer 4,
4' is formed.
絶縁層を形成した個片の断面図を第５図に示す
が絶縁層４，４′は一層毎に左右交互に形成され
ている。ここで１，１′は内部電極、２，２′は誘
電体である。 FIG. 5 shows a cross-sectional view of an individual piece on which an insulating layer is formed, and the insulating layers 4, 4' are formed alternately on the left and right sides of each layer. Here, 1 and 1' are internal electrodes, and 2 and 2' are dielectrics.
このような積層体を第６図に示すように点線に
添つて切断し、第７図に示すようなチツプを形成
する。このチツプの絶縁層をこのようなチツプの
内部電極の露出した左右の部分に絶縁層６，６′
を印刷、デツプ、電気泳動法などの方法を用いて
形成し、外部電極５，５′を焼付け第８図ａ，ｂ
に示すようなチツプコンデンサとする。 Such a laminate is cut along the dotted line as shown in FIG. 6 to form a chip as shown in FIG. 7. The insulating layers 6, 6' of this chip are placed on the exposed left and right parts of the internal electrodes of the chip.
The external electrodes 5, 5' are formed using methods such as printing, depth, and electrophoresis, and the external electrodes 5, 5' are baked to form the external electrodes 5, 5'.
Use a chip capacitor as shown in .
実施例 １
チタン酸バリウム系セラミツク粉末を有機バイ
ンダーとともに溶媒中に分散し、スラリーを作
る。これをドクターブレード法によつて25μm〜
200μmの均一な厚さのセラミツクグリーンシート
を作る。このセラミツクシートを60mm×40mmの矩
形に打ち抜き、その表面に内部電極となるパラジ
ウムペーストをスクリーン印刷法によつて印刷す
る。Example 1 Barium titanate ceramic powder is dispersed in a solvent together with an organic binder to form a slurry. This is 25 μm ~ 25 μm using the doctor blade method.
Make a ceramic green sheet with a uniform thickness of 200μm. This ceramic sheet is punched out into a 60 mm x 40 mm rectangle, and palladium paste, which will become the internal electrodes, is printed on the surface by screen printing.
このセラミツクシートを所定の枚数、積層圧着
し、積層体を形成する。この積層体を図３のよう
な形状に切断する。 A predetermined number of these ceramic sheets are laminated and pressure-bonded to form a laminate. This laminate is cut into a shape as shown in FIG.
この個片を1350℃で１時間焼結し、第４図に示
すような仮設電極を形成する。 This individual piece is sintered at 1350°C for 1 hour to form a temporary electrode as shown in FIG.
次に絶縁層を電気泳動法によつて形成するため
の懸濁液を作成する。ホウケイ酸亜鉛系結晶化ガ
ラス粉末30g、エタノール290ml、５％ヨウ素エ
タノール溶液10mlを高速ホモジナイザーで混合す
る。30分間超音波をかけた後、30分間静置して、
沈殿物を除去し、残りの懸濁液を使用する。 Next, a suspension for forming an insulating layer by electrophoresis is prepared. Mix 30 g of zinc borosilicate crystallized glass powder, 290 ml of ethanol, and 10 ml of 5% iodine ethanol solution using a high-speed homogenizer. After applying ultrasound for 30 minutes, let it stand for 30 minutes,
Remove the precipitate and use the remaining suspension.
前記積層焼結個の片面を粘着テープで被い、懸
濁液にねれるのを防いだ後前記懸濁液を満たした
容器に沈める。付着させたい面の前方に付着させ
たい面よりも大きい面積を持つ対向電極を沈め
る。対向電極板に直流電源のプラス端子を接続
し、図中の３，３′で示す仮設電極をマイナス端
子に接続し、20Vの電圧を300秒印加する。終了
後乾燥し、裏面の粘着テープを剥離した後、700
℃で10分間熱処理を行い、内部電極露出部分に付
着したガラスを焼き付ける。この処理を終つた個
片を第４図に示す。図中の２，２′は誘電体セラ
ミツクス１，１′は絶縁層を形成しない内部電極
露出部分、４，４′は内部電極上に形成した絶縁
層、３，３′は仮設電極を示す。 One side of the laminated sintered piece is covered with adhesive tape to prevent it from getting wet with the suspension, and then submerged in a container filled with the suspension. Submerge a counter electrode with a larger area than the surface you want to attach in front of the surface you want to attach. Connect the positive terminal of the DC power source to the counter electrode plate, connect the temporary electrodes shown as 3 and 3' in the figure to the negative terminal, and apply a voltage of 20 V for 300 seconds. After drying and peeling off the adhesive tape on the back, 700
Heat treatment is performed at ℃ for 10 minutes to burn off the glass attached to the exposed parts of the internal electrodes. Figure 4 shows the individual pieces that have undergone this treatment. In the figure, 2 and 2' are dielectric ceramics 1 and 1' that are exposed internal electrode portions on which no insulating layer is formed, 4 and 4' are insulating layers formed on the internal electrodes, and 3 and 3' are temporary electrodes.
次に同様な方法によつて反対側の面にも絶縁層
を形成するが、この場合は前回絶縁層を形成して
いない内部電極層の露出部分に絶縁層を形成す
る。 Next, an insulating layer is formed on the opposite side using the same method, but in this case, the insulating layer is formed on the exposed portions of the internal electrode layers on which no insulating layer was previously formed.
以上のように表側と裏側に絶縁層を形成した積
層体個片を第６図で示す点線の位置で切断する。
得られた積層チツプコンデンサを第７図に示す。
得られたチツプの絶縁層を形成した２つの面に外
部電極を形成する。 The individual pieces of the laminate with the insulating layers formed on the front and back sides as described above are cut at the dotted lines shown in FIG.
The obtained multilayer chip capacitor is shown in FIG.
External electrodes are formed on the two surfaces of the obtained chip on which the insulating layer is formed.
この積層チツプコンデンサのまだ絶縁層を形成
していない内部電極露出部分に、電気泳動法によ
つて同様に絶縁層を形成して、第８図ａに示すよ
うにする。 An insulating layer is similarly formed on the exposed portions of the internal electrodes of this multilayer chip capacitor on which no insulating layer has yet been formed, by electrophoresis, as shown in FIG. 8a.
このようにして形成した積層チツプコンデンサ
の外形寸法は縦10mm、横20mm、厚さ1.0mmであつ
た。 The outer dimensions of the multilayer chip capacitor thus formed were 10 mm long, 20 mm wide, and 1.0 mm thick.
積層数は20層、電極間距離は40μmであり容量
は3.0nFを得た。 The number of laminated layers was 20, the distance between electrodes was 40 μm, and the capacitance was 3.0 nF.
比較のため、従来の製造方法に従つた積層チツ
プコンデンサでは同一材料、同一積層数、同一形
状、同一電極間距離のもので0.4nFの容量しか得
られず、本発明の製造方法によつて、7.5倍の容
量が得られることが明らかである。 For comparison, multilayer chip capacitors made using the same material, the same number of laminated layers, the same shape, and the same distance between electrodes can only obtain a capacitance of 0.4 nF using the conventional manufacturing method, but with the manufacturing method of the present invention, It is clear that 7.5 times the capacity can be obtained.
実施例 ２
誘電体材料として、Pb（Fe1/2Nb1/2）O3−Pb
（Fe2/3Ｗ1/3）O3系材料、内部電極として銀・パ
ラジウム合金、絶縁材料としてホウケイ酸鉛系結
晶化ガラスを用い、実施例１と同様の方法に従つ
て積層チツプコンデンサを形成した。Example 2 Pb(Fe1/2Nb1/2)O 3 −Pb as dielectric material
A multilayer chip capacitor was formed in the same manner as in Example 1 using a (Fe2/3W1/3)O 3 based material, a silver-palladium alloy as the internal electrode, and a lead borosilicate crystallized glass as the insulating material.
形成した積層チツプコンデンサの外形寸法は縦
1.0mm、横3.0mm、厚さ1.0mmであり、積層数は30
層、電極間距離は30μmであり、容量として
277nFを得た。 The external dimensions of the formed multilayer chip capacitor are vertical.
1.0mm, width 3.0mm, thickness 1.0mm, number of layers is 30
The distance between layers and electrodes is 30 μm, and the capacitance is
Obtained 277nF.
比較のため従来の製造方法によつて形成した同
一寸法の積層チツプコンデンサは47nFであり、
本発明の製造方法によつて、同一形状で約６倍の
容量が得られた。 For comparison, a multilayer chip capacitor of the same size formed by the conventional manufacturing method has a value of 47nF.
By the manufacturing method of the present invention, approximately 6 times the capacity was obtained with the same shape.
以上示したように本発明の製造方法によつて、
従来の積層セラミツクコンデンサよりも単位体積
当りの容量を著しく大きくし、しかも歩留り良く
小形のチツプコンデンサを製造することが可能と
なつた。 As shown above, by the manufacturing method of the present invention,
It has become possible to manufacture small chip capacitors with significantly larger capacitance per unit volume than conventional multilayer ceramic capacitors and with high yield.
本発明は特に形状の小さい、又は縦横比の大き
いコンデンサに対して効果的に容量を大きく、し
かも歩留りを向上させることができる。 The present invention can effectively increase the capacity particularly for capacitors with a small shape or a large aspect ratio, and can also improve the yield.
なお本実施例では絶縁材料として結晶化ガラス
を焼付けたものを示したが、この他にも使用用途
によつてはエポキシ樹脂、シリコーン樹脂などの
高絶縁性有機樹脂を用いても同様の効果があるこ
とを確認した。 In this example, baked crystallized glass was used as the insulating material, but depending on the intended use, highly insulating organic resins such as epoxy resins and silicone resins may also be used to achieve the same effect. I confirmed that there is.
さらに、外部電極を形成した後の露出内部電極
部分の絶縁には必ずしも電気泳動法による必要は
なく、印刷法、デイツプ法、吹付法などを用い
て、絶縁層を形成しても同様の効果が得られる。
第８図ｂには印刷法によつて露出内部電極上に絶
縁層を形成した一例を示す。 Furthermore, it is not necessarily necessary to use electrophoresis to insulate the exposed internal electrode portions after forming the external electrodes; the same effect can be obtained by forming an insulating layer using a printing method, dipping method, spraying method, etc. can get.
FIG. 8b shows an example in which an insulating layer is formed on exposed internal electrodes by a printing method.
第１図は従来の積層セラミツクコンデンサの電
極印刷面の断面図である。第２図は生積層体を切
断した後の斜視図である。第３図は切断した個片
に仮電極を形成したものの斜視図である。第４
図、第５図はこれに電気泳動法によつて絶縁層を
形成したものの斜視図および断面図である。第６
図は絶縁層を形成した個片を切断する位置を示し
た斜視図であり、第７図は切断後のチツプの形状
を示す斜視図である。第８図ａ，ｂは本発明の製
造方法によつて製造した積層チツプコンデンサの
斜視図である。
図の中で、１，１′は内部電極、２，２′は誘電
体、３，３′は仮設電極、４，４′は絶縁層、５，
５′は外部電極、６，６′は絶縁層を示す。
FIG. 1 is a sectional view of the electrode printed surface of a conventional multilayer ceramic capacitor. FIG. 2 is a perspective view of the green laminate after it has been cut. FIG. 3 is a perspective view of the cut pieces with temporary electrodes formed thereon. Fourth
FIG. 5 is a perspective view and a cross-sectional view of the structure on which an insulating layer is formed by electrophoresis. 6th
This figure is a perspective view showing the position at which the individual pieces on which the insulating layer is formed is cut, and FIG. 7 is a perspective view showing the shape of the chip after cutting. 8a and 8b are perspective views of a multilayer chip capacitor manufactured by the manufacturing method of the present invention. In the figure, 1, 1' are internal electrodes, 2, 2' are dielectrics, 3, 3' are temporary electrodes, 4, 4' are insulating layers, 5,
5' is an external electrode, and 6 and 6' are insulating layers.
Claims (1)
該内部電極と一層おきにそれぞれ接続する２つの
外部電極が形成された積層コンデンサ型構造の積
層体で積層方向に平行で、しかも外部電極形成面
と異なる２つの面に内部電極層が露出している構
造の積層焼結体を作製する工程と、該積層体の一
方の外部電極と該積層体の外側に設置する電極板
との間に直流電圧を印加し、電気泳動法によつて
前記内部電極露出面の一方の面において、一層お
きの内部電極層上とその近傍に絶縁材料を形成す
る工程と、当該積層体の絶縁材料を形成した面及
び内部電極層と異なる内部電極露出面及び電極層
とその近傍に前記外部電極と異なる外部電極と電
極板との間に直流電圧を印加し、電気泳動法によ
つて絶縁材料を形成する工程と、当該絶縁材料が
形成された積層体の外部電極形成部近傍及び所定
部分を積層方向に切断する工程と、得られた積層
体の絶縁材料が形成されている２つの面に外部電
極を形成する工程と、該積層体の内部電極の露出
している２つの面に絶縁層を形成する工程とを具
備することを特徴とする積層セラミツクコンデン
サの製造方法。1 dielectric material and internal electrodes are alternately laminated,
A laminate having a multilayer capacitor type structure in which two external electrodes are formed which are connected to the internal electrodes at every other layer, and the internal electrode layers are exposed on two surfaces parallel to the stacking direction and different from the surface on which the external electrodes are formed. A process of producing a laminated sintered body having a structure in which a direct current voltage is applied between one external electrode of the laminated body and an electrode plate installed outside the laminated body, and the inner part is formed by electrophoresis. A step of forming an insulating material on and in the vicinity of every other internal electrode layer on one surface of the exposed electrode surface, and forming an internal electrode exposed surface and an electrode different from the surface on which the insulating material of the laminate is formed and the internal electrode layer. A step of forming an insulating material by electrophoresis by applying a DC voltage between the layer and the electrode plate and an external electrode different from the external electrode to the layer and its vicinity, and forming an insulating material outside the laminate on which the insulating material is formed. A step of cutting a predetermined portion near the electrode forming part in the stacking direction, a step of forming external electrodes on the two surfaces of the obtained laminate where the insulating material is formed, and a step of exposing the internal electrodes of the laminate. 1. A method for manufacturing a multilayer ceramic capacitor, comprising the step of forming an insulating layer on two surfaces of the capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16976283A JPS6060708A (en) | 1983-09-14 | 1983-09-14 | Method of producing laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16976283A JPS6060708A (en) | 1983-09-14 | 1983-09-14 | Method of producing laminated ceramic capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6060708A JPS6060708A (en) | 1985-04-08 |
| JPH0420248B2 true JPH0420248B2 (en) | 1992-04-02 |
Family
ID=15892376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16976283A Granted JPS6060708A (en) | 1983-09-14 | 1983-09-14 | Method of producing laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6060708A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2477069A1 (en) | 2011-01-14 | 2012-07-18 | Dainippon Screen Mfg. Co., Ltd. | Optical device, exposure apparatus and laser apparatus |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2895141B2 (en) * | 1990-02-06 | 1999-05-24 | 三井化学株式会社 | Manufacturing method of multilayer ceramic capacitor |
| CN101128895B (en) * | 2005-05-26 | 2010-09-01 | 株式会社村田制作所 | Monolithic ceramic electronic component and method for manufacturing the same |
| KR101872531B1 (en) * | 2012-07-04 | 2018-06-28 | 삼성전기주식회사 | Multi-layer ceramic electronic part and method for manufacturing the same |
-
1983
- 1983-09-14 JP JP16976283A patent/JPS6060708A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2477069A1 (en) | 2011-01-14 | 2012-07-18 | Dainippon Screen Mfg. Co., Ltd. | Optical device, exposure apparatus and laser apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6060708A (en) | 1985-04-08 |
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