JPS59202618A - Method of producing laminated ceramic condenser - Google Patents

Method of producing laminated ceramic condenser

Info

Publication number
JPS59202618A
JPS59202618A JP7664383A JP7664383A JPS59202618A JP S59202618 A JPS59202618 A JP S59202618A JP 7664383 A JP7664383 A JP 7664383A JP 7664383 A JP7664383 A JP 7664383A JP S59202618 A JPS59202618 A JP S59202618A
Authority
JP
Japan
Prior art keywords
silver
electrodes
multilayer ceramic
electrode
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7664383A
Other languages
Japanese (ja)
Other versions
JPH0153497B2 (en
Inventor
日下部 健治
板倉 鉉
義男 飯田
徹 田村
黒田 孝之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7664383A priority Critical patent/JPS59202618A/en
Publication of JPS59202618A publication Critical patent/JPS59202618A/en
Publication of JPH0153497B2 publication Critical patent/JPH0153497B2/ja
Granted legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はハイフリットIC用及びプリント基板直付用の
8を層セラミックコンデンサの製造方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing an 8-layer ceramic capacitor for high frit ICs and for direct mounting on printed circuit boards.

従来例の構成とその問題点 積層セラミックコンデンサは、一般にセラミック誘電体
とパラジウム及び/または白金の薄膜層を交互に積層し
て得られる積層体に基づくものであり、内部の金属薄膜
が誘電体を挾持する形で並列回路を形成するように端部
の銀または銀−パラニ。
Conventional Structures and Problems Multilayer ceramic capacitors are generally based on a laminate obtained by alternately laminating ceramic dielectric and thin film layers of palladium and/or platinum, and the internal thin metal film covers the dielectric. Silver or silver-palani at the ends to form a parallel circuit in the form of a pinch.

ジウム合金電極と接続1−る構成をなしている。この積
層セラミックコンデンサに使用される誘電体の厚みは一
15〜100μm程度であり、このような薄い誘電体平
面に電極を設けて折りたたんだような構造をしている。
It has a configuration in which it is connected to a dium alloy electrode. The thickness of the dielectric used in this multilayer ceramic capacitor is about 15 to 100 μm, and the structure is such that electrodes are provided on a flat surface of such a thin dielectric and folded.

一般に、コンデンサの静電容量は、 C−ε8ε〇− でゐられされる。ここで、ε0は真空の誘電率、εは誘
電体の比誘電率、Sは電極面積、及びtは電極間距離を
示す。したがって、体積当りの容量を考えると、 C/ VOO−(yはコンデンサの体積)2 となり、厚みの2乗に反比例する。そこで、円板型のセ
ラミックコンデンサと積層セラミックコンデンサの体積
当りの容量を比較すると、積層セラミックコンデンサの
方が円板型セラミックコンデンサ、の厚みの約l/10
以下にすることが可能であるから、約100倍以上の容
置か同一体積で得ることができる。(なお、円板型セラ
ミックコンデンサでは強度的に厚みを薄くすることが不
可能だから・現在でlまSOOμm前後が限度である。
Generally, the capacitance of a capacitor is expressed as C-ε8ε〇-. Here, ε0 is the dielectric constant of vacuum, ε is the relative dielectric constant of the dielectric, S is the electrode area, and t is the distance between the electrodes. Therefore, considering the capacitance per volume, it becomes C/VOO-(y is the volume of the capacitor)2, which is inversely proportional to the square of the thickness. Therefore, when comparing the capacitance per volume of a disk-type ceramic capacitor and a multilayer ceramic capacitor, the thickness of the multilayer ceramic capacitor is approximately 1/10 of the thickness of the disk-type ceramic capacitor.
Since it is possible to obtain the same volume or about 100 times more volume. (Note that it is impossible to reduce the thickness of a disc-type ceramic capacitor in terms of strength; the current limit is around 1SOOμm.

9このようにg/F7セラミツクコンデンサは小型かつ
大静電容量を有するものであり、電子回路の小型化に適
合して将り、ざらに電極にスズ及び鉛の合金メッキをほ
どこすことにより、プリント基板への直付け、v)容易
にできるようになってきている。
9 In this way, g/F7 ceramic capacitors are small and have large capacitance, and are suitable for the miniaturization of electronic circuits. v) Direct attachment to printed circuit boards is becoming easier.

しかしナカら、このような積層セラミックコンデンサの
欠点もいくつかあり、その欠点の一つは、訊を体厚みを
薄くするために生ずる欠陥である。
However, there are some drawbacks to such multilayer ceramic capacitors, one of which is defects that occur due to the thinness of the capacitor.

すなわち、セラミック自身もともと多結晶体からなるも
ので、緻密な単結晶とは異なり、無数の気孔を有してい
る。このような気孔はまた均一な大きさではなく、大き
な気孔も存在する。この気孔は小さく均一分布化するこ
とは一つの課題であり、種々研究されてはいるが、未だ
十分とはいえない。
That is, ceramic itself is originally a polycrystalline body, and unlike a dense single crystal, it has countless pores. Such pores are also not of uniform size, and large pores also exist. It is one of the challenges to make these pores small and uniformly distributed, and although various studies have been conducted, it is still not sufficient.

このような気孔の及ぼす影響としては、耐湿性を弱くす
ることである。特lこ(ζニッケルあるいはスズー鉛合
金メッキなどにより、電解液を用いる工程において、電
解質の残存などが問題となったりする。電解質X7)T
15存すると、湿気η)再び浸透することに尖り絶縁抵
抗が低下することがある。また両端部の銀電極は通常銀
粒子、ガラスフリット微粒子、有機バインダ及び有機溶
剤よりなる電極ペーストを、焼結したセラミックチップ
に塗布・乾燥したものを800°C程度の電極焼付炉に
て焼付ける。そうすることによりセラミックと焼結した
銀粒子をガラスフリット成分にて結合しかつセラミック
内部のPdあるいはPd−Ptfli極とこの端面銀電
極の接合を計っている。しかしながら、この焼結しγこ
銀電極にも気孔が存在し、前記と同様にメッキ時におい
て電解質が浸透し、ガラスフリット成分が電解質により
溶解され端部電極とセラミツの り接着強度が低下し、信頼性が低下することになる。特
にこのような銀焼付電極の場合、焼付温度及びセラミッ
クとのなじみなどのfH限より、硼珪酸鉛系ガラスがガ
ラスフリットとして使用される場合が多く、これは酸性
のメッキ液に容易に漫され、外部電極固着力の低下の原
因となっていた。
The effect of such pores is to weaken moisture resistance. Special (Due to ζ nickel or tin-lead alloy plating, residual electrolyte may become a problem in processes that use electrolytes. Electrolyte X7) T
15. If moisture η) is present, the insulation resistance may decrease due to re-penetration. The silver electrodes at both ends are usually made by applying an electrode paste consisting of silver particles, glass frit particles, an organic binder, and an organic solvent to a sintered ceramic chip, drying it, and baking it in an electrode baking furnace at about 800°C. . By doing so, the ceramic and the sintered silver particles are bonded by the glass frit component, and the Pd or Pd-Ptfli electrode inside the ceramic is bonded to the end surface silver electrode. However, this sintered gamma silver electrode also has pores, and as mentioned above, the electrolyte penetrates during plating, and the glass frit component is dissolved by the electrolyte, reducing the bond strength between the end electrode and the ceramic glue, resulting in reliability. This will result in a decline in sexuality. Particularly in the case of such silver-baked electrodes, lead borosilicate glass is often used as the glass frit due to fH limitations such as baking temperature and compatibility with ceramics, which is easily contaminated by acidic plating solutions. , which caused a decrease in the adhesion force of the external electrode.

このようなことは製品としての信頼性を著しく損なうも
のであり、市場にて問題を発生することが少なくない。
Such a situation significantly impairs the reliability of the product and often causes problems in the market.

このため、特にメッキ電極を付与する積層セラミックコ
ンデンサについては注意を要したものであった。
For this reason, special attention must be paid to multilayer ceramic capacitors provided with plated electrodes.

発明の目的 本発明は上記従来の問題に対処すべく為されたもので、
外部電極固着力が大き、<、耐湿性の良好なメッキされ
た端部電極を有する積層セラミックコンデンサを製造す
ることを目的とするものである。
Purpose of the Invention The present invention has been made to address the above-mentioned conventional problems.
The object of the present invention is to manufacture a multilayer ceramic capacitor having plated end electrodes with high external electrode adhesion and good moisture resistance.

発明の構成 上記目的を達成するため、本発明の積層セラミックコン
デンサの製造方法は、クシ形状に電極層が交互に積層さ
れてなる磁器誘電体の両端部に銀または銀−パラジウム
合金電極を付与し、この磁器誘電体に嫌気性接着剤を含
浸させ、その後表面部に付着した余分の接着剤を除去後
、両端部の電極部にメッキをほどこしたものである。
Structure of the Invention In order to achieve the above object, the method for manufacturing a multilayer ceramic capacitor of the present invention includes applying silver or silver-palladium alloy electrodes to both ends of a ceramic dielectric material in which electrode layers are alternately laminated in a comb shape. This porcelain dielectric was impregnated with an anaerobic adhesive, and after removing the excess adhesive adhering to the surface, the electrodes at both ends were plated.

実施例の説明 以下、本発明の一実施例についで、図面に基づいて説明
する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

チタン酸バリウム71.4重量部、ジルコン酸バリウム
20.4重量部、チタン酸カルシウム7.4重量部、酸
化面’lEr0.2重量部、二酸化マンガン0.15重
量部、酸化タングステン0,25重量部及び酸化アルミ
ニウム0.25重jlよりなる混合粉末に対して、エチ
ルセルローズを主体とするバインダーを用いてスラリー
を作製し、40±2μmの厚みのシートをドクターブレ
ード法を用いて成形した。このシートを一定のサイズに
打抜いた後、パラジウム電極を印刷した。この電極印刷
済みのシートを電極がクシ形状になるように積重ねて圧
着しノこ後、8.6X1.&nmX0.69m+の大き
さに切断した。このチップを1370℃±20°Cで2
時間焼成して得た焼結体の両端面に銀ペーストをほどこ
し、800℃で焼付けた。このようにして作製された積
層体に嫌気性接着剤(商品名:ロックタイトPMS−1
0)を4℃にて1時間真空含浸した。その後セラミック
及びgM部電極などの表面上の余分の接着剤を遠心分離
しトリクロルエチレンで洗浄した。その後80°Cで1
5分完全硬化させた。ついで、両端部の銀電極部にバレ
ルメッキ法にてニッケルメッキを1〜2μm1さらにそ
の上にスズと鉛の合金メッキを1〜2μmはどこした。
71.4 parts by weight of barium titanate, 20.4 parts by weight of barium zirconate, 7.4 parts by weight of calcium titanate, 0.2 parts by weight of oxidized surface 'lEr, 0.15 parts by weight of manganese dioxide, 0.25 parts by weight of tungsten oxide. A slurry was prepared using a binder mainly composed of ethyl cellulose from a mixed powder of 0.25 g/l of aluminum oxide and 40±2 μm thick sheet was formed using a doctor blade method. After punching out this sheet to a certain size, palladium electrodes were printed. After stacking the electrode-printed sheets so that the electrodes are in a comb shape and pressing and sawing, 8.6X1. It was cut into a size of &nm x 0.69m+. This chip was heated at 1370℃±20℃ for 2
Silver paste was applied to both end faces of the sintered body obtained by firing for a period of time, and the sintered body was baked at 800°C. An anaerobic adhesive (product name: Loctite PMS-1) was applied to the thus produced laminate.
0) was vacuum impregnated at 4°C for 1 hour. Thereafter, excess adhesive on the surfaces of the ceramic and gM section electrodes was centrifuged and washed with trichlorethylene. Then 1 at 80°C
It was completely cured for 5 minutes. Next, the silver electrodes at both ends were plated with nickel to a thickness of 1 to 2 .mu.m by barrel plating, and then alloy plating of tin and lead was applied to a thickness of 1 to 2 .mu.m.

このときのメッキ液のPH(木葉イオン濃度)はニッケ
ルメッキ浴は約4、スズと鉛の合金メッキ浴は約l″c
′あった。
At this time, the PH (leaf ion concentration) of the plating solution is approximately 4 for the nickel plating bath and approximately 1''c for the tin and lead alloy plating bath.
'there were.

第1凶はこのようにして得られた本発明の積層セラミッ
クコンデンサを示し、図中(1)は磁器誘電体層、(2
)はパラジウム電極層、(3)は銀電極、(4)はニッ
ケルメッキ層、(5)はスズと鉛の合金メッキ層である
The first layer shows the multilayer ceramic capacitor of the present invention obtained in this way, in which (1) is the ceramic dielectric layer, (2
) is a palladium electrode layer, (3) is a silver electrode, (4) is a nickel plating layer, and (5) is a tin-lead alloy plating layer.

次表は本発明の方法に基づく積層セラミックコンデンサ
と、従来の方法に基づく接着剤含浸のない積層セラミッ
クコンデンサ(接着剤含浸以外は本発明方法と同一であ
る)の外部電極固着力の実測値−Cある。炭より明らか
なように、本発明によるものは外部電極のセラミックと
の接着が強固である。なお外部電極固着力はチップに0
.5順φのリード線をハンダ付けし、引張り強度試験機
にて垂直方向の引張り強度を測定しfコ。
The following table shows actual measured values of external electrode adhesion of a multilayer ceramic capacitor based on the method of the present invention and a multilayer ceramic capacitor without adhesive impregnation based on the conventional method (same as the method of the present invention except for adhesive impregnation). There is C. As is clear from charcoal, the material according to the present invention has strong adhesion to the ceramic of the external electrode. Note that the external electrode adhesion force is 0 to the chip.
.. Solder the lead wires of 5 order φ and measure the tensile strength in the vertical direction using a tensile strength tester.

表 (各30個の平均値) また、第2図は本発明の方法に基づく&層セラミックコ
ンデンサと、従来の方法に基づく接着剤含浸処理のない
積層セラミックコンデンサ(接着剤含浸処理以外は本発
明方法と同一である)の40℃、相対湿度95%中での
・50V印加時の耐湿特性の様子を示したものである。
Table (average value of 30 pieces each) Figure 2 shows a multilayer ceramic capacitor based on the method of the present invention and a multilayer ceramic capacitor without adhesive impregnation treatment based on the conventional method (except for the adhesive impregnation treatment). This figure shows the moisture resistance characteristics when 50V is applied at 40° C. and 95% relative humidity (same as the method).

第2図でaは本発明品の特性、bは従来品の特性である
。この第2図から明らかなように、本発明の方法に基づ
く積層セラミックコンデンサの耐湿特性は極めて安定し
ていることが明白である。
In FIG. 2, a shows the characteristics of the product of the present invention, and b shows the characteristics of the conventional product. As is clear from FIG. 2, it is clear that the moisture resistance of the multilayer ceramic capacitor based on the method of the present invention is extremely stable.

尚、上記実施例ではチタン酸バリウム、ジルコン酸バリ
ウム及びチタン酸カルシウムを主体とする磁器誘電体材
料を使用したが、他の誘電体材料に関しても悪用可能な
ことはgうまでもないことである。また、両端部に銀電
極をほどこした場合について説明したか、−一パラジウ
ム合金電極でもよいものである。また実施例ではニッケ
ルメッキ及びスズー鉛合金メッキについて説明したが、
金、パラジウム等の他の賃金属のメッキにおいても同様
の効果が確認されているし、無電解メッキ法を用いても
有効である。
Incidentally, in the above embodiment, a porcelain dielectric material mainly composed of barium titanate, barium zirconate, and calcium titanate was used, but it goes without saying that other dielectric materials can also be misused. Furthermore, although the case where silver electrodes are provided at both ends has been described, -1-palladium alloy electrodes may also be used. In addition, although nickel plating and tin-lead alloy plating were explained in the examples,
Similar effects have been confirmed in plating other metals such as gold and palladium, and electroless plating is also effective.

発明の効果 以上述べたように、本発明の方法によれば、メッキ電極
を設けた積層セラミックコンデンサにありがちな外部電
極固着力の低下、耐湿特性の不安定特性等といった問題
点を解決することかできる。
Effects of the Invention As described above, the method of the present invention solves the problems that tend to occur in multilayer ceramic capacitors provided with plated electrodes, such as a decrease in the adhesion of the external electrode and unstable moisture resistance characteristics. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法に基づく積層セラミックコンデンサ
の−gi切欠斜視図、第2図は本発明方法と従来方法に
基づく積層セラミックコンデンサの耐湿特性の比較図で
ある。 (1)・・・磁器誘電体層、(2)・・・電極層()(
ラジウム電極1り、(3)・・・銀電極、(4)・・・
ニッケルメッキ層、(5)・・・スズと鉛の合金メッキ
j− 代理人 、森本義弘
FIG. 1 is a -gi cutaway perspective view of a multilayer ceramic capacitor based on the method of the present invention, and FIG. 2 is a comparison diagram of the moisture resistance characteristics of multilayer ceramic capacitors based on the method of the present invention and the conventional method. (1)...Porcelain dielectric layer, (2)...Electrode layer ()(
1 radium electrode, (3)...silver electrode, (4)...
Nickel plating layer, (5)...Tin and lead alloy plating j- Agent, Yoshihiro Morimoto

Claims (1)

【特許請求の範囲】[Claims] 1、 クシ形状に屯極眉が交互に積属されてなる磁器誘
電体の両端部に銀または銀−パラジウム合金電極を付与
し、この磁器誘電体に嫌気性接着剤を含浸させ、その後
表面部に付着した余分の接着剤を除去後、両端部の電極
部にメッキをほどこした積層セラミックコンデンサの製
造方法。
1. Silver or silver-palladium alloy electrodes are applied to both ends of a porcelain dielectric material in which tunic poles are stacked alternately in a comb shape, this porcelain dielectric material is impregnated with an anaerobic adhesive, and then the surface portion is A method of manufacturing a multilayer ceramic capacitor in which the electrodes at both ends are plated after removing excess adhesive from the capacitor.
JP7664383A 1983-04-30 1983-04-30 Method of producing laminated ceramic condenser Granted JPS59202618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7664383A JPS59202618A (en) 1983-04-30 1983-04-30 Method of producing laminated ceramic condenser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7664383A JPS59202618A (en) 1983-04-30 1983-04-30 Method of producing laminated ceramic condenser

Publications (2)

Publication Number Publication Date
JPS59202618A true JPS59202618A (en) 1984-11-16
JPH0153497B2 JPH0153497B2 (en) 1989-11-14

Family

ID=13611063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7664383A Granted JPS59202618A (en) 1983-04-30 1983-04-30 Method of producing laminated ceramic condenser

Country Status (1)

Country Link
JP (1) JPS59202618A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6355527U (en) * 1986-09-30 1988-04-14
JPH01241809A (en) * 1988-03-23 1989-09-26 Nec Corp Laminated ceramic chip parts
JPH04250607A (en) * 1991-01-25 1992-09-07 Taiyo Yuden Co Ltd Chip-shaped electronic parts and their manufacture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935058A (en) * 1972-08-02 1974-04-01
JPS5123417A (en) * 1974-05-08 1976-02-25 Loctite Corp Takoseibutsupinnokaizensaretaganshinhoho
JPS5546644A (en) * 1978-09-29 1980-04-01 Nippon Technical Co Ltd Rotary preset channel selector
JPS5866321A (en) * 1981-10-15 1983-04-20 松下電器産業株式会社 Method of producing laminated ceramic condenser

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935058A (en) * 1972-08-02 1974-04-01
JPS5123417A (en) * 1974-05-08 1976-02-25 Loctite Corp Takoseibutsupinnokaizensaretaganshinhoho
JPS5546644A (en) * 1978-09-29 1980-04-01 Nippon Technical Co Ltd Rotary preset channel selector
JPS5866321A (en) * 1981-10-15 1983-04-20 松下電器産業株式会社 Method of producing laminated ceramic condenser

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6355527U (en) * 1986-09-30 1988-04-14
JPH0519942Y2 (en) * 1986-09-30 1993-05-25
JPH01241809A (en) * 1988-03-23 1989-09-26 Nec Corp Laminated ceramic chip parts
JPH0440849B2 (en) * 1988-03-23 1992-07-06 Nippon Electric Co
JPH04250607A (en) * 1991-01-25 1992-09-07 Taiyo Yuden Co Ltd Chip-shaped electronic parts and their manufacture
JPH0656824B2 (en) * 1991-01-25 1994-07-27 太陽誘電株式会社 Chip-shaped electronic component and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0153497B2 (en) 1989-11-14

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