JPH0420106U - - Google Patents
Info
- Publication number
- JPH0420106U JPH0420106U JP5832690U JP5832690U JPH0420106U JP H0420106 U JPH0420106 U JP H0420106U JP 5832690 U JP5832690 U JP 5832690U JP 5832690 U JP5832690 U JP 5832690U JP H0420106 U JPH0420106 U JP H0420106U
- Authority
- JP
- Japan
- Prior art keywords
- test
- signal
- control device
- process control
- execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004886 process control Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 7
- 230000000737 periodic effect Effects 0.000 description 1
Description
第1図はこの考案の一実施例によるプロセス制
御装置の試験装置のソフトウエア構成を示すブロ
ツク図、第2図は第1図の試験処理のソフトウエ
ア構成内容を詳細に示すブロツク図、第3図は第
1図におけるバイステーブル試験実行処理の詳細
を示すフローチヤート図、第4図は従来およびこ
の考案の試験装置を示すブロツク図、第5図は従
来の定周期管理によるソフトウエア構成の内容を
示すブロツク図、第6図は第5図における試験処
理の詳細を示すブロツク図、第7図は第6図にお
けるバイステーブルの構造を示す説明図、第8図
はタグ情報テーブルの構造を示す説明図、第9図
はバイステーブルテスト試験テーブルの構造を示
す説明図、第10図は模擬入力信号とバイステー
ブル入出力信号との関係を示す説明図である。
1はプロセス制御装置、2は試験装置、Sは信
号処理回路。なお、図中、同一符号は同一、また
は相当部分を示す。
FIG. 1 is a block diagram showing the software configuration of a test device for a process control device according to an embodiment of this invention, FIG. 2 is a block diagram showing details of the software configuration of the test process in FIG. 1, and FIG. The figure is a flowchart showing the details of the bistable test execution process in Fig. 1, Fig. 4 is a block diagram showing the conventional test equipment and the test equipment of this invention, and Fig. 5 is the content of the software configuration using conventional periodic control. FIG. 6 is a block diagram showing details of the test processing in FIG. 5, FIG. 7 is an explanatory diagram showing the structure of the bistable in FIG. 6, and FIG. 8 shows the structure of the tag information table. FIG. 9 is an explanatory diagram showing the structure of the bistable test test table, and FIG. 10 is an explanatory diagram showing the relationship between the simulated input signal and the bistable input/output signal. 1 is a process control device, 2 is a test device, and S is a signal processing circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
補正 平3.3.8
実用新案登録請求の範囲を次のように補正する
。Amendment 3.8.3.3 The scope of claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
プロセス制御装置の信号処理回路に対して試験
装置から試験信号を入力し、この試験信号に応じ
て上記信号処理回路から出力される状態信号を受
信し、この受信した状態信号と基準値とをそれぞ
れ比較して、上記プロセス制御装置の健全性を試
験するプロセス制御装置の試験装置において、高
速性が要求される上記試験信号の変更処理を行う
バイステーブル試験実行処理と上記試験信号の出
力処理とを短い周期で実行管理する実行手段と、
診断処理および試験処理を長い周期で実行管理す
る処理手段とを備えたことを特徴とするプロセス
制御装置の試験装置。[Claim for Utility Model Registration] A test signal is input from the test device to the signal processing circuit of the process control device, and a status signal output from the signal processing circuit is received in response to the test signal. A bistable test execution process that performs processing to change the test signal, which requires high speed, in a test device for a process control device that tests the health of the process control device by comparing the status signal and a reference value, respectively; Execution means for executing and managing the output processing of the test signal in a short cycle ;
1. A test device for a process control device, comprising processing means for executing and managing diagnostic processing and test processing in a long cycle.
Claims (1)
装置から試験信号を入力し、この試験信号に応じ
て上記信号処理回路から出力される状態信号を受
信し、この受信した状態信号と基準値とをそれぞ
れ比較して、上記プロセス制御装置の健全性を試
験するプロセス制御装置の試験装置において、高
速性が要求される上記試験信号の変更処理を行う
バイステーブル試験実行処理と上記試験信号の出
力処理とを短い周期で実行管理する実行手段と診
断処理および試験処理を長い周期で実行管理する
処理手段とを備えたことを特徴とするプロセス制
御装置の試験装置。 A test signal is input from the test device to the signal processing circuit of the process control device, a status signal output from the signal processing circuit is received in response to the test signal, and the received status signal and the reference value are respectively In comparison, in a test device for a process control device that tests the health of the process control device, a bistable test execution process that performs a change process of the test signal that requires high speed and an output process of the test signal are performed. 1. A test device for a process control device, comprising: an execution means for managing execution in short cycles; and a processing means for managing execution in long cycles.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5832690U JPH0420106U (en) | 1990-06-01 | 1990-06-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5832690U JPH0420106U (en) | 1990-06-01 | 1990-06-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0420106U true JPH0420106U (en) | 1992-02-20 |
Family
ID=31583834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5832690U Pending JPH0420106U (en) | 1990-06-01 | 1990-06-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0420106U (en) |
-
1990
- 1990-06-01 JP JP5832690U patent/JPH0420106U/ja active Pending
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