JPS607080U - microprocessor analyzer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the state of a data bus with an 8-bit configuration.
The figure shows an example of the trace display in Fig. 1, Fig. 3 is an explanatory diagram of the status of a 16-bit data bus, Fig. 4 shows an example of the trace display in Fig. 3, and Fig. 5 shows one of the proposals of this study. FIG. 6 is a block diagram showing the overall configuration of the embodiment, FIG. 6 is an example of trace display according to the present invention, FIG. 7 is a block diagram showing a specific example of the FIP in FIG. 5, and FIG. 8 is a block diagram showing the operation of FIG. 7. This is a time chart for explanation. 3...Personal module (PSM), 4.
...Front instruction index creation circuit (FIP), 5...
...Sample memory (SPM), 6...CP
U, 7...ROM, f3...RT0

Claims (1)

[Scope of utility model registration request] A function for tracing and displaying data bus movements of a microprocessor configured to interrupt a portion of an instruction fetch cycle of another instruction between an instruction fetch cycle of one instruction and an execution bus cycle following the instruction fetch cycle. A microprocessor analyzer comprising: a microprocessor analyzer comprising means for counting the number of instruction fetch cycles up to each first instruction fetch cycle corresponding to each execution bus cycle; processor analyzer.