JPH0418718B2 - - Google Patents
Info
- Publication number
- JPH0418718B2 JPH0418718B2 JP59033426A JP3342684A JPH0418718B2 JP H0418718 B2 JPH0418718 B2 JP H0418718B2 JP 59033426 A JP59033426 A JP 59033426A JP 3342684 A JP3342684 A JP 3342684A JP H0418718 B2 JPH0418718 B2 JP H0418718B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- misalignment
- solder resist
- component layout
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910000679 solder Inorganic materials 0.000 claims description 31
- 230000007547 defect Effects 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 238000004080 punching Methods 0.000 description 11
- 239000011889 copper foil Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電子機器に使用されるプリント配線板
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a printed wiring board used in electronic equipment.
従来例の構成とその問題点
近年、電子機器は軽薄短少という言葉で代表さ
れるように、小型・軽量化、高密度実装化がとど
まることなく進んでいる。このように高密度実装
を行うためのプリント配線板も、電子部品の自動
実装において高密度でしかも高密度配線が要望さ
れている。Conventional configurations and their problems In recent years, electronic devices have become smaller, lighter, and more densely packaged, as represented by the phrase "light, thin, short, and small." Printed wiring boards for performing such high-density mounting are also required to have high density and high-density wiring for automatic mounting of electronic components.
一般にプリント配線板は銅張積層板よりなり、
電子部品をリード線等により配線する代りに、銅
張積層板の銅箔部をエツチング除去し、所定の銅
泊による導電性回路のパターンを設け、さらに半
田付時に半田付けを必要としないランド以外の銅
泊部分及び積層板表面に半田の付着しないソルダ
ーレジストを通常スクリーン印刷で形成する。次
に、一般的には電子部品の挿入または装着する位
置を明示するロードマツプ、またはプリント配線
板へ電子部品を実装したのちに調整とかで修理等
で利用するサービスマツプ等の部品配置図をスク
リーン印刷で形成する。次いで電子部品を取り付
けるための貫通孔を金型を使用したパンチング加
工により銅箔のランド部内に設けることによりプ
リント配線板が構成されていた。 Printed wiring boards are generally made of copper-clad laminates.
Instead of wiring electronic components with lead wires, etc., the copper foil part of the copper-clad laminate is etched away, a conductive circuit pattern is provided with a specified copper foil, and furthermore, when soldering, other than lands that do not require soldering are used. A solder resist that does not adhere to solder is usually formed by screen printing on the copper foil portion and the surface of the laminate. Next, screen print a component layout diagram, such as a road map that generally shows the positions where electronic components are inserted or installed, or a service map that is used for adjustments or repairs after electronic components are mounted on a printed wiring board. to form. Next, a printed wiring board was constructed by providing through holes for attaching electronic components in the land portions of the copper foil by punching using a mold.
しかしながら、プリント配線板のベースとなる
銅張積層板はフエノール樹脂またはエポキシ樹脂
を紙に含浸させ、その含浸紙を複数枚重ね加熱加
圧して積層したものであり、プリント配線板の製
造工程における熱履歴または吸湿等により寸法が
変化する性質を有している。また、ソルダーレジ
ストおよび部品配置図をスクリーン印刷する場合
には一定のテンシヨンで張られたスクリーンをス
キージで加圧移動させるためスクリーンが伸びる
という性質を有している。上記の性質や、ソルダ
ーレジストとか部品配置図を所定の位置にスクリ
ーン印刷するためのスクリーン合せの正確さの度
合により、銅箔回路のパターンとソルダーレジス
トや部品配置図を完全に合致させることは困難で
あり、多少のずれが発生するのは普通である。 However, copper-clad laminates, which are the base of printed wiring boards, are made by impregnating paper with phenolic resin or epoxy resin, and then stacking multiple sheets of impregnated paper together under heat and pressure. It has the property of changing dimensions due to history, moisture absorption, etc. Furthermore, when screen printing a solder resist and a component layout diagram, the screen is stretched with a certain tension and moved under pressure with a squeegee, so the screen has the property of being stretched. Due to the above characteristics and the degree of accuracy of screen alignment for screen printing solder resist and component layout diagrams in predetermined positions, it is difficult to perfectly match the copper foil circuit pattern with solder resist and component layout diagrams. It is normal for some deviation to occur.
また、銅箔回路のランド部に部品取付溶貫通孔
を設ける場合も、銅箔回路と打抜用金型は別々の
工程で加工されるので銅箔回路のランドの位置と
貫通孔の位置も必ずしも合致するとは限らない。
そこで金型にパンチング用ガイドピンを設け、プ
リント配線板にもパンチング用ガイド孔を設け
て、パンチング時に金型のガイドピンにプリント
配線板をはめ込んでパンチングを行うが、この場
合、プリント配線板のガイド孔はボール盤等によ
り１孔ずつ明けるため、ガイド孔が必ずしも一定
の正確な位置にあけられるものではない。さら
に、前述のようにプリント配線板はその製造工程
により寸法変化を生じることやパンチング時の加
工温度のばらつきにも影響を受けるので、部品取
付用貫通孔は銅箔回路のランド中央位置からずれ
ることになる。 Also, when providing through-holes for mounting components on the lands of copper foil circuits, the copper foil circuits and the punching mold are processed in separate processes, so the positions of the lands and through-holes of the copper foil circuits are also different. They do not necessarily match.
Therefore, a guide pin for punching is provided in the mold, a guide hole for punching is also provided in the printed wiring board, and the printed wiring board is fitted into the guide pin of the mold during punching. Since the guide holes are drilled one by one using a drilling machine or the like, the guide holes are not necessarily drilled at fixed and accurate positions. Furthermore, as mentioned above, printed wiring boards undergo dimensional changes due to the manufacturing process and are also affected by variations in processing temperature during punching, so the through holes for mounting components may be shifted from the center position of the land of the copper foil circuit. become.
以上のように、ソルダーレジスト、部品配置図
のずれや、貫通孔のずれは多少の場合は許容され
るが、ずれが大きくなると半田付面積の低下によ
り、半田付接続の信頼性が悪くなるため半田付不
良となる。 As mentioned above, some misalignment of the solder resist, component layout, and through holes are acceptable, but if the misalignment becomes large, the solder area decreases and the reliability of the soldered connection deteriorates. This will result in poor soldering.
そこで、上記ソルダーレジスト、部品配置図、
貫通孔のずれの程度を知る必要があり、従来はル
ーペ、拡大鏡等により測定していた。しかしなが
ら、これらの方法では非常に工数がかかり、非能
率的であり、また精度の点でも良くなかつた。 Therefore, the above solder resist, parts layout diagram,
It is necessary to know the degree of deviation of the through hole, and conventionally this has been measured using a loupe, magnifying glass, etc. However, these methods require a lot of man-hours, are inefficient, and have poor accuracy.
発明の目的
本発明は上記従来の欠点に鑑み、ソルダーレジ
スト、部品配置図、貫通孔のずれの良否を容易に
判定することのできるプリント配線板を提供する
ことにある。OBJECTS OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a printed wiring board in which it is possible to easily determine whether or not the solder resist, component layout diagram, and through-hole misalignment are good or bad.
発明の構成
この目的を達成するために本発明のプリント配
線板は、ずれ不良の基準となる第１および第２の
導電性パターンを同心円状に設け、前記第１の導
電性パターンは、パンチング孔を囲む位置に設け
るとともに、第１の導電性パターンの内径を前記
パンチング孔の径と、パンチング孔のずれ不良の
基準となる寸法公差の２倍との和とし、かつ前記
第２の導電性パターンは、前記第１の導電性パタ
ーンと別体で第１の導電性パターンの外側に設け
るとともに、ソルダーレジストまたは部品配置図
は、その内径内に前記第２の導電性パターンを囲
むように設け、さらにそのソルダーレジストまた
は部品配置図の内径を前記第２の導電性パターン
の外径と、ソルダーレジストまたは部品配置図の
ずれ不良の基準となる寸法公差の２倍との和とし
たものである。Structure of the Invention In order to achieve this object, the printed wiring board of the present invention is provided with first and second conductive patterns concentrically arranged as a reference for misalignment, and the first conductive pattern has punched holes. and the inner diameter of the first conductive pattern is the sum of the diameter of the punched hole and twice the dimensional tolerance serving as a reference for misalignment of the punched hole, and the second conductive pattern is provided separately from the first conductive pattern and outside the first conductive pattern, and a solder resist or a component layout diagram is provided within the inner diameter of the solder resist so as to surround the second conductive pattern, Furthermore, the inner diameter of the solder resist or component layout diagram is the sum of the outer diameter of the second conductive pattern and twice the dimensional tolerance that serves as a reference for misalignment of the solder resist or component layout diagram.
これにより、パンチング孔、ソルダーレジスト
または部品配置図が基準となる寸法公差よりも大
きく一方向にずれた場合、第１の導電性パターン
がパンチング孔により欠除され、またソルダーレ
ジストまたは部品配置図下の導電性パターンが露
出することになり、ずれ不良と目視にて容易に判
定できる。 As a result, if the punching hole, solder resist, or component layout diagram deviates in one direction to a greater extent than the standard dimensional tolerance, the first conductive pattern is removed by the punching hole, and the solder resist or component layout diagram The conductive pattern will be exposed, making it easy to visually determine that the misalignment is defective.
なお、上記のずれ不良判定マークは小さい面積
のプリント配線板であれば１箇所に設ければ良い
が、大きな面積を有するプリント配線板の場合に
は２箇所以上設けることにより、ずれ不良の検出
において正確さが高まるものである。 Note that if the above-mentioned deviation defect determination mark is a printed wiring board with a small area, it is sufficient to provide it in one place, but in the case of a printed wiring board with a large area, by providing it in two or more places, it will be easier to detect deviation defects. This increases accuracy.
実施例の説明
以下、本発明の一実施例について図面を参照し
ながら説明する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示すプリント配線
板上のずれ不良判定マークを示す図である。同図
において１はパンチング孔、２ａはパンチング孔
１のずれ不良判定用で円孔２ｂを有する導電性パ
ターンである。３はソルダーレジスト、４は部品
配置図、５はこの部品配置図４のずれ不良判定用
の導電性パターンである。 FIG. 1 is a diagram showing a misalignment defect determination mark on a printed wiring board showing an embodiment of the present invention. In the figure, 1 is a punched hole, and 2a is a conductive pattern having a circular hole 2b for determining the misalignment of the punched hole 1. 3 is a solder resist, 4 is a component layout diagram, and 5 is a conductive pattern for determining misalignment of the component layout diagram 4.
ここで、パンチング孔１のずれ不良判定用の導
電性パターン２ａがソルダーレジスト３のずれ不
良判定用導電性パターンをかねており、パンチン
グ孔１の外側に同心円環状に設けている。そし
て、さらにその外側に同心円環状の部品配置図４
のずれ不良判定用の導電性パターン５を設けてい
る。 Here, the conductive pattern 2a for determining misalignment of the punched hole 1 also serves as a conductive pattern for determining misalignment of the solder resist 3, and is provided in a concentric ring shape outside the punched hole 1. Further, on the outside thereof, a concentric ring-shaped parts layout diagram 4
A conductive pattern 5 for determining misalignment is provided.
上記ずれ不良判定マークは、通常適当な寸法の
ワークサイズに切断された銅張積層板の銅箔面に
エツチングレジストを印刷形成し、露出した不要
部の銅箔をエツチング除去することにより、銅箔
回路パターンを形成し、その後エツチングレジス
トを除去する、いわゆるエツチング工程によりパ
ンチング孔１のずれ不良判定用およびソルダーレ
ジスト３のずれ不良判定用導電性パターン２ａと
部品配置図４のずれ不良判定用の導電性パターン
５を同時に形成する。 The above-mentioned misalignment/defect judgment mark is usually made by printing an etching resist on the copper foil surface of a copper-clad laminate that has been cut into a workpiece size of an appropriate size, and etching away the exposed unnecessary copper foil. A so-called etching process in which a circuit pattern is formed and then the etching resist is removed is used to form a conductive pattern 2a for determining misalignment of the punched hole 1, a conductive pattern 2a for determining misalignment of the solder resist 3, and a conductive pattern for determining misalignment of the component layout diagram 4. A sexual pattern 5 is formed at the same time.
上記において、パンチング孔１の径Ｄに対し、
パンチング孔ずれ不良判定用導電性パターン２ａ
の円孔２ｂの径、すなわち導電性パターン２αの
内径はＤ＋2α（αはずれ不良の基準となる許容
値、通常0.1mm）とし、ソルダーレジスト３のず
れ不良判定用として導電性パターン２ａの外径
L1に対して、ソルダーレジスト３の外径がL1＋
2β（βはずれ不良の基準となる許容値、通常0.2
mm）とし、さらにその外側の同心円環状導電性パ
ターン５の外径L2に対して、部品配置図４の外
径がL2＋2γ（γはずれ不良の基準となる許容値、
通常0.2mm）とすることにより、ずれ不良判定用
マークが得られる。 In the above, for the diameter D of the punching hole 1,
Conductive pattern 2a for determining punching hole misalignment
The diameter of the circular hole 2b, that is, the inner diameter of the conductive pattern 2α, is D + 2α (α is the tolerance value that is the standard for misalignment, usually 0.1 mm), and the outer diameter of the conductive pattern 2a is used to judge the misalignment of the solder resist 3.
For L 1 , the outer diameter of solder resist 3 is L 1 +
2β (β is the tolerance value that is the standard for deviation defects, usually 0.2
mm), and furthermore, with respect to the outer diameter L 2 of the concentric annular conductive pattern 5 on the outside, the outer diameter of the component layout diagram 4 is L 2 + 2γ (γ is the tolerance value that is the standard for misalignment,
(usually 0.2 mm), a mark for determining misalignment can be obtained.
ここで、ソルダーレジスト３、または部品配置
図４が許容値以上にずれると、その下にある導電
性パターン２ａ，５が露出するため容易に目視で
検査できる。また、パンチング孔１のずれは、パ
ンチング孔１が導電性パターン２ａの一部を切断
すればずれ不良と判定できる。 Here, if the solder resist 3 or the component layout diagram 4 deviates by more than the allowable value, the conductive patterns 2a and 5 underneath are exposed and can be easily visually inspected. Further, the displacement of the punched hole 1 can be determined to be a defective displacement if the punched hole 1 cuts a part of the conductive pattern 2a.
なお、ソルダーレジスト３を外側円環とし、部
品配置図４を内側円環として形成しても同様の判
定ができることは明らかである。 Note that it is clear that the same determination can be made even if the solder resist 3 is formed as an outer ring and the component layout diagram 4 is formed as an inner ring.
なお、第２図に概略図を示すように、サイズの
大きなプリント配線板７にはその端部の２箇所以
上にずれ不良判定マーク８ａ，８ｂを設けること
により、ずれ不良の検出力は高くなる。 As shown in the schematic diagram in FIG. 2, the ability to detect misalignment defects can be increased by providing misalignment defect determination marks 8a and 8b at two or more locations on the ends of the large printed wiring board 7. .
発明の効果
以上のように本発明は、ずれ不良の基準となる
第１および第２の導電性パターンを同心円状に設
け、前記第１の導電性パターンは、パンチング孔
を囲む位置に設けるとともに、第１の導電性パタ
ーンの内径を前記パンチング孔の径と、パンチン
グ孔のずれ不良の基準となる寸法公差の２倍との
和とし、かつ前記第２の導電性パターンは、前記
第１の導電性パターンと別体で第１の導電性パタ
ーンの外側に設けるとともに、ソルダーレジスト
または部品配置図は、その内径内に前記第２の導
電性パターンを囲むように設け、さらにそのソル
ダーレジストまたは部品配置図の内径を前記第２
の導電性パターンの外径と、ソルダーレジストま
たは部品配置図のずれ不良の基準となる寸法公差
の２倍との和としたもので、パンチング孔のずれ
により導電性パターンの切断の有無や、ソルダー
レジストや部品配置図のずれにより下地の導電性
パターンの露出の有無を同時に一見するだけで、
ずれの寸法公差内かあるいはずれ不良かも容易に
判定することができるものであり、その実用的効
果は大なるものである。Effects of the Invention As described above, in the present invention, first and second conductive patterns serving as a reference for misalignment defects are provided concentrically, and the first conductive pattern is provided at a position surrounding a punched hole. The inner diameter of the first conductive pattern is the sum of the diameter of the punched hole and twice the dimensional tolerance that is a criterion for misalignment of the punched hole, and the second conductive pattern has an inner diameter of the first conductive pattern. A solder resist or component layout diagram is provided outside the first conductive pattern separately from the conductive pattern, and a solder resist or component layout diagram is provided to surround the second conductive pattern within the inner diameter of the solder resist or component layout diagram. The inner diameter in the figure is the second
It is the sum of the outer diameter of the conductive pattern and twice the dimensional tolerance, which is the standard for misalignment of the solder resist or component layout diagram. At a glance, you can check whether or not the underlying conductive pattern is exposed due to misalignment of the resist or component layout.
It is possible to easily determine whether the deviation is within the dimensional tolerance or whether the deviation is defective, and its practical effects are great.
第１図は本発明のプリント配線板上のずれ表示
マークの一実施例を示す平面図、第２図は本発明
のプリント配線板のずれ表示マーク位置を示す一
例の斜視図である。
１……パンチング孔、２ａ……導電性パター
ン、３……ソルダーレジスト、４……部品配置
図、５……導電性パターン、８ａ，８ｂ……ずれ
不良判定マーク。
FIG. 1 is a plan view showing an embodiment of the deviation indicating mark on the printed wiring board of the present invention, and FIG. 2 is a perspective view of an example showing the position of the deviation indicating mark on the printed wiring board of the present invention. 1... Punching hole, 2a... Conductive pattern, 3... Solder resist, 4... Component layout diagram, 5... Conductive pattern, 8a, 8b... Misalignment defect determination mark.
Claims (1)
性パターンを同心円状に設け、前記第１の導電性
パターンは、パンチング孔を囲む位置に設けると
ともに、その第１の導電性パターンの内径を前記
パンチング孔の径と、パンチング孔のずれ不良の
基準となる寸法公差の２倍との和とし、かつ前記
第２の導電性パターンは、前記第１の導電性パタ
ーンと別体で第１の導電性パターンの外側に設け
るとともに、ソルダーレジストまたは部品配置図
は、その内径内に前記第２の導電性パターンを囲
むように設け、さらにそのソルダーレジストまた
は部品配置図の内径を前記第２の導電性パターン
の外径と、ソルダーレジストまたは部品配置図の
ずれ不良の基準となる寸法公差の２倍との和とし
たプリント配線板。1 First and second conductive patterns that serve as a reference for misalignment defects are provided concentrically, and the first conductive pattern is provided at a position surrounding the punched hole, and the inner diameter of the first conductive pattern is The diameter of the punched hole is the sum of twice the dimensional tolerance serving as a reference for misalignment of the punched hole, and the second conductive pattern is a first conductive pattern separate from the first conductive pattern. In addition to providing the solder resist or component layout outside the conductive pattern, the solder resist or component layout is provided within its inner diameter so as to surround the second conductive pattern, and the inner diameter of the solder resist or component layout is provided within the second conductive pattern. A printed wiring board that is the sum of the outer diameter of the pattern and twice the dimensional tolerance that is the standard for misalignment of the solder resist or component layout drawing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342684A JPS60186088A (en) | 1984-02-23 | 1984-02-23 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342684A JPS60186088A (en) | 1984-02-23 | 1984-02-23 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60186088A JPS60186088A (en) | 1985-09-21 |
| JPH0418718B2 true JPH0418718B2 (en) | 1992-03-27 |
Family
ID=12386224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3342684A Granted JPS60186088A (en) | 1984-02-23 | 1984-02-23 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60186088A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012057458A1 (en) * | 2010-10-26 | 2012-05-03 | 한국과학기술정보연구원 | Method and device for supporting the global commercialization of technology |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0294690A (en) * | 1988-09-30 | 1990-04-05 | Nippon Seiki Co Ltd | Printed wiring board |
| JP2775819B2 (en) * | 1989-03-21 | 1998-07-16 | アイシン精機株式会社 | Multi-layer printing alignment method by screen printing |
| JPH0440570U (en) * | 1990-07-31 | 1992-04-07 | ||
| CN102498223A (en) | 2009-09-18 | 2012-06-13 | 科诺科菲利浦公司 | Mercury removal from water |
| JP5777220B2 (en) * | 2012-05-16 | 2015-09-09 | 株式会社伸光製作所 | Printed wiring board manufacturing method and printed wiring board using the same |
| JP6183103B2 (en) * | 2013-09-26 | 2017-08-23 | 大日本印刷株式会社 | Position detection electrode substrate for touch panel, touch panel using the same, and image display device using the touch panel |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425226A (en) * | 1977-07-27 | 1979-02-26 | Kobe Steel Ltd | Method of treating waste gas from pickling process |
-
1984
- 1984-02-23 JP JP3342684A patent/JPS60186088A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425226A (en) * | 1977-07-27 | 1979-02-26 | Kobe Steel Ltd | Method of treating waste gas from pickling process |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012057458A1 (en) * | 2010-10-26 | 2012-05-03 | 한국과학기술정보연구원 | Method and device for supporting the global commercialization of technology |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60186088A (en) | 1985-09-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |