JP2570174B2 - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JP2570174B2
JP2570174B2 JP11911294A JP11911294A JP2570174B2 JP 2570174 B2 JP2570174 B2 JP 2570174B2 JP 11911294 A JP11911294 A JP 11911294A JP 11911294 A JP11911294 A JP 11911294A JP 2570174 B2 JP2570174 B2 JP 2570174B2
Authority
JP
Japan
Prior art keywords
hole
inner layer
wiring board
printed wiring
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11911294A
Other languages
Japanese (ja)
Other versions
JPH07326867A (en
Inventor
聡 隅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11911294A priority Critical patent/JP2570174B2/en
Publication of JPH07326867A publication Critical patent/JPH07326867A/en
Application granted granted Critical
Publication of JP2570174B2 publication Critical patent/JP2570174B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は多層プリント配線板に関
し、特に多層プリント配線板に発生するレジンスミアを
検出する為に用いられる多層プリント配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board used for detecting a resistance smear generated in a multilayer printed wiring board.

【0002】[0002]

【従来の技術】従来の多層プリント板は、図4(A),
(B)に示すように基材7の両面のスルーホール4の周
囲に形成された外層ランド3と基材7の内部に形成され
た内層ランド5を有し、外層ランド3と内層ランド5は
スルーホール4のスルーホールめっき層9により所定の
位置で接続されている。
2. Description of the Related Art A conventional multilayer printed board is shown in FIG.
As shown in (B), the base material 7 has an outer layer land 3 formed around the through holes 4 on both surfaces of the base material 7 and an inner layer land 5 formed inside the base material 7. The through holes 4 are connected at predetermined positions by a through hole plating layer 9.

【0003】このように構成された多層プリント配線板
は、層間接続を行う場合、ドリル加工によりスルーホー
ル穴あけを行い、その後銅めっきによりスルーホールめ
っき層9を形成しているが、このとき、図5(A),
(B)に示すように、穴壁の内層ランド5の露出面への
融解コーティングによるレジンスミアを発生し、スルー
ホールめっき層9と内層ランド5との接続面積を減少さ
せ、部品を実装する半田付け工程での熱衝撃等により接
続不良を起こしていた。
[0003] In the multilayer printed wiring board thus configured, when performing interlayer connection, a through-hole is drilled by drilling, and then a through-hole plating layer 9 is formed by copper plating. 5 (A),
As shown in FIG. 3B, the surface of the inner wall 5 of the hole wall is exposed to the melt coating by melting coating, thereby reducing the connection area between the through-hole plating layer 9 and the inner land 5 and soldering for mounting the component. Connection failure was caused by thermal shock or the like in the process.

【0004】このように、多層プリント配線板の内層ラ
ンド5とスルーホールめっき層9との接続部分に発生す
るレジンスミア10は、多層プリント配線板の外層面か
らは検出できなかった。そこで、まず、多層プリント配
線板を破壊し表面あるいは裏面より目的の内層まで削り
込み、内層ランド5を露出させる。次に、拡大鏡等の測
定器を用いて内層ランド5とスルーホールめっき層9の
接続部分を観察し、レジンスミア10が認められた場合
にはその長さを測定し、その測定結果をJISC501
4の3.9.2項の判定基準(レジンスミアの許容値は
穴円周の25%以下)に基いて良品,不良品の判定を行
っていた。
As described above, the resistance smear 10 generated at the connection portion between the inner land 5 and the through-hole plating layer 9 of the multilayer printed wiring board cannot be detected from the outer layer surface of the multilayer printed wiring board. Therefore, first, the multilayer printed wiring board is destroyed and cut from the front surface or the back surface to the target inner layer to expose the inner layer land 5. Next, the connection portion between the inner layer land 5 and the through-hole plating layer 9 is observed using a measuring instrument such as a magnifying glass, and when the resistance smear 10 is recognized, the length is measured.
The non-defective product and the defective product were determined based on the criterion described in 3.9.2 of item 4 (the tolerance of the resistance smear was 25% or less of the hole circumference).

【0005】[0005]

【発明が解決しようとする課題】この従来のレジンスミ
アの検出方法では、多層プリント配線板を破壊し内層ラ
ンドまで削り込んでレジンスミアの長さを測定して検査
を行うので検査に多大な工数と日程が必要であるという
問題点があった。その為、製品の納期に支障がでるとい
う問題点が生じていた。
In the conventional method for detecting a resist smear, the multilayer printed wiring board is destroyed and cut down to the inner layer land to measure the length of the resist smear, and the inspection is performed. There was a problem that it was necessary. For this reason, there has been a problem that the delivery date of the product is hindered.

【0006】本発明の目的は、レジンスミアの検査が容
易で、工数と日程を要せず、納期短縮が可能な検査パタ
ーンを備える多層プリント配線板を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer printed wiring board having an inspection pattern capable of easily inspecting a resistance smear, requiring no man-hour and a schedule, and shortening a delivery time.

【0007】[0007]

【課題を解決するための手段】本発明の多層プリント配
線板は、レジンスミア検出用スルーホールと、このレジ
ンスミア検出用スルーホールに接続しこのレジンスミア
検出用スルーホールを中心に等角度で放射状に外側に伸
びる内層パターンと、この内層パターンの終端部に接続
する内層ランドと、この内層ランドに接続する外層との
貫通スルーホールまたは非貫通スルーホールとを有す
る。
SUMMARY OF THE INVENTION A multilayer printed wiring board according to the present invention comprises a through hole for detecting a resistance smear, and a radially outward connection at an equal angle around the through hole for detecting a resistance smear. It has an extending inner layer pattern, an inner layer land connected to the terminal end of the inner layer pattern, and a through-hole or a non-through through hole for an outer layer connected to the inner layer land.

【0008】[0008]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0009】図1(A),(B)は本発明の第1の実施
例の平面図およびそのA−A′線断面図である。本発明
の第1の実施例は、図1(A),(B)に示すように、
回路形成部以外の領域に、レジンスミア検出用のスルー
ホール4とこのスルーホール4を中心とし等角度で放射
状の位置にスルーホール2a〜2hを設け、内層面には
スルーホール2a〜2hのそれぞれに内層ランド5a〜
5h(図示せず)を配置し内層パターン6により内層ラ
ンド5a〜5hそれぞれをスルーホール4に接続する。
この時、スルーホール4には内層ランドを設けない。一
方、外層面にはスルーホール2a〜2hのそれぞれに接
続する外層ランド1とスルーホール4に接続する外層ラ
ンド3を配置する。
FIGS. 1A and 1B are a plan view and a sectional view taken along line AA 'of a first embodiment of the present invention. The first embodiment of the present invention, as shown in FIGS.
In a region other than the circuit forming portion, through holes 4 for detecting the resistance smear and through holes 2a to 2h are provided at radial positions at equal angles around the through holes 4, and the through holes 2a to 2h are formed on the inner layer surface. Inner layer land 5a ~
5 h (not shown) are arranged, and the inner layer lands 5 a to 5 h are connected to the through holes 4 by the inner layer pattern 6.
At this time, no inner layer land is provided in the through hole 4. On the other hand, an outer layer land 1 connected to each of the through holes 2a to 2h and an outer layer land 3 connected to the through hole 4 are arranged on the outer layer surface.

【0010】図2(A),(B)はそれぞれ設計基準に
基ずく外層パターンおよび内層パターン製造用フィルム
の平面図である。多層プリント配線板の回路形成能力が
回路幅0.1mm,回路間隔0.15mmとすると内層
回路を8方向に配置できるレジンスミア検出用のスルー
ホール4の最小穴径は次式で表される。
FIGS. 2A and 2B are plan views of a film for manufacturing an outer layer pattern and an inner layer pattern based on design criteria, respectively. Assuming that the circuit forming capability of the multilayer printed wiring board has a circuit width of 0.1 mm and a circuit interval of 0.15 mm, the minimum hole diameter of the through hole 4 for detecting the resistance smear in which the inner layer circuits can be arranged in eight directions is expressed by the following equation.

【0011】〔(回路幅+回路間隔)×方向数〕/円周
率=〔(0.1+0.15)×8〕/3.14 そこで、レジンスミア検出用のスルーホール4の径は、
この計算値以上のスルーホール径で、製品内に使用して
いて、かつレジンスミアの発生の有無を検査したいスル
ーホールの径を基に設定し、スルーホール2a〜2hの
穴径は、製造工程能力に応じた最小穴径以上に制定す
る。
[(Circuit width + circuit interval) × the number of directions] / pi = [(0.1 + 0.15) × 8] /3.14 Therefore, the diameter of the through hole 4 for detecting the resistance smear is:
With the diameter of the through hole larger than this calculated value, it is set based on the diameter of the through hole that is used in the product and to check for the occurrence of the resistance smear. Establish the minimum hole diameter according to.

【0012】一方、スルーホール4とスルーホール2a
〜2hの最小間隔は、次式で表される。
On the other hand, through hole 4 and through hole 2a
The minimum interval of 22h is represented by the following equation.

【0013】(外層ランド3の径+外層ランド1の径)
/2+回路間隔 まず、上記の設計基準に基いて作成された図2(B)に
示す内層パターン製造用フィルムを用いて内層の所定の
位置に内層ランド5と内層パターン6を形成し、プリプ
レグを介して片面に銅箔を有する基材を積み重ねて公知
の熱圧着手段で積層体を形成する。次に、同様に設計基
準に基いて作成された図2(A)に示す外層パターン製
造用フィルムを用いて外層ランド3の中心が内層パター
ン6の交差する位置に、外層パターン1が内層パターン
5と対応する位置に外層パターンを形成する。次に、そ
れぞれの外層ランド3,1の中心にスルーホール用の穴
開けを行った後、めっき工程を経て、内層パターン6と
接続するスルーホール4,内層パターン6を介してそれ
ぞれスルーホール4に接続するスルーホール2a〜2h
を形成した後、ソルダレジスト,文字印刷,外径加工を
施す。
(Diameter of outer layer land 3 + diameter of outer layer land 1)
First, an inner land 5 and an inner layer pattern 6 are formed at predetermined positions of an inner layer using a film for manufacturing an inner layer pattern shown in FIG. 2B created based on the above-described design criteria, and a prepreg is formed. The base material having a copper foil on one side is stacked on the substrate and a laminate is formed by a known thermocompression bonding means. Next, the outer layer pattern 1 is moved to the position where the center of the outer layer land 3 intersects the inner layer pattern 6 using the film for manufacturing an outer layer pattern shown in FIG. An outer layer pattern is formed at a position corresponding to the above. Next, after drilling holes for through holes at the centers of the outer layer lands 3 and 1, through a plating step, the through holes 4 are connected to the inner layer patterns 6, and the through holes 4 are respectively formed through the inner layer patterns 6. Through holes 2a to 2h to be connected
Then, solder resist, character printing, and outer diameter processing are performed.

【0014】次に、電気検査工程にてスルーホール4を
基準にしてスルーホール2a〜2hとの接続を検査す
る。この時、スルーホール4とスルーホール2a〜2h
全てが導通状態にある場合はレジンスミアの発生はな
く、スルーホール4は図4(A),(B)の状態であ
る。一方、スルーホール2aのみが断線している場合は
その部分にレジンスミアが発生していることを示し、レ
ジンスミアの長さはスルーホール4の円周の25%以下
といえる。この時のスルーホール4の状態は図5
(A),(B)の状態である。また、スルーホール2a
と2bが断線している場合はレジンスミアの長さはスル
ーホール4の円周の25%以上37.5%以下といえ
る。
Next, in the electrical inspection step, the connection with the through holes 2a to 2h is inspected with reference to the through hole 4. At this time, the through hole 4 and the through holes 2a to 2h
When all are in the conductive state, no resistance smear occurs and the through hole 4 is in the state shown in FIGS. 4A and 4B. On the other hand, if only the through-hole 2a is broken, it indicates that a resistance smear has occurred in that portion, and it can be said that the length of the resistance smear is 25% or less of the circumference of the through-hole 4. The state of the through hole 4 at this time is shown in FIG.
(A) and (B). Also, through hole 2a
2b is disconnected, the length of the resistance smear can be said to be 25% or more and 37.5% or less of the circumference of the through hole 4.

【0015】図3は本発明の第2の実施の断面図であ
る。第2の実施例は図3に示すように、第1の実施例の
貫通スルーホール2の代りに非貫通スルール8を2層に
形成し電気検査を両面より実施する。このため、第1の
実施例と同じ面積で検査パターンが設けられ、4層の多
層プリント配線板に対応させることが可能となる。
FIG. 3 is a sectional view of a second embodiment of the present invention. In the second embodiment, as shown in FIG. 3, a non-penetrating srule 8 is formed in two layers instead of the through-hole 2 of the first embodiment, and an electrical inspection is performed from both sides. Therefore, the inspection pattern is provided in the same area as that of the first embodiment, and it is possible to correspond to a four-layer multilayer printed wiring board.

【0016】[0016]

【発明の効果】以上説明したように本発明は、レジンス
ミア検査用のスルーホールを設け、このスルーホールを
中心として放射状に内層パターンを設け、この内層パタ
ーンの終端部に外層とのスルーホールを設けることによ
り、電気検査工程にてレジンスミアの発生の有無と、そ
の大きさを多層プリント配線板を破壊することなしに容
易に検出できるという効果がある。
As described above, according to the present invention, a through-hole for resistance smear inspection is provided, an inner layer pattern is provided radially around the through-hole, and a through-hole with the outer layer is provided at the end of the inner layer pattern. Accordingly, there is an effect that the presence or absence of the occurrence of the resistance smear and the size thereof can be easily detected without breaking the multilayer printed wiring board in the electrical inspection process.

【0017】また、電気検査工程で検査を実施するた
め、従来実施していたレジンスミアの検査工数が不要と
なるので、製品納期短縮にも貢献できるという効果があ
る。
In addition, since the inspection is performed in the electrical inspection process, the number of man-hours for inspection of the resistance smear, which has been conventionally performed, is not required, which contributes to shortening the delivery time of the product.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A),(B)は本発明の第1の実施例の平面
図およびそのA−A′線断面図である。
FIGS. 1A and 1B are a plan view and a sectional view taken along line AA ′ of a first embodiment of the present invention.

【図2】(A),(B)はそれぞれ設計基準に基ずく外
層パターンおよび内層パターン製造用フィルムの平面図
である。
FIGS. 2A and 2B are plan views of a film for manufacturing an outer layer pattern and an inner layer pattern based on design standards, respectively.

【図3】本発明の第2の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the present invention.

【図4】(A),(B)は従来の多層プリント配線板の
スルーホールの一例の平面図およびそのB−B′線断面
図である。
FIGS. 4A and 4B are a plan view of an example of a through hole of a conventional multilayer printed wiring board and a cross-sectional view taken along line BB 'of FIG.

【図5】(A),(B)は従来の多層プリント配線板の
レジンスミアの一例を説明する平面図およびそのC−
C′線断面図である。
FIGS. 5A and 5B are a plan view for explaining an example of a resistance smear of a conventional multilayer printed wiring board, and FIGS.
It is C 'line sectional drawing.

【符号の説明】[Explanation of symbols]

1,3 外層ランド 2,2a〜2h,4 スルーホール 5 内層ランド 6 内層パターン 7 基材 8 非貫通スルーホール 9 スルーホールめっき層 10 レジンスミア 1,3 outer layer land 2,2a-2h, 4 through hole 5 inner layer land 6 inner layer pattern 7 base material 8 non-through through hole 9 through hole plating layer 10 resistance smear

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 レジンスミア検出用スルーホールと、こ
のレジンスミア検出用スルーホールに接続しこのレジン
スミア検出用スルーホールを中心に等角度で放射状に外
側に伸びる内層パターンと、この内層パターンの終端部
に接続する内層ランドと、この内層ランドに接続するス
ルーホールとを有することを特徴とする多層プリント配
線板。
1. A through hole for detecting a resistance smear, an inner layer pattern connected to the through hole for detecting a resistance smear and extending radially outward at an equal angle around the through hole for detecting a resistance smear, and connected to a terminal end of the inner layer pattern. A multilayer printed wiring board comprising: an inner layer land to be formed; and a through hole connected to the inner layer land.
【請求項2】 前記内層ランドに接続するスルーホール
が外層との貫通スルーホールであることを特徴とする請
求項1記載の多層プリント配線板。
2. The multilayer printed wiring board according to claim 1, wherein the through hole connected to the inner layer land is a through hole with the outer layer.
【請求項3】 前記スルーホールが外層との非貫通スル
ーホールであることを特徴とする請求項1記載の多層プ
リント配線板。
3. The multilayer printed wiring board according to claim 1, wherein the through hole is a non-through through hole with an outer layer.
JP11911294A 1994-05-31 1994-05-31 Multilayer printed wiring board Expired - Fee Related JP2570174B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11911294A JP2570174B2 (en) 1994-05-31 1994-05-31 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11911294A JP2570174B2 (en) 1994-05-31 1994-05-31 Multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH07326867A JPH07326867A (en) 1995-12-12
JP2570174B2 true JP2570174B2 (en) 1997-01-08

Family

ID=14753222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11911294A Expired - Fee Related JP2570174B2 (en) 1994-05-31 1994-05-31 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP2570174B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060008021A (en) 2004-07-23 2006-01-26 삼성전자주식회사 A printed circuit board and a flat display device using the same

Also Published As

Publication number Publication date
JPH07326867A (en) 1995-12-12

Similar Documents

Publication Publication Date Title
US7889510B2 (en) Component-embedded board device and faulty wiring detecting method for the same
TWI399137B (en) Manufacture of thin wiring boards
JP2001053447A (en) Multilayer wiring board with built-in part and manufacturing method thereof
JPH04348595A (en) Method for repairing multilayer printed circuit board
US5266380A (en) Method and apparatus for visual verification of proper assembly and alignment of layers in a multi-layer printed circuit board
JP2570174B2 (en) Multilayer printed wiring board
US20010039727A1 (en) Manufacturing method for multilayer printed circuit board
JP4117390B2 (en) Manufacturing method of multilayer printed wiring board with cavity
JP3206635B2 (en) Multilayer printed wiring board
JP2003283145A (en) Method of inspecting misregistration of multilayer wiring board
JP2008028213A (en) Circuit board and inspection method therefor
JP2002198661A (en) Multilayer printed wiring board
JP2007059777A (en) Multilayered printed circuit board and method for manufacturing the same
JPH07243985A (en) Accuracy confirming method for printed wiring board
JP3077776B2 (en) Mechanism for detecting through hole position in manufacturing printed wiring board, printed wiring board, and method for manufacturing the same
JP4015900B2 (en) Method for manufacturing multilayer printed wiring board incorporating chip resistor
JP2712997B2 (en) Solder resist processing method in manufacturing printed wiring board
JPS6191992A (en) Printed circuit board
KR20230100286A (en) Manufacturing Method of Multi-layer Printed circuit Board and Multi-layer Printed circuit Board manufactured by the same
KR20140147398A (en) Method for manufacturing printed circuit board
KR20050038238A (en) Printed circuit board wherein a deviation between layers can examined
JPH05297049A (en) Pattern inspection method of printed wiring board
JPH04155891A (en) Manufacture of multilayer printed wiring board
JPH0661604A (en) Printed wiring board
JPH04247693A (en) Manufacture of printed-wiring board

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19960820

LAPS Cancellation because of no payment of annual fees