JPH05297049A - Pattern inspection method of printed wiring board - Google Patents

Pattern inspection method of printed wiring board

Info

Publication number
JPH05297049A
JPH05297049A JP4129969A JP12996992A JPH05297049A JP H05297049 A JPH05297049 A JP H05297049A JP 4129969 A JP4129969 A JP 4129969A JP 12996992 A JP12996992 A JP 12996992A JP H05297049 A JPH05297049 A JP H05297049A
Authority
JP
Japan
Prior art keywords
copper foil
pattern
hole
inspection
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4129969A
Other languages
Japanese (ja)
Inventor
Hidekazu Mizushima
英一 水嶋
Toshimichi Onishi
利道 大西
Naoki Tomizawa
直樹 富澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elna Co Ltd
Original Assignee
Elna Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elna Co Ltd filed Critical Elna Co Ltd
Priority to JP4129969A priority Critical patent/JPH05297049A/en
Publication of JPH05297049A publication Critical patent/JPH05297049A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Image Analysis (AREA)

Abstract

PURPOSE:To simply and automatically inspect the misalignment of a pattern on a printed wiring board by means of a continuity checker. CONSTITUTION:In individual processes such as a pattern formation process for a board main body 10a, a process for making a through hole and a process for filling a conductive paste, a check pattern 11 is formed in a blank part 10b on a board by using the same method as the processes. Said check pattern 11 is composed of the following: a first copper foil part 12 and a second copper foil part 13 which are formed on the surface side of the blank part at a prescribed interval; a third copper foil part 14 which is formed on the rear side in such a way that both ends correspond to the first and second copper foil parts 12, 13 continuously across them; through holes 15a, 15b which are made in positions to be used as the first and second copper foil parts; and a conductive paste 16 which is filled into the through holes. When the continuity or the continuity defect between the first and second copper foil parts 12, 13 is detected by means of a continuity checker, it is possible to inspect whether a misalignment of a circuit pattern or the like exists or not.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプリント配線板のパター
ン検査方法に関し、さらに詳しく言えば、導通チェッカ
ーによるショート・オープン検査にて回路パターンやス
ルーホールなどの位置ずれの有無を検査し得るようにし
たプリント配線板のパターン検査方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a pattern of a printed wiring board, and more specifically, it is possible to inspect the presence / absence of displacement of a circuit pattern, a through hole, etc. by a short / open inspection by a continuity checker. The present invention relates to a pattern inspection method for a printed wiring board.

【0002】[0002]

【従来の技術】部品の小形化および高密度実装化に伴っ
て配線パターンも高精細化が要求されている。例えば、
メモリやCPUの端子と接続されるランド間の間隔は
0.25mm程度とされている。
2. Description of the Related Art With the miniaturization of components and high-density mounting, high-definition wiring patterns are required. For example,
The distance between the lands connected to the terminals of the memory or CPU is about 0.25 mm.

【0003】したがって、回路パターンの印刷時やスル
ーホールの穿孔時に位置ずれが生ずると、それが直接的
に誤接続の不良原因となってしまう。
Therefore, if a positional deviation occurs when a circuit pattern is printed or when a through hole is punched, it directly causes a defective connection.

【0004】図3には配線パターンがきわめて簡略的に
描かれたプリント配線板が例示されているが、そのパタ
ーンなどの位置ずれを検査する方法の一つとして、座標
測定機にて実測する方法がある。
FIG. 3 exemplifies a printed wiring board in which a wiring pattern is drawn in a very simple manner. As one of the methods for inspecting the positional deviation of the pattern, a method of actually measuring with a coordinate measuring machine is used. There is.

【0005】これは、基板に穿設されている例えば実装
基準孔1aもしくはプレス基準孔1bに対する各ランド
2…の位置情報(例えば距離)を求めて、それが許容値
内であるかを見る。
This is done by obtaining position information (for example, distance) of each land 2 with respect to, for example, the mounting reference hole 1a or the press reference hole 1b formed on the substrate and checking whether or not it is within an allowable value.

【0006】しかしながら、この方法は生産性の面で好
ましくない。これに対して、パターン認識装置があるが
高価であるため、特に多品種少量生産の場合にはコスト
的に負担しきれない。
However, this method is not preferable in terms of productivity. On the other hand, although there is a pattern recognition device, it is expensive, so that it cannot bear the cost particularly in the case of high-mix low-volume production.

【0007】[0007]

【発明が解決しようとする課題】そこで、人手による検
査ということになるが、目視検査にて回路パターンやス
ルーホールなどの各種のずれを短時間の内に、しかも正
確に検査するには、相当の熟練を要し、またその検査員
に過度の負担を強いるものであった。
Therefore, it is a manual inspection, but it is considerably necessary to visually inspect various deviations such as circuit patterns and through holes in a short time and accurately by visual inspection. However, the inspector had to be proficient and the inspector had to be overloaded.

【0008】特に、銀スルーホール基板においては、穿
孔時の位置ずれや印刷時のスクリーンずれのほかに、導
電塗料の乾燥条件、製造ラインの雰囲気、原材料の状態
などの複合的な要因により、スルーホール内に充填され
た銀ペーストにクラックなどが発生するおそれがあり、
全品検査の必要性が求められている。
In particular, in the case of a silver through-hole substrate, in addition to the positional deviation at the time of punching and the screen deviation at the time of printing, there are multiple factors such as the drying condition of the conductive paint, the atmosphere of the manufacturing line, the condition of the raw materials, and the like. There is a risk that cracks may occur in the silver paste filled in the holes,
The need for full product inspection is required.

【0009】[0009]

【課題を解決するための手段】本発明は上記従来の事情
に鑑みなされたもので、その構成上の特徴は、銅張積層
基板の両面に回路パターンを形成するパターン形成工程
と、その回路パターンが形成される所定の部位にスルー
ホールを穿孔する穿孔工程と、同スルーホール内に表裏
の回路パターン同士を導通させる導電性ペーストを充填
するペースト充填工程とを経て形成されるプリント配線
板において、上記パターン形成工程、上記穿孔工程およ
び上記ペースト充填工程の各工程時に、上記銅張積層基
板の余白部にそれらと同様な方法をもってその表裏両面
に検査用回路パターンを形成するとともに、それら検査
用回路パターンの所定部位に検査用スルーホールを穿設
し、さらに同検査用スルーホール内に導電性ペーストを
充填してなるチェックパターンを形成し、同チェックパ
ターンの導通、導通不良状態により、回路パターンやス
ルーホールなどの位置ずれの有無を電気的に検査し得る
ようにしたことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above conventional circumstances, and its structural features are a pattern forming step of forming a circuit pattern on both surfaces of a copper clad laminate, and a circuit pattern thereof. In a printed wiring board formed through a punching step of punching a through hole in a predetermined portion where is formed, and a paste filling step of filling a conductive paste that electrically connects the front and back circuit patterns to each other in the through hole, At the time of each of the pattern forming step, the perforating step and the paste filling step, a circuit pattern for inspection is formed on the front and back surfaces of the copper clad laminated board in the same manner as those in the blank portion, and the circuit for inspection is also formed. A check hole is formed by forming an inspection through hole at a predetermined portion of the pattern, and filling the inside of the inspection through hole with a conductive paste. Forming a click patterns, continuity of the check pattern, the conduction failure state, lies in the adapted to electrically inspect the presence or absence of the displacement such as a circuit pattern and the through-hole.

【0010】この場合、上記チェックパターンは好まし
くは、上記余白部の一方の面上に所定の間隔をもって形
成される第1および第2の銅箔部と、上記余白部の他方
の面側において両端が上記第1および第2の銅箔部に対
応するようにそれらの間にわたって一連に形成される第
3の銅箔部と、上記第1および第2の銅箔部の予定され
た位置に穿孔されるスルーホールと、同スルーホール内
に充填される導電性ペーストとから構成される。
In this case, it is preferable that the check pattern has first and second copper foil portions formed on one surface of the margin portion with a predetermined space and both ends on the other surface side of the margin portion. A third copper foil portion formed in series so as to correspond to the first and second copper foil portions, and perforated at predetermined positions of the first and second copper foil portions. And a conductive paste filled in the through hole.

【0011】[0011]

【作用】基板の表裏両面に形成される回路パターンはス
ルーホール内に充填される導電性ペーストによって導通
状態とされる。同様に、基板の余白部の表裏両面に形成
されるチェックパターンもスルーホール内に充填される
導電性ペーストによって導通状態とされる。
The circuit patterns formed on both the front and back surfaces of the substrate are made conductive by the conductive paste filled in the through holes. Similarly, the check patterns formed on both the front and back surfaces of the blank portion of the substrate are also made conductive by the conductive paste filled in the through holes.

【0012】したがって、パターン形成工程、穿孔工程
およびペースト充填工程の各工程において、位置ずれが
ない場合には、基板の余白部の表裏両面に形成されるチ
ェックパターンは導通状態となる。
Therefore, in each of the pattern forming step, the punching step, and the paste filling step, if there is no displacement, the check patterns formed on both the front and back surfaces of the blank portion of the substrate are in a conductive state.

【0013】これに対して、回路パターンやスルーホー
ルにずれがあったり、導電性ペーストにクラックが発生
している場合には、チェックパターンは非導通や高い抵
抗値を示す導通不良となる。したがって、導通チェッカ
ーにて基板の良否を検査することが可能となる。
On the other hand, when the circuit pattern or the through hole is misaligned or the conductive paste is cracked, the check pattern is non-conductive or has a high resistance value and has poor conduction. Therefore, it becomes possible to inspect the quality of the substrate with the continuity checker.

【0014】[0014]

【実施例】以下、図1および図2を参照しながら、本発
明の一実施例を説明する。まず、両面銅張積層基板10
(この例では紙基材フェノール樹脂基板を用いている)
に所定の回路パターンを有する例えばドライフィルムを
添設し、露光してエッチングレジストを形成した後、エ
ッチングして基板本体10aに例えば図3と同様の回路
パターンを形成するにあたって、同基板10の余白部1
0bにチェックパターン11を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. First, double-sided copper-clad laminated substrate 10
(This example uses a paper-based phenolic resin substrate)
For example, a dry film having a predetermined circuit pattern is attached to the substrate, exposed to form an etching resist, and then etched to form a circuit pattern similar to that of FIG. 3 on the substrate body 10a. Part 1
Check pattern 11 is formed at 0b.

【0015】すなわち、同チェックパターン11は上記
ドライフィルムにより回路パターンと同時に形成される
もので、余白部10bの一方の面側、この例では表面側
に所定の間隔をもって形成される第1および第2の銅箔
部12,13と、同余白部10bの他方の面側、すなわ
ち裏面側において両端が第1および第2の銅箔部12,
13と重なるように対応し、かつ、それらの間に一連に
形成された帯状をなす第3の銅箔部14とを備える。
That is, the check pattern 11 is formed simultaneously with the circuit pattern by the dry film. The check pattern 11 is formed on the one surface side of the blank portion 10b, that is, the front surface side in this example, with a predetermined interval. 2 of the copper foil portions 12 and 13 and the other surface side of the same blank portion 10b, that is, the back surface side has first and second copper foil portions 12 and 12,
And a third copper foil portion 14 corresponding to overlap with 13 and having a strip shape formed in series between them.

【0016】次ぎに、基板本体10aの所定部位に例え
ばパンチングプレスにてスルーホールを穿孔する際、同
プレスにて第1および第2の銅箔部12,13の予定さ
れた位置にもスルーホール15a,15bを穿設する。
Next, when a through hole is formed in a predetermined portion of the substrate body 10a by, for example, a punching press, the through hole is also formed at the predetermined positions of the first and second copper foil portions 12, 13 by the press. 15a and 15b are drilled.

【0017】そして、例えばスクリーン印刷により、基
板本体10aに穿設されたスルーホールに導電性ペース
ト、この例では銀ペーストを充填する際に、同一のスク
リーンにて上記スルーホール15a,15b内にも銀ペ
ースト16を充填する。その後、銀ペーストを高温で強
制的に乾燥する。
Then, for example, by screen printing, when the through holes formed in the substrate body 10a are filled with the conductive paste, in this example, the silver paste, the same screen is used to fill the through holes 15a and 15b. Fill with silver paste 16. Then the silver paste is forced to dry at high temperature.

【0018】なお、場合によっては回路パターン形成工
程とスルーホール穿孔工程とが入れ代わることもある。
In some cases, the circuit pattern forming step and the through hole punching step may be interchanged.

【0019】パターン検査を行なうにあたっては、導通
チェッカーが用いられる。すなわち、同導通チェッカー
の一対のプローブPa,Pbを第1の銅箔部12と第2
の銅箔部13とに接触させて導通か導通不良かを見る。
A continuity checker is used to perform the pattern inspection. That is, the pair of probes Pa and Pb of the continuity checker are connected to the first copper foil portion 12 and the second copper foil portion 12.
It is contacted with the copper foil portion 13 of No. 1 to see if the continuity or the poor continuity.

【0020】すなわち、このチェックパターン11が導
通していれば、基板本体側の回路パターンやスルーホー
ルに位置ずれがなく、また、そのスルーホール内に銀ペ
ーストが正確に充填されていると判断される。その後、
余白部10bは基板本体10aから分離される。
That is, if the check pattern 11 is conductive, it is determined that the circuit pattern and the through hole on the substrate main body side are not displaced, and that the through hole is accurately filled with the silver paste. It afterwards,
The blank portion 10b is separated from the substrate body 10a.

【0021】これに対して、非導通の場合には、基板本
体側の回路パターンやスルーホールにも位置ずれがあ
り、高抵抗値のときには銀ペーストにクラックなどが発
生していることが予想され、不良と判断される。
On the other hand, in the case of non-conduction, it is expected that the circuit pattern and the through holes on the substrate body side are also displaced, and cracks or the like are generated in the silver paste when the resistance value is high. , Judged to be defective.

【0022】[0022]

【発明の効果】以上説明したように、本発明によれば、
基板本体に対するパターン形成工程、スルーホール穿孔
工程および導電ペースト充填工程の各工程時に、基板の
余白部にそれらと同様な方法をもってチェックパターン
を形成するようにしたことにより、回路パターンやスル
ーホールの位置ずれおよび導電性ペーストのクラック発
生などの有無を導通チェッカーによって簡単にしかも自
動的に検査することができ、品質の安定した基板検査を
能率良く行なうことができる。
As described above, according to the present invention,
The position of the circuit pattern and the through hole is determined by forming the check pattern in the blank area of the board in the same manner as the pattern forming step, through hole punching step, and conductive paste filling step for the board body. The presence or absence of misalignment and cracking of the conductive paste can be easily and automatically inspected by the continuity checker, and the substrate inspection of stable quality can be efficiently performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の検査方法が適用されるプリント基板の
一例を示した同基板の摸式図。
FIG. 1 is a schematic view of a printed circuit board showing an example of a printed circuit board to which an inspection method of the present invention is applied.

【図2】図1のA−A線拡大断面図。2 is an enlarged cross-sectional view taken along the line AA of FIG.

【図3】従来の検査方法によって検査される基板を示し
た説明図。
FIG. 3 is an explanatory view showing a substrate to be inspected by a conventional inspection method.

【符号の説明】[Explanation of symbols]

10 基板 11 チェックパターン 12 第1の銅箔部 13 第2の銅箔部 14 第3の銅箔部 15 スルーホール 16 導電性ペースト 10 substrate 11 check pattern 12 first copper foil portion 13 second copper foil portion 14 third copper foil portion 15 through hole 16 conductive paste

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 銅張積層基板の両面に回路パターンを形
成するパターン形成工程と、その回路パターンが形成さ
れる所定の部位にスルーホールを穿孔する穿孔工程と、
同スルーホール内に表裏の回路パターン同士を導通させ
る導電性ペーストを充填するペースト充填工程とを経て
形成されるプリント配線板において、上記パターン形成
工程、上記穿孔工程および上記ペースト充填工程の各工
程時に、上記基板の余白部にそれらと同様な方法をもっ
てその表裏両面に検査用回路パターンを形成するととも
に、それら検査用回路パターンの所定部位に検査用スル
ーホールを穿設し、さらに同検査用スルーホール内に導
電性ペーストを充填してなるチェックパターンを形成
し、同チェックパターンの導通、導通不良状態により、
回路パターンやスルーホールなどの位置ずれの有無を電
気的に検査し得るようにしたことを特徴とするプリント
配線板のパターン検査方法。
1. A pattern forming step of forming a circuit pattern on both surfaces of a copper clad laminate, and a step of forming a through hole in a predetermined portion where the circuit pattern is formed,
In a printed wiring board formed through a paste filling step of filling a conductive paste that electrically connects the front and back circuit patterns to each other in the through hole, the pattern forming step, the punching step and the paste filling step A circuit pattern for inspection is formed on both front and back surfaces in the same manner as those in the blank part of the board, and a through hole for inspection is formed at a predetermined portion of the circuit pattern for inspection, and the through hole for inspection is further formed. A check pattern formed by filling the inside with a conductive paste is formed.
A method for inspecting a pattern of a printed wiring board, which is capable of electrically inspecting a circuit pattern or a through hole for a positional deviation.
【請求項2】 上記チェックパターンは、上記余白部の
一方の面上に所定の間隔をもって形成される第1および
第2の銅箔部と、上記余白部の他方の面側において両端
が上記第1および第2の銅箔部に対応するようにそれら
の間にわたって一連に形成される第3の銅箔部と、上記
第1および第2の銅箔部の予定された位置に穿孔される
スルーホールと、同スルーホール内に充填される導電性
ペーストとからなり、導通チェッカーにて上記第1およ
び第2の銅箔部間の導通、導通不良を検出することを特
徴とする請求項1に記載のプリント配線板のパターン検
査方法。
2. The check pattern includes first and second copper foil portions formed on one surface of the blank portion at a predetermined interval, and both ends of the blank portion on the other surface side are the first and second copper foil portions. A third copper foil portion formed in series between the first and second copper foil portions so as to correspond to the first and second copper foil portions, and a through hole punched at a predetermined position of the first and second copper foil portions. 2. A hole and a conductive paste filled in the through hole, and a conduction checker detects conduction and a conduction failure between the first and second copper foil portions. The printed wiring board pattern inspection method described.
JP4129969A 1992-04-23 1992-04-23 Pattern inspection method of printed wiring board Withdrawn JPH05297049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4129969A JPH05297049A (en) 1992-04-23 1992-04-23 Pattern inspection method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4129969A JPH05297049A (en) 1992-04-23 1992-04-23 Pattern inspection method of printed wiring board

Publications (1)

Publication Number Publication Date
JPH05297049A true JPH05297049A (en) 1993-11-12

Family

ID=15022913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4129969A Withdrawn JPH05297049A (en) 1992-04-23 1992-04-23 Pattern inspection method of printed wiring board

Country Status (1)

Country Link
JP (1) JPH05297049A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015082585A (en) * 2013-10-23 2015-04-27 富士通株式会社 Printed circuit board manufacturing method, printed circuit board unit manufacturing method and printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015082585A (en) * 2013-10-23 2015-04-27 富士通株式会社 Printed circuit board manufacturing method, printed circuit board unit manufacturing method and printed circuit board

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Effective date: 19990706