JPH04183117A - Clock regenerating circuit - Google Patents
Clock regenerating circuitInfo
- Publication number
- JPH04183117A JPH04183117A JP2313537A JP31353790A JPH04183117A JP H04183117 A JPH04183117 A JP H04183117A JP 2313537 A JP2313537 A JP 2313537A JP 31353790 A JP31353790 A JP 31353790A JP H04183117 A JPH04183117 A JP H04183117A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- circuit
- input signal
- phase
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001172 regenerating effect Effects 0.000 title abstract 3
- 230000010355 oscillation Effects 0.000 claims abstract description 26
- 230000008929 regeneration Effects 0.000 claims description 9
- 238000011069 regeneration method Methods 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000011084 recovery Methods 0.000 description 6
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 101100350613 Arabidopsis thaliana PLL1 gene Proteins 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、クロック再生回路に関するもので、特に、周
波数の異なる複数の入力に対応する場合に好適なりロッ
ク再生回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock recovery circuit, and more particularly to a lock recovery circuit suitable for dealing with a plurality of inputs having different frequencies.
従来の技術
従来の複数の入力に対応するクロック再生回路は第３図
に示すように構成される。図において、１）は入力端で
入力信号を入力する。 １２は入力端で分周比Ｎを入力
する。１３は位相同期ループ（ＰＬＬ −Ｐｈａｚｃ
Ｌｏｃｋｅｄ １ｏｏｐ ）で入力端１）からの入力信
号と入力＃Ａ１２からの分周比を受け、入力信号に同期
したＮ倍の周波数の再生クロ７りを出力する。2. Description of the Related Art A conventional clock recovery circuit corresponding to a plurality of inputs is constructed as shown in FIG. In the figure, 1) is an input terminal that inputs an input signal. 12 inputs the frequency division ratio N at the input terminal. 13 is a phase locked loop (PLL-Phazc
Locked 1loop) receives the input signal from input terminal 1) and the frequency division ratio from input #A12, and outputs a reproduced clock signal of N times the frequency synchronized with the input signal.
位相同期ループ】３は並列に複数個接続されており、す
べての入力信号に対し少なくとも１つがロックするよう
それぞれフリー発振周波数を変えて設定する。１４は切
換え回路で、すべての位相同期ループ１３の再生クロッ
クを人力し、入力信号に対応しているＰＬＬを選択し再
生クロックを出力する。A plurality of phase-locked loops 3 are connected in parallel, and the free oscillation frequency of each loop is set to be different so that at least one locks for all input signals. Reference numeral 14 denotes a switching circuit which inputs the reproduced clocks of all the phase-locked loops 13, selects the PLL corresponding to the input signal, and outputs the reproduced clock.
発明が解決しようとする！！ｌ！題
ところで、かかる構成において、それぞれのＰＬＬの人
力信号のＮ倍の周波数のクロック信号に対する同期し７
得る範囲は、安定度の点からできる限り狭くするのが理
想的であるので、複数の入力信号を入力し入力信号のＮ
倍の周波数のクロック信号に対し広い周波数範囲で同期
させようとすればかなり多くのＰＬＬを要することにな
る。そのような場合、構成も大規模となりまた、コスト
の面においても問題である。また、複数の発振器からの
妨害による影響も大きい。Invention tries to solve! ! l! By the way, in such a configuration, each PLL is synchronized with a clock signal having a frequency N times that of the human input signal.
Ideally, the range to be obtained should be as narrow as possible from the viewpoint of stability, so input multiple input signals and reduce the N of input signals.
If synchronization is to be performed over a wide frequency range with a clock signal of twice the frequency, a considerably large number of PLLs will be required. In such a case, the configuration becomes large-scale and there is also a problem in terms of cost. Furthermore, the influence of interference from multiple oscillators is also large.
本発明は、このような問題点に基ずき、その欠点を解消
し、簡潔な構成をもって、入力信号のＮ倍の周波数のク
ロック信号の周波数に対して広い周波数範囲で同期する
クロック再生回路を捉供するものである。The present invention is based on these problems, eliminates the drawbacks, and provides a clock regeneration circuit that has a simple configuration and synchronizes over a wide frequency range with the frequency of a clock signal that is N times the frequency of the input signal. It is meant to capture and provide information.
課題を解決するための手段
上記ｅＪＨを解決するために本発明のクロック再生回路
は、ＰＬＬ回路において入力信号のＮ倍の周波数のクロ
ック信号の周波数に対応して電圧制御発振回路（Ｖ Ｃ
Ｏ−・＝Ｖｏｌｔａｚｅ Ｃｏｎｔｏｒｏｌｌｅｄ ０
ｓｃｉｌｌａｔｏｒ・・・・・・以下単に■ＣＯと称す
る。）のフリー発振周波数を変化させることを特徴とす
る。Means for Solving the Problems In order to solve the above eJH, the clock regeneration circuit of the present invention generates a voltage controlled oscillation circuit (V C
O-・=Voltaze Controlled 0
scillator...hereinafter simply referred to as ■CO. ) is characterized by changing the free oscillation frequency of
作用
本発明は上記した構成によって、入力信号のＮ倍の周波
数のクロック信号の周波数に対応して■ＣＯのフリー発
振周波数を変化させることにより、ＰＬＬ１回路で入力
信号のＮ倍の周波数のクロック信号に対し広い周波数範
囲で同期するクロック再生回路を構成でき、回路規模を
小さくすることができる。また、■Ｃ○が１回路で構成
できることにより不要な妨害の発生もない。Effect of the present invention With the above-described configuration, by changing the free oscillation frequency of CO in response to the frequency of the clock signal having a frequency N times that of the input signal, the PLL1 circuit generates a clock signal having a frequency N times that of the input signal. It is possible to configure a clock regeneration circuit that synchronizes over a wide frequency range, and the circuit scale can be reduced. Furthermore, since ■C○ can be configured with one circuit, unnecessary interference will not occur.
実施例
以下本発明の実施例のクロック再生回路およびその回路
用■ＣＯについて、図面を参照しながら説明する。第１
図は本発明におけるクロック再生回路およびその回路用
■ＣＯの構成を示すものである。Embodiments Hereinafter, a clock recovery circuit and a CO for the circuit according to embodiments of the present invention will be explained with reference to the drawings. 1st
The figure shows the configuration of a clock recovery circuit and a CO for the circuit according to the present invention.
第１図において、位相比較器２４．ローハスフィルター
２５． ＶＣＯ２６，分周器２３によりＰＬＬを構成
している。そして、本構成では、複数の時定数回路２７
を切換えスイッチ２８で切り換えることによりＶＣＯ２
６のフリー発振周波数を切り換えている。In FIG. 1, phase comparator 24. Lohas filter 25. The VCO 26 and frequency divider 23 constitute a PLL. In this configuration, a plurality of time constant circuits 27
By switching the changeover switch 28, the VCO2
6 free oscillation frequencies are switched.
切換え制御回路３０は入力信号のＮ倍の周波数のクロッ
ク信号の周波数により切換えスイッチ２８の切換えを制
御するものである。The switching control circuit 30 controls switching of the changeover switch 28 based on the frequency of a clock signal that is N times the frequency of the input signal.
以上のように構成されたクロック再生回路およびその回
路用■ＣＯについて、以下第１図および第２図を用いて
その動作を説明する。まず第２図は切換えスイッチによ
る時定数の切換えによるフリー発振周波数の切換えとそ
のそれぞれの場合の特定のフリー発振周波数におけるＰ
ＬＬの同期範囲を示したものであって、入力信号の周波
数のＮ倍の周波数のクロック信号の周波数に応じて切換
えスイッチ２８を切り換えることにより同期しうる前記
電圧制御発振器のフリー発振周波数を選択することを示
すものである。The operation of the clock recovery circuit and the CO for the circuit constructed as described above will be explained below with reference to FIGS. 1 and 2. First of all, Figure 2 shows the switching of the free oscillation frequency by changing the time constant with a changeover switch and the P at a specific free oscillation frequency in each case.
The free oscillation frequency of the voltage controlled oscillator that can be synchronized is selected by switching the changeover switch 28 according to the frequency of the clock signal which is N times the frequency of the input signal. This shows that.
発明の効果
以上のように本実施例によれば、ＶＣＯ２６のフリー発
振周波数を切り換える切換スイッチ２８を設け、入力信
号の周波数のＮ倍の周波数のクロック信号の周波数に応
じて同期しうる前記電圧制御発振器２６のフリー発振周
波数に切換えることにより、入力信号のＮ倍の周波数の
クロック信号の周波数に対し広い周波数範囲で同期させ
ることが可能となり、複数種の入力信号に対応すること
ができる。Effects of the Invention As described above, according to this embodiment, the changeover switch 28 for switching the free oscillation frequency of the VCO 26 is provided, and the voltage control can be synchronized according to the frequency of the clock signal whose frequency is N times the frequency of the input signal. By switching to the free oscillation frequency of the oscillator 26, it becomes possible to synchronize in a wide frequency range with the frequency of the clock signal N times the frequency of the input signal, and it is possible to correspond to a plurality of types of input signals.
第１図は本発明の一実施例におけるクロック再生回路の
ブロック図、第２図は本発明の実施例におけるスイッチ
の切り換えによるＰＬＬの入力信ロック再生回路のブロ
ック図である。
２３・・−・・・分周回路、２４・・・・・・位相比較
回路、２６・・・・・・電圧制御発振回路、２７・・・
・・・時定数回路、２８・・・・・・切換えスイッチ、
３０・・・・・・切換え制御回路。
代理人の氏名 弁理士 小限治 明 ほか２名品 ｌ
図
路２図
■ＣＯの７９−発坂円波数の七〃り象礼ｌｉ ３ 図FIG. 1 is a block diagram of a clock regeneration circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a PLL input signal lock regeneration circuit based on switch switching according to an embodiment of the present invention. 23... Frequency divider circuit, 24... Phase comparison circuit, 26... Voltage controlled oscillation circuit, 27...
... time constant circuit, 28 ... changeover switch,
30...Switching control circuit. Name of agent Patent attorney Haru Akira Kogi and 2 other masterpieces l
Diagram 2 ■CO's 79-Osaka circular wave number 7〃ri symbol li 3 Diagram
Claims (3)
を位相ロックループにより入力信号と同期させて再生す
る再生回路において、 再生クロック信号をＮ分周する分周比可変の分周回路と
、 入力信号と前記分周回路の出力信号との位相差を比較し
、その位相差に応じた制御電圧を出力する位相比較回路
と、 前記位相比較回路の出力である制御電圧をローパスフィ
ルターを介して入力し、プログラマブルに前記制御電圧
の特定の値に対するフリー発振周波数を可変する手段を
設けた再生クロック信号を発生する電圧制御発振回路と
、 前記分周回路と位相比較回路と電圧制御発振回路とで構
成される位相ロックループが同期しているかどうかを識
別し、その結果に応じて前記電圧制御発振回路の前記制
御電圧の特定の値に対するフリー発振周波数を制御する
手段を備えたクロック再生回路。(1) In a regeneration circuit that regenerates a clock signal with a frequency N times the frequency of an input signal in synchronization with the input signal using a phase-locked loop, a frequency divider circuit with a variable division ratio that divides the frequency of the regenerated clock signal by N; A phase comparison circuit that compares the phase difference between the input signal and the output signal of the frequency dividing circuit and outputs a control voltage according to the phase difference, and a control voltage that is the output of the phase comparison circuit is passed through a low-pass filter. a voltage controlled oscillator circuit that generates a recovered clock signal that is provided with a means for inputting and programmably varying a free oscillation frequency with respect to a specific value of the control voltage; and the frequency dividing circuit, the phase comparison circuit, and the voltage controlled oscillation circuit. A clock regeneration circuit comprising means for identifying whether or not a configured phase-locked loop is synchronized, and controlling a free oscillation frequency of the voltage controlled oscillation circuit for a specific value of the control voltage according to the result.
を位相ロックループにより入力信号と同期させて再生す
る再生回路において、 再生クロック信号をＮ分周する分周比可変の分周回路と
、 入力信号と前記分周回路の出力信号との位相差を比較し
、その位相差に応じた制御電圧を出力する位相比較回路
と、 前記位相比較回路の出力である制御電圧をローパスフィ
ルターを介して入力し、前記制御電圧の特定の値に対す
るフリー発振周波数を切り換える手段を設ける事により
複数の制御範囲を持った再生クロック信号を発生する電
圧制御発振回数と、前記分周回路と位相比較器と電圧制
御発振回路とから構成される位相ロックループが同期す
るよう入力信号の周波数のＮ倍の周波数のクロック信号
の周波数に応じて前記電圧制御発振回路のフリー発振周
波数を切換える手段を備えたクロック再生回路。(2) In a reproduction circuit that reproduces a clock signal with a frequency N times the frequency of the input signal in synchronization with the input signal using a phase-locked loop, a frequency dividing circuit with a variable division ratio that divides the frequency of the reproduced clock signal by N; A phase comparison circuit that compares the phase difference between the input signal and the output signal of the frequency dividing circuit and outputs a control voltage according to the phase difference, and a control voltage that is the output of the phase comparison circuit is passed through a low-pass filter. The number of voltage controlled oscillations to generate a regenerated clock signal having a plurality of control ranges by inputting means for switching the free oscillation frequency for a specific value of the control voltage, the frequency dividing circuit, the phase comparator, and the voltage A clock regeneration circuit comprising means for switching the free oscillation frequency of the voltage controlled oscillation circuit in accordance with the frequency of a clock signal having a frequency N times the frequency of the input signal so that a phase-locked loop composed of the controlled oscillation circuit and the controlled oscillation circuit is synchronized. .
りフリー発振周波数を切換える手段を備えたことを特徴
とする請求項１または２記載のクロック再生回路。(3) The clock regeneration circuit according to claim 1 or 2, wherein the voltage controlled oscillation circuit includes means for switching the free oscillation frequency by switching a time constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2313537A JPH04183117A (en) | 1990-11-19 | 1990-11-19 | Clock regenerating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2313537A JPH04183117A (en) | 1990-11-19 | 1990-11-19 | Clock regenerating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04183117A true JPH04183117A (en) | 1992-06-30 |
Family
ID=18042516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2313537A Pending JPH04183117A (en) | 1990-11-19 | 1990-11-19 | Clock regenerating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04183117A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56137738A (en) * | 1980-03-31 | 1981-10-27 | Anritsu Corp | Phase-synchronizing circuit |
| JPS6012827A (en) * | 1983-07-01 | 1985-01-23 | Yaesu Musen Co Ltd | Pll circuit |
-
1990
- 1990-11-19 JP JP2313537A patent/JPH04183117A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56137738A (en) * | 1980-03-31 | 1981-10-27 | Anritsu Corp | Phase-synchronizing circuit |
| JPS6012827A (en) * | 1983-07-01 | 1985-01-23 | Yaesu Musen Co Ltd | Pll circuit |
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