JPH04183119A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To deal with even input signals different in magnitude of time variation from one another by switching to a highly stable PLL from an input signal having a considerable time variation in magnitude. CONSTITUTION:With the aid of a changeover signal from an input terminal 23, a changeover circuit 22 outputs a synchronous circuit signal to a phase compare circuit 27 when an input signal is a video signal with a considerable magnitude of time variation, or to a phase compare circuit 24 when the input signal is a computer signal with a less magnitude of time variation. Then, by setting a control range of a voltage control oscillating circuit 28 narrower than that of a voltage controlled oscillator circuit 25 at a particular free oscillating frequency, stability can be increased for a video signal with a considerable magnitude of time variation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock regeneration circuit, and more particularly to a lock regeneration circuit suitable for dealing with a plurality of types of inputs having different frequencies.

2. Description of the Related Art A conventional clock recovery circuit corresponding to a plurality of inputs is constructed as shown in FIG. In the figure, numeral 11 is an input terminal into which an input signal is input. 12 inputs the frequency division ratio N manually at the input terminal. 13 is a phase locked loop (PLL = Phazc L
ockcd 1oop) receives the input signal from the input terminal 11 and the frequency division ratio from the input terminal 12, and outputs a reproduced clock of N times the frequency synchronized with the input signal.

A plurality of phase-locked loops 13 are connected in parallel, and the free oscillation frequency of each loop is set to be different so that at least one locks for all input signals. 14
is a switching circuit which inputs the reproduced clocks of all the phase-locked loops I3, selects the PLL corresponding to the input signal, and outputs the reproduced clocks from the output terminal 15.

Problems to be Solved by the Invention In this configuration, it is ideal that the range in which each PLL can synchronize with a clock signal with a frequency N times that of the human input signal is as narrow as possible from the viewpoint of stability. If a plurality of input signals are inputted and synchronized in a wide frequency range with a clock signal having a frequency N times that of the input signal, a considerably large number of PLLs will be required. In such a case, the configuration becomes large-scale and there is also a problem in terms of cost. Furthermore, the influence of interference from multiple oscillators is also large.

The present invention is based on these problems, eliminates the drawbacks, and provides a clock regeneration circuit that has a simple configuration and synchronizes over a wide frequency range with the frequency of a clock signal that is N times the frequency of the input signal. This is what we provide.

Means for Solving the Problems In order to solve the above problems, the clock regeneration circuit of the present invention generates a voltage controlled oscillation circuit (V CO
--Voltazc Controllcd 0sc
NIator...hereinafter simply referred to as ■CO. )
In addition to switching the free oscillation frequency of
It is characterized by switching to L.

Effect The present invention has the above-described configuration, and is capable of switching the free oscillation frequency of the CO in accordance with the frequency of the clock signal that is N times the frequency of the input signal, and improving stability for the input signal with a large degree of temporal fluctuation. By switching to a PLL with a high frequency, the PLL2 circuit can synchronize over a wide frequency range with a clock signal with a frequency N times that of the input signal, and configure a clock regeneration circuit that can handle input signals with different degrees of temporal fluctuation. The circuit scale can be reduced. Further, since it can be configured with a VC02 circuit, unnecessary interference is less likely to occur.

Embodiment Below, regarding a black/7 reproducing circuit according to an embodiment of the present invention,
This will be explained with reference to the drawings. FIG. 1 shows a block diagram of a clock recovery circuit in an embodiment of the present invention.

In FIG. 1, reference numeral 21 inputs a horizontal synchronizing signal at an input end. Reference numeral 22 denotes a switching circuit, which determines whether the input signal is a video signal with a large degree of temporal variation or a small computer signal, by means of a switching signal from the input terminal 23. If so, the synchronous circuit signal is outputted to the phase comparator circuit 24.

Reference numeral 29 denotes a switching circuit which inputs the respective reproduced clocks from the voltage controlled oscillation circuit 25 and the voltage controlled oscillation circuit 28, switches according to the switching signal, and outputs the reproduced clock to the frequency dividing circuit 30 and the output terminal 32.

When a computer signal with a small degree of temporal variation is input, the switching circuit forms a phase-locked loop 1 consisting of the phase comparator circuit 24, the low-pass filter, the voltage-controlled oscillator circuit 25, and the frequency divider circuit 30.

The phase comparison circuit 24 receives the synchronization signal output from the switching circuit 22 and the reproduction synchronization signal output from the frequency dividing circuit 30, and outputs a control voltage according to the phase difference between them. The voltage controlled oscillation circuit 25 inputs the control voltage through a low-pass filter and switches the reproduced clock to the circuit 2.
Output to 9. Further, by switching the free oscillation frequency using a switching signal from the input terminal 26 in accordance with the frequency of a clock signal whose frequency is N times that of the input synchronizing signal, it is possible to cope with input signals in a wide frequency range. The frequency dividing circuit 30 divides the frequency of the reproduced clock by the number N of dot clocks per one synchronization signal of the input device, and transfers the reproduced synchronization signal to the phase comparison circuit 2.
Output to 4.

When a video signal with a large degree of temporal variation is input, a switching circuit forms a phase-locked loop 2 consisting of a phase comparator circuit 27, a low-pass filter, a voltage-controlled oscillator circuit 28, and the frequency dividing circuit 30.

The phase comparison circuit 27 receives the synchronization signal output from the switching circuit 22 and the reproduction synchronization signal output from the frequency dividing circuit 30, and outputs a control voltage according to the phase difference between them. The voltage controlled oscillation circuit 28 inputs the control voltage through a low-pass filter and switches the reproduced clock to the circuit 2.
Output to 9. Furthermore, by setting the control range of the voltage controlled oscillation circuit 28 to be narrower than the control range at a specific free oscillation frequency of the voltage controlled oscillation circuit 25, stability can be increased for video signals having a large degree of temporal variation. .

Effects of the Invention As described above, according to the present invention, the free oscillation frequency of the CO can be switched in accordance with the frequency of the clock that is N times the frequency of the input synchronization signal, and the By switching to a highly stable PLL, the PLL2 circuit can synchronize over a wide range of frequencies to a clock signal with a frequency N times that of the input signal, and can also handle input signals with different degrees of temporal fluctuation. .

[Brief explanation of the drawing]

FIG. 1 shows a clock reproduction 22 in one embodiment of the present invention.
...Switching circuit 1.24...Phase comparison circuit 1.25...Voltage controlled oscillation circuit 1.27...
...Phase comparator circuit 2.28...Voltage controlled oscillation circuit 2.30...Frequency divider circuit, 29...
・Switching circuit 2゜ Name of agent: Patent attorney Akira Okaji and 2 others Figure 1/2

Claims (1)

[Claims] In a clock regeneration circuit that regenerates a clock signal with a frequency N times the frequency of an input signal in synchronization with the input signal using a phase-locked loop, a switching circuit 1 which receives an input signal and switches between a signal with a large degree of temporal fluctuation such as a television signal or a video signal and a signal with a small degree of fluctuation and outputs the signal; a phase comparison circuit 1 that compares a phase difference between an input signal with a small degree of temporal variation, which is one of the outputs, and an output signal of the frequency dividing circuit and outputs a control voltage according to the phase difference; Voltage control that generates a regenerated clock signal with multiple control ranges by inputting the control voltage that is the output of circuit 1 through a low-pass filter and providing means for switching the free oscillation frequency for a specific value of the control voltage. The oscillation circuit 1, the frequency divider circuit, the phase comparator circuit 1, and the voltage controlled oscillation circuit 1 are configured to synchronize the phase-locked loop according to the frequency of the clock signal, which is N times the frequency of the input signal. a phase-locked loop 1 comprising means for switching the free oscillation frequency of the voltage controlled oscillator circuit 1; the frequency dividing circuit; an input signal with a large degree of temporal variation which is one of the outputs of the switching circuit 1; A phase comparator circuit 2 that compares the phase difference with the output signal of the circuit and outputs a control voltage according to the phase difference; and a control voltage that is the output of the phase comparator circuit 2 is inputted through a low-pass filter, and A phase-locked loop with higher stability than the phase-locked loop 1, which is composed of a voltage-controlled oscillation circuit 2 that outputs a recovered clock having a control range narrower than the control range of the oscillation frequency at a specific free oscillation frequency of the voltage-controlled oscillation circuit 1. 2, and a switching circuit 2 that inputs respective recovered clocks output from the voltage controlled oscillation circuit 1 and the voltage controlled oscillation circuit 2, switches in response to switching of the switching circuit 1, and outputs the recovered clock to the frequency dividing circuit. Equipped with a clock regeneration circuit.