JPH0417372A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0417372A JPH0417372A JP11984490A JP11984490A JPH0417372A JP H0417372 A JPH0417372 A JP H0417372A JP 11984490 A JP11984490 A JP 11984490A JP 11984490 A JP11984490 A JP 11984490A JP H0417372 A JPH0417372 A JP H0417372A
- Authority
- JP
- Japan
- Prior art keywords
- region
- defect layer
- type
- semiconductor device
- crystal defect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 229910021480 group 4 element Inorganic materials 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims abstract 2
- 239000013078 crystal Substances 0.000 claims description 18
- 230000007547 defect Effects 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229910052734 helium Inorganic materials 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 2
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 18
- 230000006866 deterioration Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000001151 other effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特にパワーＭＯ３ＦＥＴの
構造に関する。さらに詳しくは、動作速度と破壊強度を
高めるためのライフタイムキラーの導入とその導入箇所
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a power MO3FET. More specifically, it relates to the introduction of a lifetime killer to increase operating speed and breaking strength, and where to introduce it.
従来、パワーＭＯ３ＦＥＴの高速化と破壊強度を高める
ための、イオン打込みによるライフタイムキラーの導入
については、特開昭６２−２９８１２０号公報（８７，
１２，２５公開）において論じられている。Conventionally, the introduction of a lifetime killer by ion implantation in order to increase the speed and fracture strength of power MO3FETs has been described in Japanese Patent Application Laid-Open No. 62-298120 (87,
12, 25).
上記従来技術は、チップ上のＭＯ８ＦＥＴセル領域全面
にイオン打込みを行い、打込み後セル内に生成された結
晶欠陥層をライフタイムキラーとして働かせることによ
り、フライホイールダイオードの高速化及び破壊強度の
向上を図ったものである。The above conventional technology implants ions into the entire MO8FET cell area on the chip, and uses the crystal defect layer generated within the cell after implantation as a lifetime killer to increase the speed and fracture strength of the flywheel diode. It was planned.
ここでセル領域とは、パワーＭＯ５ＦＥＴにおいて複数
のＭＯＳＦＥＴ （セル）を並列接続して配置した領域
のことをいう、パワーＭＯ３ＦＥＴの動作時には、複数
のＭＯＳＦＥＴ （セル）の近傍の半導体中に蓄積され
る蓄積電荷が存在し、これが速度低下と破壊強度の低下
の原因となっていることが考えられている。The cell area here refers to the area in which multiple MOSFETs (cells) are connected in parallel in a power MO3FET. It is believed that there is an accumulated charge that is responsible for the reduced speed and fracture strength.
このため、上記半導体中にライフタイムキラーを導入し
、高速化と破壊強度の向上をはかったものである。For this reason, a lifetime killer was introduced into the semiconductor to increase speed and improve fracture strength.
しかし、上記従来技術は、ＭＯ８ＦＥＴセル領域全面に
、イオン打込みするためＭＯＳＦＥＴのしきい値電圧変
動、オン抵抗値の増大、リーク電流の増大、その他の静
特性への影響という特性劣化も同時に存在する。However, since the above-mentioned conventional technology implants ions into the entire MO8FET cell region, there are also characteristic deteriorations such as fluctuations in threshold voltage of the MOSFET, increase in on-resistance value, increase in leakage current, and other effects on static characteristics. .
本発明の目的は、上記の特性劣化をともなわずにライフ
タイムキラーを導入し、高速化及び破壊強度の向上を図
ったＭＯＳＦＥＴを得ることにある。An object of the present invention is to obtain a MOSFET that incorporates a lifetime killer without causing the above-mentioned characteristic deterioration, and that achieves higher speed and improved fracture strength.
上記目的を達成するために、パワーＭＯ３ＦＥＴにおい
てＭＯ８ＦＥＴセル領域の外周部にライフタイムキラー
を導入する。すなわち、パワーＭＯ３ＦＥＴのフライホ
イールダイオードが逆回復時において破壊に至る際、チ
ップ上にて破壊現象が最も集中するＭＯ８ＦＥＴセル領
域の外周部にイオン打込みを行い、打込み後生成された
結晶欠陥層をライフタイムキラーとして働かせるように
したものである。さらにドーパントに関しては、■族元
素もしくはメタル元素もしくはＨもしくはＨｅ等をイオ
ン打込みすることにより、ドーパントによる特性劣化を
最小限にしたものである。In order to achieve the above object, a lifetime killer is introduced in the outer periphery of the MO8FET cell region in the power MO3FET. In other words, when the flywheel diode of the power MO3FET is destroyed during reverse recovery, ions are implanted into the outer periphery of the MO8FET cell region where the destruction phenomenon is most concentrated on the chip, and the crystal defect layer generated after implantation is restored to life. It was designed to work as a time killer. Furthermore, regarding the dopant, deterioration of characteristics due to the dopant is minimized by ion-implanting group Ⅰ elements, metal elements, H, He, or the like.
ＭＯ８ＦＥＴセル領域の外周部に行なうイオン打込みは
、該外周部において、キャリアのライフタイムを著しく
減少させる。Ion implantation performed at the outer periphery of the MO8FET cell region significantly reduces carrier lifetime at the outer periphery.
これによりパワーＭＯ８ＦＥＴの破壊強度が格段に向上
し、特にモーター駆動用に関しては、その効果を最大限
に発揮することができる。また、ＭＯ８ＦＥＴセル領域
全面にイオン打込みしないことにより、しきい値電圧の
変動、オン抵抗値の増大、リーク電流の増大、その他の
静特性への影響という特性劣化を生ずることがない。ま
た、■族元素もしくはメタル元素もしくはＨもしくはＨ
ｅをイオン打込みのドーパントに選ぶことにより、ＭＯ
ＳＦＥＴの特性劣化が少なくなる。As a result, the breaking strength of the power MO8FET is significantly improved, and its effects can be maximized, especially when used for driving a motor. In addition, by not implanting ions into the entire MO8FET cell region, characteristic deterioration such as fluctuation in threshold voltage, increase in on-resistance, increase in leakage current, and other effects on static characteristics does not occur. Also, group III elements, metal elements, H or H
By choosing e as the dopant for ion implantation, MO
Characteristic deterioration of SFET is reduced.
上記ドーパントは、半導体中で電気的に不活性な理由に
よりＭＯＳＦＥＴの特性を劣化させることがない。The dopant does not deteriorate the characteristics of the MOSFET because it is electrically inactive in the semiconductor.
第１図は本発明の第１の実施例のパワーＭＯ５ＦＥＴの
平面図及び断面図である０本実施例では、定格電圧６０
ｖ、定格電流３０Ａ、ｎチャネル形パワーＭＯ８ＦＥＴ
を示す。FIG. 1 is a plan view and a sectional view of a power MO5FET according to a first embodiment of the present invention. In this embodiment, the rated voltage is 60
v, rated current 30A, n-channel power MO8FET
shows.
図において、２０１はｎ形高濃度半導体基板、２０２は
ｎ形低濃度領域で比抵抗０．８Ω−■、深さ１０μｍ、
２０３は深さ３μｍのｐ形ベース領域、２０４は深さ１
μｍのｎ形高濃度拡散領域。In the figure, 201 is an n-type high concentration semiconductor substrate, 202 is an n-type low concentration region with a specific resistance of 0.8Ω-■, a depth of 10 μm,
203 is a p-type base region with a depth of 3 μm, and 204 is a depth of 1
μm n-type high concentration diffusion region.
２０５は膜厚５０ｎｍのゲート絶縁膜、２０６は多結晶
シリコンから成るゲート電極、２０７はリンガラス膜、
２０８はアルミニウムから成るソース電極、２０９はド
レイン電極、２１０はイオン打込みによって生成した結
晶欠陥層、２１１はアルミニウムから成る保護素子の電
極、２１２はＭＯ８ＦＥＴセル領域、２１３はＭＯ８Ｆ
ＥＴセル領域−保護素子間分離領域、２１４はＭＯ５Ｆ
ＥＴセル部ｐ形領域、２１５はソースコンタクト、２１
６はｐ形拡散領域である。本実施例によれば、半導体基
板上にマスクを設け、イオン打込みを行い、結晶欠陥層
２１０を生成する。打込み条件に関しては、炭素をドー
パントして、ドーズ量１．０Ｘ１０１２（２）−２，３
Ｍ ｅ Ｖのエネルギーでイオン打込みすることにより
ｎ最低濃度領域２０２中において、深さ方向的３μｍの
位置に結晶欠陥層２１０を生成することができる。これ
により、ｎ形低濃度領域２０２とｐ形ベース領域２０３
から成るフライホイールダイオードが逆回復状態である
とき、外周部を除くセル領域中において、ｎ形低濃度２
０２中の電荷は、左右上部に位置した２つのｐ形ベース
領域を介し、引抜きが行われる。これに対しセル領域外
周部では、ｐ形拡散領域２１６近傍の電荷引抜きは、外
周部のｐ形ベース領域１ケ所に集中するため、最も破壊
し易くなる。よって外周部のみに結晶欠陥層２１０を生
成し、ライフタイムキラーを導入することにより、外周
部での引抜き電荷量を低減することができ、破壊強度を
向上させることができる。205 is a gate insulating film with a film thickness of 50 nm, 206 is a gate electrode made of polycrystalline silicon, 207 is a phosphor glass film,
208 is a source electrode made of aluminum, 209 is a drain electrode, 210 is a crystal defect layer generated by ion implantation, 211 is an electrode of a protection element made of aluminum, 212 is an MO8FET cell region, 213 is MO8F
ET cell region-protection element isolation region, 214 is MO5F
ET cell part p-type region, 215 is a source contact, 21
6 is a p-type diffusion region. According to this embodiment, a mask is provided on a semiconductor substrate, ion implantation is performed, and a crystal defect layer 210 is generated. Regarding the implantation conditions, carbon is doped and the dose is 1.0X1012(2)-2,3.
By performing ion implantation with an energy of M e V, a crystal defect layer 210 can be generated at a depth of 3 μm in the n lowest concentration region 202 . As a result, the n-type low concentration region 202 and the p-type base region 203
When the flywheel diode consisting of
The charges in 02 are extracted through the two p-type base regions located on the upper left and right sides. On the other hand, in the outer periphery of the cell region, the charge extraction near the p-type diffusion region 216 is concentrated at one location in the p-type base region in the outer periphery, making it the most likely to be destroyed. Therefore, by generating the crystal defect layer 210 only in the outer periphery and introducing a lifetime killer, it is possible to reduce the amount of electric charge extracted at the outer periphery and improve the breaking strength.
第２図は本発明の第１の実施例のパワーＭＯ３ＦＥＴの
、全体平面図である。本図において１０１はゲート電極
ボンディングバット、１０２はソース電極ボンディング
パット、１０３はＭＯ８ＦＥＴセル領域、１０４は保護
素子領域、１０５はＭＯ５ＦＥＴセル−保護素子間分離
領域、２１０はイオン打込みによって生成した結晶欠陥
層である。FIG. 2 is an overall plan view of the power MO3FET according to the first embodiment of the present invention. In this figure, 101 is a gate electrode bonding pad, 102 is a source electrode bonding pad, 103 is an MO8FET cell region, 104 is a protection element region, 105 is an isolation region between MO5FET cell and protection element, and 210 is a crystal defect layer generated by ion implantation. It is.
第３図は本発明の第２の実施例を示す、ｐチャネル形の
パワーＭＯ８ＦＥＴの断面図である。本実施例では、定
格電圧−６０ｖ、定格電流−１ＯＡ。FIG. 3 is a sectional view of a p-channel type power MO8FET showing a second embodiment of the present invention. In this example, the rated voltage is -60V and the rated current is -1OA.
Ｐチャネル形パワーＭＯ８ＦＥＴを示す。本図において
３０１はｐ形高濃度半導体基板、３０２はｐ形低濃度領
域で深さ１０μｍ、３０３は深さ３μｍのｎ形拡散領域
、３０４は深さ１μｍのｐ形高濃度拡散領域、３０５は
膜厚５０ｎｍのゲート絶縁膜、３０゛６は多結晶シリコ
ンから成るゲート電極、３０７はリンガラス膜、３０８
はアルミニウムから成るソース電極、３０９はドレイン
電極。A P-channel power MO8FET is shown. In this figure, 301 is a p-type high concentration semiconductor substrate, 302 is a p-type low concentration region with a depth of 10 μm, 303 is an n-type diffusion region with a depth of 3 μm, 304 is a p-type high concentration diffusion region with a depth of 1 μm, and 305 is a p-type high concentration diffusion region with a depth of 1 μm. A gate insulating film with a thickness of 50 nm, 30゛6 a gate electrode made of polycrystalline silicon, 307 a phosphor glass film, 308
309 is a source electrode made of aluminum, and 309 is a drain electrode.
３１０は結晶欠陥層である。本実施例によれば、結晶欠
陥層３１０は半導体基板上にマスクを設け。310 is a crystal defect layer. According to this embodiment, the crystal defect layer 310 is formed by providing a mask on the semiconductor substrate.
イオン打込みにより生成する。打込み条件に関しては炭
素をドーパントとし、ドーズ量１．ＯＸｌ ０１２ａｎ
−” ３ Ｍ ｅ Ｖにてイオン打込みすることによ
り、ｐ形低濃度領域３０２中において、深さ方向３μｍ
程の位置に結晶欠陥層３１０を生成することができる。Generated by ion implantation. Regarding the implantation conditions, carbon was used as the dopant, and the dose was 1. OXl 012an
-'' By performing ion implantation at 3 M e V, the p-type low concentration region 302 has a depth of 3 μm.
A crystal defect layer 310 can be generated at a certain position.
これによりｎチャネル形パワーＭＯ８ＦＥＴの場合と同
様に、モーター駆動に応用した場合、破壊強度を向上さ
せることができる。As a result, as in the case of an n-channel power MO8FET, when applied to a motor drive, the breaking strength can be improved.
第４図は本発明の第３の実施例を示すパワーＭＯ８ＦＥ
Ｔと低電圧論理トランジスタを共存させた、インテリジ
ェントＩＣの断面図である。本図において４０１はｐ形
高濃度半導体基板、４０２はｐ形低濃度領域、４０３は
ｎ形高濃度埋込み層、４０４はｐ形拡散領域、４０５は
ｎ形高濃度拡散領域、４０６は膜厚５０ｎｍのゲート絶
縁膜、４０７はリンガラス膜、４０８はパワーＭＯ５Ｆ
ＥＴのドレイン電極、４０９はｐ形高濃度拡散領域、４
１０はｎ形高濃度コレクタ領域、４１１はｐ形ベース領
域、４１２はｎ形高濃度エミッタ領域、４１３はｎ形高
濃度埋込み層、４１４はｐ形拡散領域、４１５は酸化膜
、４１６は多結晶シリコンから成るゲート電極、４１７
はアルミニウムから成るソース電極、４１８はイオン打
込みによって生成した結晶欠陥層である。FIG. 4 shows a power MO8FE according to a third embodiment of the present invention.
1 is a cross-sectional view of an intelligent IC in which T and low voltage logic transistors coexist. In this figure, 401 is a p-type high concentration semiconductor substrate, 402 is a p-type low concentration region, 403 is an n-type high concentration buried layer, 404 is a p-type diffusion region, 405 is an n-type high concentration diffusion region, and 406 is a film thickness of 50 nm. gate insulating film, 407 is a phosphor glass film, 408 is a power MO5F
Drain electrode of ET, 409 is p-type high concentration diffusion region, 4
10 is an n-type high concentration collector region, 411 is a p-type base region, 412 is an n-type high concentration emitter region, 413 is an n-type high concentration buried layer, 414 is a p-type diffusion region, 415 is an oxide film, 416 is a polycrystalline Gate electrode made of silicon, 417
418 is a source electrode made of aluminum, and 418 is a crystal defect layer generated by ion implantation.
本実施例によれば、半導体基板上にマスクを設け、■族
元素、メタル元素、Ｈ，Ｈｅを数Ｍ ｅ Ｖのエネルギ
ーでイオン打込みし、パワーＭＯ５ＦＥＴ部のＭＯ８Ｆ
ＥＴセル領域外周部のみに結晶欠陥層４１８を生成する
。これより低電圧論理トランジスタとパワーＭＯ８ＦＥ
Ｔの特性を劣下させることなく、ライフタイムキラーを
導入することができ、パワ一部の破壊強度を向上させる
こと′ができる。According to this example, a mask is provided on the semiconductor substrate, and group II elements, metal elements, H, and He are ion-implanted with an energy of several M e V, and MO8F of the power MO5FET section is implanted.
A crystal defect layer 418 is generated only at the outer periphery of the ET cell region. From this low voltage logic transistor and power MO8FE
It is possible to introduce a lifetime killer without deteriorating the characteristics of T, and it is possible to improve the breaking strength of a part of the power.
本発明によればＭＯＳＦＥＴの特性を劣下させることな
く、破壊強度の向上を達成することができる効果がある
。According to the present invention, it is possible to improve the fracture strength without deteriorating the characteristics of the MOSFET.
第１図は本発明の第１の実施例のパワーＭＯ３ＦＥＴの
、平面図および断面図、第２図は本発明の第１の実施例
のパワーＭＯ８ＦＥＴの、全体平面図、第３図は本発明
の第２の実施例を示すパワーＭＯ８ＦＥＴの断面図、第
４図は本発明の第３の実施例を示すインテリジェントＩ
Ｃの断面図である。
１０１・・・ゲート電極ボンディングバット、１０２・
・・ソース電極ボンディングパツ１−１１０３・・・Ｍ
Ｏ８ＦＥＴセル領域、１０４・・・保護素子領域、１０
５・・・ＭＯ８ＦＥＴセル−保護素子間分離領域。
２０１・・・ｎ形高濃度半導体基板、２０２・・・ｎ形
低濃度領域、２０３・・・ｐ形ベース領域、２０４・・
・ｎ形高濃度拡散領域、２０５・・・ゲート絶縁膜、２
０６・・・多結晶シリコンゲート、２０７・・・リンガ
ラス膜、２０８・・・ソース電極、２０９・・・ドレイ
ン電極、２１０・・・結晶欠陥層、２１１・・・保護素
子電極、２１２・・・ＭＯ８ＦＥＴセル領域、２１３・
・・ＭＯ５ＦＥＴセル領域−保護素子分離領域、２１４
・・・ＭＯ３ＦＥＴセル部ｐ形領域、２１５・・・ソー
スコンタクト、２１６・・・ｐ形拡散領域、３０１・・
・ｐ形高濃度半導体基板、３０２・・・ｐ形紙濃度領域
、３０３・・・ｎ形拡散領域、３０４・・・ｐ形高濃度
拡散域域、３０５・・・ゲート絶縁膜、３０６・・・多
結晶シリコンゲート、３０７・・・リンガラス膜、３０
８・・・ソース電極、３０９・・・ドレイン電極、３１
０・・・結晶欠陥層、４０１・・・ｐ形高濃度半導体基
板、４０２・・・ｐ形紙濃度領域、４０３・・・ｎ形高
濃度埋込み層、４０４・・・ｐ形拡散領域、４０５・・
・ｎ形高濃度拡散領域、４０６・・・ゲート絶縁膜、４
０７・・・リンガラス膜、４０８・・・パワーＭＯ８Ｆ
ＥＴドレイン電極、４０９・・・ｐ形高濃度拡散領域、
４１０・・・ｎ形高濃度コレクタ領域、４１１・・・Ｐ
形ベース領域、４１２・・・ｎ形高濃度エミッタ領域、
４１３・・・ｎ形高濃度埋込み層、４１４・・・Ｐ形拡
散領域、４１５・・・酸化膜、４１６・・・多結晶シリ
コンゲート、４１７・・・ソース電極、４１８罵 １
図
第 Ｚ 票
第
図
３ρＺ
３θ１
３ρ９
舅
図FIG. 1 is a plan view and a sectional view of a power MO3FET according to a first embodiment of the present invention, FIG. 2 is an overall plan view of a power MO8FET according to a first embodiment of the present invention, and FIG. 3 is a plan view of a power MO3FET according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view of a power MO8FET showing a second embodiment of the present invention, and FIG.
FIG. 101... Gate electrode bonding butt, 102...
...Source electrode bonding part 1-1103...M
O8FET cell region, 104... protection element region, 10
5...MO8FET cell-protection element isolation region. 201... N-type high concentration semiconductor substrate, 202... N-type low concentration region, 203... P-type base region, 204...
・N-type high concentration diffusion region, 205...gate insulating film, 2
06... Polycrystalline silicon gate, 207... Phosphorous glass film, 208... Source electrode, 209... Drain electrode, 210... Crystal defect layer, 211... Protection element electrode, 212...・MO8FET cell area, 213・
・・MO5FET cell region-protection element isolation region, 214
...MO3FET cell part p-type region, 215...source contact, 216...p-type diffusion region, 301...
- P type high concentration semiconductor substrate, 302... P type paper concentration region, 303... N type diffusion region, 304... P type high concentration diffusion region, 305... Gate insulating film, 306...・Polycrystalline silicon gate, 307...phosphorus glass film, 30
8... Source electrode, 309... Drain electrode, 31
0... Crystal defect layer, 401... P-type high concentration semiconductor substrate, 402... P-type paper concentration region, 403... N-type high concentration buried layer, 404... P-type diffusion region, 405・・・
・N-type high concentration diffusion region, 406...gate insulating film, 4
07...Phosphorous glass film, 408...Power MO8F
ET drain electrode, 409... p-type high concentration diffusion region,
410...N-type high concentration collector region, 411...P
type base region, 412...n type high concentration emitter region,
413...N type heavily doped buried layer, 414...P type diffusion region, 415...Oxide film, 416...Polycrystalline silicon gate, 417...Source electrode, 418 1
Figure No. Z Vote No. 3ρZ 3θ1 3ρ9
Claims (1)
ート型トランジスタにおいて、上記複数のＭＯＳＦＥＴ
の各ゲート直下のチャネル領域表面を除く領域に結晶欠
陥層を生成したことを特徴とする絶縁ゲート型半導体装
置。 ２、イオン打込みによって前記結晶欠陥層の生成を行っ
たことを特徴とする特許請求の範囲第１項記載の半導体
装置。 ３、IV族元素もしくはメタル元素もしくはＨもしくはＨ
ｅをドーパントとして、打込みエネルギー１００ＫｅＶ
以上で、前記イオン打込みを行ない、前記結晶欠陥層の
生成を行ったことを特徴とする特許請求の範囲第１項記
載の半導体装置。 ４、前記の絶縁形半導体装置は１つのシリコンチップ上
に論理用集積回路と共存して構成されたことを特徴とす
る、特許請求の範囲第１項記載の半導体装置。 ５、アルミ電極形成用のアルミ蒸着後、該アルミ電極を
マスクとして、イオン打込みを行ない、前記結晶欠陥層
の生成を行ったことを特徴とする特許請求の範囲第１項
記載の半導体装置。[Claims] 1. In an insulated gate transistor having a parallel connection region of a plurality of MOSFETs, the plurality of MOSFETs
An insulated gate semiconductor device characterized in that a crystal defect layer is formed in a region excluding the surface of a channel region directly under each gate. 2. The semiconductor device according to claim 1, wherein the crystal defect layer is generated by ion implantation. 3. Group IV element or metal element or H or H
implantation energy 100KeV with e as a dopant
2. The semiconductor device according to claim 1, wherein the ion implantation is performed to generate the crystal defect layer. 4. The semiconductor device according to claim 1, wherein the insulated semiconductor device is configured coexisting with a logic integrated circuit on one silicon chip. 5. The semiconductor device according to claim 1, wherein after aluminum vapor deposition for forming an aluminum electrode, ion implantation is performed using the aluminum electrode as a mask to generate the crystal defect layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11984490A JPH0417372A (en) | 1990-05-11 | 1990-05-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11984490A JPH0417372A (en) | 1990-05-11 | 1990-05-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0417372A true JPH0417372A (en) | 1992-01-22 |
Family
ID=14771665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11984490A Pending JPH0417372A (en) | 1990-05-11 | 1990-05-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0417372A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545915A (en) * | 1995-01-23 | 1996-08-13 | Delco Electronics Corporation | Semiconductor device having field limiting ring and a process therefor |
| US5747371A (en) * | 1996-07-22 | 1998-05-05 | Motorola, Inc. | Method of manufacturing vertical MOSFET |
| EP1098371A2 (en) * | 1999-11-05 | 2001-05-09 | Fuji Electric Co. Ltd. | A semiconductor device with good reverse recovery withstand and the method of manufacturing the same |
| JP2008192737A (en) * | 2007-02-02 | 2008-08-21 | Denso Corp | Semiconductor device |
| WO2015189929A1 (en) * | 2014-06-11 | 2015-12-17 | 株式会社日立製作所 | Semiconductor device, power module, power conversion device, and semiconductor device manufacturing method |
| WO2016021077A1 (en) * | 2014-08-08 | 2016-02-11 | 株式会社日立製作所 | Semiconductor device, power module, electric power converting device, automobile, and railway vehicle |
-
1990
- 1990-05-11 JP JP11984490A patent/JPH0417372A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545915A (en) * | 1995-01-23 | 1996-08-13 | Delco Electronics Corporation | Semiconductor device having field limiting ring and a process therefor |
| US5672528A (en) * | 1995-01-23 | 1997-09-30 | Delco Electronics Corporation | Method for making semiconductor device having field limiting ring |
| US5747371A (en) * | 1996-07-22 | 1998-05-05 | Motorola, Inc. | Method of manufacturing vertical MOSFET |
| EP1098371A2 (en) * | 1999-11-05 | 2001-05-09 | Fuji Electric Co. Ltd. | A semiconductor device with good reverse recovery withstand and the method of manufacturing the same |
| EP1098371A3 (en) * | 1999-11-05 | 2003-06-25 | Fuji Electric Co. Ltd. | A semiconductor device with good reverse recovery withstand and the method of manufacturing the same |
| US6870199B1 (en) | 1999-11-05 | 2005-03-22 | Fuji Electric Co., Ltd. | Semiconductor device having an electrode overlaps a short carrier lifetime region |
| JP2008192737A (en) * | 2007-02-02 | 2008-08-21 | Denso Corp | Semiconductor device |
| WO2015189929A1 (en) * | 2014-06-11 | 2015-12-17 | 株式会社日立製作所 | Semiconductor device, power module, power conversion device, and semiconductor device manufacturing method |
| WO2016021077A1 (en) * | 2014-08-08 | 2016-02-11 | 株式会社日立製作所 | Semiconductor device, power module, electric power converting device, automobile, and railway vehicle |
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