JP3730283B2 - Manufacturing method of high voltage semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method for manufacturing a high voltage semiconductor device, more particularly to a method of manufacturing a p-channel high breakdown voltage semiconductor device of the gate drive system.
[0002]
[Prior art]
Conventionally, a power IC in which a high breakdown voltage element such as a high breakdown voltage drive circuit and a low breakdown voltage element such as a low breakdown voltage control circuit are formed on the same substrate is known, and many applications are considered. For example, it is possible to simplify the level shifter or the gate circuit on the high side by creating an inverter circuit using a p-channel MOSFET or IGBT as the high breakdown voltage element.
[0003]
However, the high breakdown voltage drive circuit and the low breakdown voltage control circuit cannot be manufactured by a common process due to the restrictions on the structure of the element. Therefore, they are formed after either one is formed. For example, in a p-channel high withstand voltage MOSFET, since a deep p-well is conventionally formed and an element is formed there as in a DMOS, there is little commonality with a manufacturing process of a logic part. For this reason, the number of processes is large, and a lot of manufacturing time is consumed, resulting in an increase in manufacturing cost.
Further, the conventional high voltage MOSFET has a problem that the breakdown voltage is lowered when the dose of impurities in the active region is increased in order to lower the on-resistance.
[0004]
[Problems to be solved by the invention]
Therefore, the present invention has been made in consideration of the above circumstances, and by simultaneously forming a high withstand voltage drive circuit and a low withstand voltage control circuit, it is possible to significantly reduce the cost and to maintain the on-resistance while maintaining a high withstand voltage. An object of the present invention is to provide a high voltage semiconductor device that can be lowered.
[0005]
[Means for Solving the Problems]
According to the present invention (claim 1) , an n-type impurity is ion-implanted into an n-type active layer formed on an insulating layer at a dose of 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ^−2. A step of forming a drift region, a p-type impurity is selectively ion-implanted into the n-type drift region at a dose of 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ⁻² , and does not reach the insulating layer Forming a p-type drift region, forming a n-type base region by selectively ion-implanting n-type impurities into a surface region of the n-type drift region, and the n-type base region and Forming a gate insulating film on the p-type drift region; forming a gate electrode on the gate insulating film; and p-type impurities in the p-type drift region and the n-type base region. To form a p-type drain region in the p-type drift layer, Forming a p-type source region in the n-type base region, and forming a drain electrode on the p-type drain region and a source electrode on the p-type source region, respectively. A method for manufacturing a high voltage semiconductor device is provided.
[0006]
In the invention (invention 2) , n-type impurities are ion-implanted into the n-type active layer formed on the insulating layer at a dose of 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ^−2. Forming a p-type buffer layer by ion-implanting a p-type impurity into the n-type drift layer, and forming a p-type region in the n-type drift layer adjacent to the p-type buffer layer. Forming a p-type drift layer so as not to reach the insulating layer by ion-implanting a type impurity at a dose of 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ⁻² ; Forming a n-type base region by ion-implanting n-type impurities into the surface region; forming a gate insulating film on the n-type base region and the p-type drift region; Forming a gate electrode on the gate insulating film, the p-type drift Ion-implanting p-type impurities into the n-type base region and the n-type base region to form a p-type drain region in the p-type drift layer and a p-type source region in the n-type base region; There is provided a method of manufacturing a high breakdown voltage semiconductor device , comprising the steps of forming a drain electrode on the p-type drain region and forming a source electrode on the p-type source region .
[0007]
[Action]
The high breakdown voltage semiconductor device of the present invention has a structure in which a shallow drift region of the second conductivity type is formed on the first conductivity type SOI substrate. In such a structure, compared with the case where the first conductivity type substrate having a uniform impurity concentration is used, it is possible to greatly increase the impurity dose of the first conductivity type active layer, Therefore, it is possible to greatly reduce the on-resistance while maintaining a high breakdown voltage.
[0008]
In addition, since the SOI structure is adopted, it is easy to electrically isolate elements from each other, and therefore, it is very effective against noise.
Furthermore, since the high breakdown voltage semiconductor device of the present invention forms a shallow drift region without forming a second well-type deep well region, this drift region can be formed in the logic portion forming step. As a result, the logic part forming process can be employed in many processes. Therefore, the high breakdown voltage element and the low breakdown voltage logic portion can be formed at the same time, and the number of processes can be reduced and the cost can be greatly reduced.
[0009]
【Example】
Hereinafter, a high voltage semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of a high breakdown voltage p-channel MOSFET according to a first embodiment of the present invention. In FIG. 1, a SiO ₂ layer 2 is formed on a semiconductor substrate 1, and a high resistance n-type active layer 3 is formed on the SiO ₂ layer 2. An n-type drift layer 4 is formed in the high resistance n-type active layer 3, and a p-type drift layer 5 is formed on the surface of the n-type drift layer 4. An n-type base layer 6 is formed adjacent to the p-type drift layer 5 on the surface of the n-type drift layer 4. The n-type drift layer 4 may reach the oxide film 2.
[0010]
p-type p ⁺ is the drift layer 5 - the drain region 7, and n-type base - the scan layer 6 p ⁺ - source - source region 8 are formed respectively. Note that an n ⁺ -contact region 9 for fixing the potential of the active layer 3 is formed in the n-type base layer 6.
[0011]
A gate insulating film 10 is formed on a region between the p-type drift layer 5 and the p ⁺ -source region 8, and a gate electrode 11 is formed thereon. Further, a drain electrode 12 and a source electrode 13 are formed on the p ⁺ -drain region 7 and the p ⁺ -source region 8, respectively. In this way, a high breakdown voltage p-channel MOSFET is configured.
[0012]
The high breakdown voltage p-channel MOSFET configured as described above is manufactured as follows.
First, an SOI structure in which a SiO ₂ layer 2 and a high-resistance n-type active layer 3 are formed on an n-type semiconductor substrate 1 by directly bonding two substrates having a SiO ₂ layer formed on one surface. A semiconductor substrate is obtained. Next, phosphorus is ion-implanted into the high resistance n-type active layer 3 so that the dose amount is 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² to form the n-type drift layer 4, Further, boron is ion-implanted to a thickness of 1 to ² μm so that the dose amount is 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ^{−2 in the} n-type drift layer 4, thereby forming a p-type. The drift layer 5 is formed. If the p-type drift layer 5 is shallower than 1 μm, the breakdown voltage is lowered. If the p-type drift layer 5 is deeper than 2 μm, the dose amount of the n-type drift layer 4 decreases, which causes a problem.
[0013]
Next, using a channel implantation technique for CMOS threshold control, an n-type base layer 6 for p-channel formation and punch-through prevention (p-type drift layer 5 has a thickness of 1 μm). In this case, the thickness is 2 μm). Thereafter, a gate insulating film 10 having a thickness of 15 nm is formed, polysilicon is further deposited, and a gate electrode 11 is formed on the side of the source region 8 and a field plate is formed on the side of the drain region 7. -Forming a gut.
[0014]
Thereafter, boron is ion-implanted by self-alignment using the gate electrode 11 and the field plate as a mask, and when the p-type drift layer 5 is 1 μm, the drain region 7 having a thickness of 0.5 μm. And a source region 8 is formed. Next, in order to fix the potential of the active layer 3, an n ⁺ -contact region 9 is formed in the source region 8, and a source electrode 13 and a drain electrode 12 are further formed. Complete.
[0015]
The manufacturing process described above adopts a process used for forming a CMOS instead of a process used for forming a DMOS which has been conventionally performed. For this reason, it is possible to form a high withstand voltage element and a low withstand voltage element at the same time, including many steps common to low withstand voltage elements such as logic circuits. An example of a manufacturing process of a semiconductor device in which such a high breakdown voltage element (p-channel MOSFET) and a low breakdown voltage element (logic part) are formed simultaneously is shown in FIG.
[0016]
As shown in FIG. 2, it can be seen that among the 13 steps, the steps common to the p-channel MOSFET and the logic part reach 10 steps, and the number of steps and the manufacturing time can be greatly reduced.
[0017]
With respect to the high breakdown voltage p-channel MOSFET configured as described above, the dose amount of the p-type drift layer 5 is set as a parameter (0 to 2.12 × 10 ¹² cm ⁻² ). FIG. 3 shows the breakdown voltage when the dose is changed. The graph of FIG. 3 is data obtained in a MOSFET having a drift length of 25 μm formed on a 5 μm high-resistance n-type active layer 3 on a ₂ μm SiO ₂ layer 2.
[0018]
As apparent from the graph of FIG. 3, the dose amount of the n-type drift layer 4 is 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² , and the dose amount of the p-type drift layer 5 is 1 ×. An excellent withstand voltage is obtained at 10 ¹² cm ^{−2 to} 2 × 10 ¹² cm ⁻² . When the dose amount of the p-type drift layer 5 is 0, that is, when the p-type drift layer 5 is not formed, the dose amount of the n-type drift layer 4 is obtained in order to obtain an excellent breakdown voltage. Therefore, the element resistance cannot be lowered. In contrast, when the dose amount of the p-type drift layer 5 is 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ⁻² , the dose of the n-type drift layer 4 is maintained while maintaining a high breakdown voltage. As a result, the device resistance can be lowered.
[0019]
Next, when the breakdown voltage of the MOSFET having a drift length of 60 μm formed on the 15 μm high-resistance n-type active layer 3 on the 3 μm SiO ₂ layer 2 was determined, a high breakdown voltage of 500 V was obtained. In this case, the dose amount of the n-type drift layer 4 was 2.7 × 10 ¹² cm ⁻² , and the dose amount of the p-type drift layer 5 was 1.5 × 10 ¹² cm ⁻² .
[0020]
When the relationship between the drain voltage and drain current at a gate voltage of 5 V was determined for this MOSFET, the results shown in FIG. 4 were obtained. In this case, the on-resistance was 180 Ω · mm ² . Further, when the relationship between the drain current and the gate voltage when the source / drain voltage was 3 V was obtained, the result shown in FIG. 5 was obtained.
[0021]
FIG. 6 is a cross-sectional view of an IGBT according to the second embodiment of the present invention. In FIG. 6, an SiO ₂ layer 22 is formed on an n-type semiconductor substrate 21, and a high resistance n-type active layer 23 is formed on the SiO ₂ layer 22. An n-type drift layer 24 is formed in the high resistance n-type active layer 23, and a p-type drift layer 25 is formed on the surface of the n-type drift layer 24. An n-type base layer 26 is formed adjacent to the p-type drift layer 25 on the surface of the n-type drift layer 24.
[0022]
The p-type drift layer 25 and the n-type drift layer 24 is formed a p-type buffer layer 20, n ⁺ in this p-type buffer layer 20 - the drain region 27, and n-type base - to scan layer 26 is p ⁺ -Source regions 28 are respectively formed. An n ⁺ -contact region 29 for fixing the potential of the active layer 3 is formed in the n-type base layer 26.
[0023]
A gate insulating film 30 is formed on the region between the p-type drift layer 25 and the p ⁺ -source region 28, and a gate electrode 31 is formed thereon. Further, a drain electrode 32 and a source electrode 33 are formed on the n ⁺ -drain region 27 and the p ⁺ -source region 28, respectively. In this way, the IGBT is configured.
[0024]
The IGBT shown in FIG. 6 can be formed by a method similar to that of the MOSFET shown in FIG. 1 except that the p-type buffer layer 20 is different from the p-type drift layer 25 and the n-type drift layer 24 in the MOSFET shown in FIG. It is formed. The p-type buffer layer 20 can be formed by ion implantation of boron before and after the field implantation.
[0025]
FIG. 7 is a graph showing the relationship between the drain voltage and the drain current when the dose amount of the p-type buffer layer 20 is a parameter in the IGBT shown in FIG. From this graph, by setting the dose amount of the p-type buffer layer 20 to 2.5 × 10 ¹³ cm ⁻² or less, sufficient conductivity modulation can be caused and current-voltage characteristics can be improved. I can see that The dose of the p-type buffer layer 20 is preferably 1 × 10 ¹³ cm ^{−2 to} 2.5 × 10 ¹³ cm ⁻² .
FIG. 8 is a characteristic diagram showing switching waveforms of the IGBT shown in FIG. FIG. 8 shows that the switching speed is as fast as about 0.5 μsec.
[0026]
【The invention's effect】
As described above, according to the present invention, since the second conductivity type shallow drift region is formed on the first conductivity type SOI substrate, the first conductivity type substrate having a uniform impurity concentration is used. Compared to the case, it is possible to greatly increase the dose of impurities in the active layer of the first conductivity type. Therefore, it is possible to significantly reduce the on-resistance while maintaining a high breakdown voltage.
[0027]
In addition, since the SOI structure is adopted, it is easy to electrically isolate elements from each other, and therefore, it is very effective against noise.
Further, since the shallow drift region is formed without forming the second conductivity type deep well region, the formation process of the logic part can be adopted in many processes. Therefore, the high breakdown voltage element and the low breakdown voltage logic can be adopted. The portions can be formed at the same time, and the cost can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a high voltage MOSFET according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a flow of a manufacturing process for forming the high voltage MOSFET shown in FIG. 1 at the same time as a logic portion.
FIG. 3 is a graph showing a change in breakdown voltage when the dose amount of the n-type drift layer is changed with the dose amount of the p-type drift layer as a parameter in the high breakdown voltage MOSFET shown in FIG. 1; Figure.
4 is a characteristic diagram showing the relationship between the drain voltage and drain current of the high voltage MOSFET shown in FIG.
FIG. 5 is a characteristic diagram showing the relationship between the drain current and the gate voltage of the high voltage MOSFET shown in FIG.
FIG. 6 is a cross-sectional view of an IGBT according to a second embodiment of the present invention.
7 is a characteristic diagram showing the relationship between drain voltage and drain current when the dose of the p-type buffer layer of the IGBT shown in FIG. 6 is a parameter.
FIG. 8 is a characteristic diagram showing a switching waveform of the IGBT shown in FIG. 6;
[Explanation of symbols]
1,21 ... semiconductor substrate, 2, 22 ... SiO ₂ layer, 3, 23 ... high-resistance n-type active layer, 4, 24 ... n-type drift layer, 5,25 ... p-type drift layer, 6, 26 ... n-type Base layer, 7... P ⁺ -drain region, 8, 28... P ⁺ -source region, 9, 29... N ⁺ -contact region, 10, 30. -Electrode, 12, 32 ... drain electrode, 13, 33 ... source electrode, 20 ... p-type buffer layer, 27 ... n ⁺ -drain region.

Claims (3)

Forming an n-type drift region by ion-implanting an n-type impurity into the n-type active layer formed on the insulating layer at a dose of 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² ; A p-type impurity is selectively implanted into the drift region at a dose of 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ⁻² to form a p-type drift region so as not to reach the insulating layer. Forming an n-type base region by selectively ion-implanting n-type impurities into a surface region of the n-type drift region; forming a gate on the n-type base region and the p-type drift region; Forming a gate insulating film; forming a gate electrode on the gate insulating film; implanting p-type impurities into the p-type drift region and the n-type base region; A p-type drain region is formed in the drift layer, and a p-type drain region is formed in the n-type base region. A method of manufacturing a high breakdown voltage semiconductor device , comprising: forming a source electrode region on the p-type drain region, and forming a source electrode on the p-type source region. . Forming an n-type drift region by ion-implanting an n-type impurity into the n-type active layer formed on the insulating layer at a dose of 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² ; Forming a p-type buffer layer by selectively ion-implanting p-type impurities in the drift region, and p-type impurities in the n-type drift region at 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ⁻² . A step of selectively implanting ions at a dose to form a p-type drift region adjacent to the buffer layer so as not to reach the insulating layer; and selectively applying an n-type impurity to a surface region of the n-type drift layer A step of forming an n-type base region by ion implantation, a step of forming a gate insulating film on the n-type base region and the p-type drift region, and a gate on the gate insulating film. A step of forming a G-type electrode, n in the p-type buffer layer Selectively ion-implanting a p-type impurity to form an n-type drain region, selectively ion-implanting a p-type impurity into the n-type base region to form a p-type source region, and n A method of manufacturing a high breakdown voltage semiconductor device , comprising: forming a drain electrode on a p-type source region and forming a source electrode on the p-type source region . 3. The method of manufacturing a high breakdown voltage semiconductor device according to claim 2, wherein a dose amount of the p-type impurity forming the buffer layer is 2.5 × 10 ¹³ cm ⁻² or less.

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