JPH04169863A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To enable phase comparison of a pulselike signal with the suppression of effect of noises by having an OR signal between an input signal and a pulse with a specified width as input to perform a phase comparison of an input signal with respect to the center of time of a reference signal. CONSTITUTION:An input signal S has a chattering removed therefrom with an LPF11 and a lower pass component alone is inputted into a monostable multivibrator (MMV) 12, while the rising thereof is delayed. The MMV12 outputs a waveform shaping output signal with a duty thereof closer to 50% to supply to a 3-state gate 17 a signal SA which transmits information at a rising part of the signals by an ORing 13 between the output signal of the MMV12 and the signal S. On the other hand, after inverted in phase 14, a reference signal R is shaped in waveform with a delay circuit 15 and an AND gate 16 so that a high level section reaches a pulse with a fixed width to be turned to a pulse signal RA. Then, a phase comparison 17 is performed between a pulse central point of the signal RA and the signal SA to remove 18 a low pass component and output a signal P0. Here, a gate 17 compares signal edges to remove noises an integration processing while the noises excluding those at the edge part are removed with the MMV12.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a phase comparator circuit, and particularly to a phase comparator circuit that prevents malfunctions.
The present invention relates to a phase comparison circuit that enables high-precision comparison.

(Prior Art) As a phase comparison circuit for detecting a deviation (phase difference) of an input signal from a reference signal, circuits as shown in FIGS. 5 and 6 are conventionally known.

The phase comparator circuit in FIG. 5 consists of ANDs connected as shown.
Gates 501-504, OR gates 511.512. N
AND gate 521~523°NOR gate 531,5
32. Inverters 541-545. CMOS circuit 551
etc., and the reference signal is OR gate 511 and AND
The input signal to the gate 502 is the AND gate 50.
4 and the OR gate 512, phase comparison is performed at the rising edge of both signals, and the phase comparison output PD, υT is output from the CMOS circuit 551, and the PHASE oUT signal as a PLL lock detection signal is output from the inverter 545. obtained from the output.

In addition, the phase comparison circuit shown in FIG. 6 supplies an input signal S and a reference signal R, which are square waves with a duty of 50%, to two input terminals of an exclusive OR circuit 60, and outputs a phase comparison result signal. This is a circuit designed to obtain the following.

<Problems to be Solved by the Invention> As described above, in the conventional phase comparator circuit shown in FIG. 5, the rising edges of the input signal and the reference signal are compared. However, since the operation of this circuit is basically a phase frequency comparison, it malfunctions due to chattering etc. in the case of a noisy input signal.

Furthermore, the phase comparator circuit shown in FIG. 6 has to supply square wave pulses with a duty of 50% as both the input signal and the reference signal, resulting in a complicated circuit configuration.

Therefore, an object of the present invention is to provide a phase comparator circuit that is less affected by noise and can be applied to pulsed input signals.9 (Means for Solving the Problems) Solving the above-mentioned problems Therefore, the phase comparator circuit according to the present invention includes: a filter means for passing the low-frequency component of the input signal; a pulse generation means for outputting a pulse of a predetermined width triggered by the output of the filter means; OR gate means receiving the output signal of the generating means as an input; and receiving the output of the OR gate means, taking the reference signal as a control input and outputting a signal proportional to the phase difference of the input signal with respect to the time center of the reference signal. and 3-state gate means.

(Function) In this invention, a low-frequency component of an input signal is extracted, noise such as chattering is removed, a pulse of a predetermined width is generated based on this low-frequency component, and a pulse of a predetermined width is generated between the input signal and the predetermined width using a 3-state gate. The phase of the pulsed signal is resistant to noise by using the OR output with the pulse as input, the reference signal as the control input, and outputting a signal proportional to the phase difference of the input signal with respect to the time center of the reference signal. It allows for comparison.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a phase comparator circuit according to the present invention. Further, FIG. 2 shows a timing chart of signal waveforms of each part of the circuit of FIG. 1.

Only the low frequency components of the input signal S are extracted by a low pass filter (LPF) 11 consisting of a resistor and a capacitor, and are input to a monostable multivibrator (MMV) 12 . The input signal S with noise and chattering is LPFII
Chattering is removed by passing through the channel, but the rise is delayed. The MMV 12 outputs a waveform shaped output signal. The input signal S and the output signal of the monostable multivibrator 12 are input to the OR gate 13, and its gate output SA is supplied to the three-state gate 17.

On the other hand, the reference signal R is phase-inverted by the inverter 14, delayed by a predetermined time by the delay circuit <Delay> 15, and then sent to one input terminal of the AND gate 16. AN
The D gate 16 converts the AND output of the reference signal R and the output signal of the delay circuit 15 into the gate signal R of the 3-state gate 17.
Output as A.

That is, the reference signal R is shaped by the delay circuit 15 and the AND gate 16 so that its High level section becomes a pulse with a constant width, and the signal RA is obtained. Therefore, the phase of the signal is compared between the center point of the pulse of the signal RA and the input signal.

The output P of the 3-state gate 17 is the pulse signal RA.
A low-pass filter (LPF) 18 consisting of a resistor and a capacitor extracts a low-frequency component and outputs it.

It is preferable to use a monostable multivibrator 12 whose trigger input has steresis characteristics in order to eliminate chattering.
Information on the rising edge of the input signal S is transmitted to the signal SA by performing OR logic with the input signal S. By gating with the signal RA obtained from the reference signal R and integrating the range of the signal RA, a voltage proportional to the areas of the Low level and High level can be obtained as a phase comparison output signal.

It is preferable that the delay circuit 15 has a digital configuration, dividing the frequency of the reference signal from a frequency several times that of the reference signal, and using a counter or a shift register that uses the pre-divided signal as a clock.

The phase comparator circuit shown in Figure 1 compares signal edges, and noise is removed by integration processing, except for edge portions (
Noise when RA is low (RA) is removed by monostable multi-by-break.

FIG. 3 is a block diagram showing another embodiment of the phase comparator circuit according to the present invention, in which, similarly to FIG. 1, an LPF 31, a monostable multivibrator 32. OR gate 33. Inverter 3
4. Delay circuit 35. A delay circuit B38 . includes an AND gate 36 and further delays the output of the delay circuit 35 by a predetermined time. 3-state gate 37 . whose input is grounded and gates the output signal RA of AND gate 36 . 3-state gate 40, 3-state gate 3 which inputs the output signal SA of the OR gate 33 and uses the output signal R3 of the AND gate 39 as a gate.
The outputs P1 and R2 of 7 and 40 are passed through an LPF 41 consisting of a resistor and a capacitor to output P. I am getting .

FIG. 4 shows a timing chart of signal waveforms of various parts as shown in FIG. 3.

In this embodiment, the reference signal R is connected to an inverter 34° delay circuit 35, 38 . By using AND gates 36 and 39, two signals RA and R are combined, and by operation of signal R^ and 3-state gate 37, output Po is set to V c c / 2
, the phases are compared in the signal (Ra-RA) section, and the comparison results are held for signals other than signal R3. Even if the range of linear variation is narrow, it is effective in improving conversion efficiency.

(Effects of the Invention) As described above, according to the phase comparison circuit of the present invention, it is possible to compare the phases of pulsed signals without being easily affected by noise such as chattering.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the phase comparison circuit according to the present invention, FIG. 2 is a timing chart of signal waveforms of various parts of the configuration of FIG. 1, and FIG. FIG. 4 is a timing chart of signal waveforms of each part of the configuration shown in FIG. 3, and FIGS. 5 and 6 are configuration diagrams of a conventional phase comparator circuit. 11.18, 31.41...Low pass filter, 12
．． 32... Monostable multibibreak, 13.33.
...OR gate, 14.34...Inverter, 15.35.38...Delay circuit, 16.36.39...AND gate, 17.37.3
9...3 state gate. Agent Patent Attorney Masahiro Fukuyama Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] Filter means for passing low-frequency components of an input signal; pulse generation means for outputting a pulse of a predetermined width triggered by the output of the filter means; and the input signal and the output of the pulse generation means. a three-state gate that receives the output of the OR gate, has a reference signal as a control input, and outputs a signal proportional to the phase difference of the input signal with respect to the time center of the reference signal. A phase comparator circuit comprising: means;