KR100392337B1 - A circuits for generating minimum on/of pulse width - Google Patents

Abstract

The present invention receives a clock signal and an arbitrary pulse signal from the short pulse removing means to remove the pulse of the noise component, and inverts and outputs a pulse having a width greater than twice the width of the clock signal to a time delayed pulse, Receives the minimum on-signal and clock signal from the minimum on-pulse width generating means, detects the falling edge of the minimum on-signal, generates and outputs the low-off minimum signal in synchronization with the clock, and outputs the minimum off signal and the clock signal to the minimum off pulse. The falling edge of the minimum off signal is received by the width generating means, and a low level minimum off pulse width signal synchronized with the clock is generated and output to the combining means. The combining means removes the short pulse output from the short pulse removing means. Negative logic product of the received pulse signal and the minimum on pulse width signal output from the minimum on pulse width generating means Output the minimum off signal, receive the minimum off signal and the minimum off pulse width signal output from the minimum off pulse generating means, and perform a negative AND to generate a minimum on signal, and Butting is configured to output a pulse of a constant width.

Therefore, the present invention generates a pulse of a constant width and outputs it as a drive signal of the switching element, thereby protecting the switching element.

Description

A CIRCUITS FOR GENERATING MINIMUM ON / OF PULSE WIDTH}

The present invention relates to a minimum on / off pulse width generation circuit for outputting a width of a switching pulse of a predetermined width or more. In particular, since a switching frequency limit of many semiconductor switching elements exists, the switching pulse can be reprocessed within the switching frequency limit range. And a minimum on / off pulse width generation circuit.

Conventionally, short pulses were cut off by reprocessing the pulses or using analog delay circuits. However, this method is not easy to create an arbitrary pulse width, which is inconvenient, and because it is impossible to integrate, power consumption increases. There were various problems such as increase.

In general, when a higher switching frequency is applied to a semiconductor device having a limit of switching frequency, the semiconductor device not only has a problem of aging due to a large amount of current flowing locally, but also has various problems such as severe damage to the device.

In general, pulses calculated by a microprocessor are processed and transferred to a switching element, but an unwanted pulse may be applied to the switching element due to noise in the process of the microprocessor calculation or transmission, and the output pulse of the hysteresis controller Since the switching frequency cannot be predicted, there are also various problems such as giving a burden to the switching element.

Accordingly, the present invention has been made to solve various problems as described above, and an object of the present invention is to provide a minimum on / off pulse width generation circuit capable of generating a pulse of a constant width to protect the switching device. have.

Another object of the present invention is to provide a minimum on / off pulse width generation circuit that can limit the switching frequency to protect the switching device and increase the reliability of the product using the switching device.

In order to achieve the above object, the present invention receives a clock signal and an arbitrary pulse signal, removes a pulse of noise component, and removes a short pulse that inverts and outputs a pulse having a width larger than twice the width of the clock signal into a delayed pulse. A minimum on pulse width generating means for receiving a minimum on signal and a clock signal and detecting a falling edge of the minimum on signal to generate and output a low level minimum on pulse width signal synchronized with the clock; A minimum off pulse width generating means for receiving a signal and detecting a falling edge of the minimum off signal to generate and output a low level minimum off pulse width signal synchronized with a clock; and a short pulse output from the short pulse removing means is removed. At the same time as receiving the pulse signal, the minimum ON pulse width signal outputted from the minimum ON pulse width generation means is received to perform a negative logical product. Outputs the minimum off signal, receives the minimum off signal and the minimum off pulse width signal output from the minimum off pulse generating means, performs a negative AND to generate a minimum on-signal, and recognizes the minimum on-signal. Combining means for outputting a pulse of a constant width by the butting.

1 is a block diagram schematically illustrating a minimum on / off pulse width generation circuit according to an embodiment of the present invention;

2 is an input / output signal waveform diagram of a short pulse removing means of a minimum on / off pulse width generation circuit according to an embodiment of the present invention, and FIG. 2 (a) shows a pulse input signal waveform input to an input terminal of the short pulse removing means. 2 (b) is a clock signal waveform diagram, FIG. 2 (c) is an output signal waveform diagram at an output terminal (a) of the short pulse removing means,

3 is an input / output signal waveform diagram of a minimum on pulse width generation means of a minimum on / off pulse width generation circuit according to an embodiment of the present invention, and FIG. 3 (a) is input to an input terminal of the minimum on pulse width generation means. Figure 3 (b) is a clock signal waveform diagram, Figure 3 (c) is an output signal waveform diagram at the output terminal (b) of the minimum on pulse width generation means,

4 is an input / output signal waveform diagram of a minimum off pulse width generation means of a minimum on / off pulse width generation circuit according to an embodiment of the present invention, and FIG. 4 (a) is input to an input terminal of the minimum off pulse width generation means. Figure 4 (b) is a clock signal waveform diagram, Figure 4 (c) is an output signal waveform diagram at the output terminal (d) of the short pulse removing means,

5 is a pulse output waveform diagram of each input and output terminal in FIG. 1, FIG. 5 (a) is a clock pulse waveform diagram, and FIG. 5 (b) is an output terminal a from which pulse noise is removed in a short pulse elimination circuit. Fig. 5 (c) is a waveform diagram of the output stage (b) in the minimum on-pulse generation circuit, and Fig. 5 (d) is an output waveform diagram of the output stage (d) of the minimum off-pulse generation circuit. 5 (e) is an output waveform of the minimum off signal output from the output terminal c of the first NAND gate of the combination circuit, and FIG. 5 (f) is an output waveform of the second NAND gate output terminal e of the combination circuit. Output waveform diagram.

<Description of the symbols for the main parts of the drawings>

10: short pulse removing means 20: minimum on pulse width generating means

21: delay time element 22: counter

30: minimum off pulse width generating means 31: time delay element

32: counter 40: combination means

41: first NAND gate 42: second NAND gate

43: inverter

Hereinafter, a minimum on / off pulse width generation circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a minimum on / off pulse width generation circuit according to an embodiment of the present invention, and FIG. 2 is a short pulse of the minimum on / off pulse width generation circuit according to an embodiment of the present invention. Figure 2 (a) is a pulse input signal waveform diagram input to the input terminal of the short pulse removal means, Figure 2 (b) is a clock signal waveform diagram, Figure 2 (c) is a short pulse removal 3 is an output signal waveform diagram of the output terminal a of the means, and FIG. 3 is an input / output signal waveform diagram of the minimum on pulse width generating means of the minimum on pulse width generating circuit according to an embodiment of the present invention. Figure 3 (b) is a clock signal waveform diagram, Figure 3 (c) is an output signal waveform at the output terminal (b) of the minimum on pulse width generation means input to the input terminal of the minimum on pulse width generation means; Figure 4 is a minimum of the minimum on / off pulse width generation circuit according to an embodiment of the present invention Figure 4 (a) is a minimum off pulse width signal waveform diagram input to the input terminal of the minimum off pulse width generation means, Figure 4 (b) is a clock signal waveform diagram, Figure 4 (c) is an output signal waveform diagram at the output terminal d of the minimum off pulse width generating means, FIG. 5 is a pulse output waveform diagram at each input / output terminal in FIG. 1, and FIG. 5 (a) is a clock pulse waveform. Fig. 5B is a pulse waveform diagram at an output terminal a from which pulse noise has been removed in a short pulse elimination circuit, and Fig. 5C is a waveform diagram at an output terminal b in a minimum on pulse generating circuit. 5 (d) is an output waveform diagram at the output terminal d of the minimum off pulse generating circuit, and FIG. 5 (e) is a diagram of the minimum off signal output from the output terminal c of the first NAND gate of the combination circuit. 5 (f) is an output waveform diagram of the second NAND gate output terminal e of the combination circuit.

As shown in FIGS. 1 to 5, the minimum on / off pulse width generation circuit according to an embodiment of the present invention receives a clock signal and an arbitrary pulse signal and receives a pulse of a noise component (width smaller than twice the clock signal width). Short pulse removing means (10) made of a digital filter for removing the pulses of the pulses) and inverting the pulses having a width greater than twice the width of the clock signal to the delayed pulses; A minimum on pulse width generating means 20 for detecting a falling edge of the on signal and generating and outputting a minimum on pulse width signal of a low level synchronized with a clock; and a falling edge of the minimum off signal by receiving the minimum off signal and a clock signal. The minimum off pulse width generating means (30) for detecting and generating a low level minimum off pulse width signal synchronized with a clock, and the short pulse output from the short pulse removing means (10) Receiving the removed pulse signal and receiving the minimum on pulse width signal output from the minimum on pulse width generation means 20, performing a negative AND to output a minimum off signal, and outputting the minimum off signal and the Combination means (40) for receiving the minimum off signal output from the minimum off pulse generating means (30) and performing a negative logical product to generate a minimum on-signal, and inverting this minimum on-signal to output a pulse of constant width (40). ).

The combining means 40 receives the pulse signal a from which the short pulses output from the short pulse removing means 10 have been removed, and at the same time, the minimum on pulse width output from the minimum on pulse width generating means 20. The first NAND gate 41 for receiving the signal b and performing a negative logical product to output the minimum off signal c, and the minimum off signal c output from the first NAND gate 41 are received. And a second NAND gate 42 which receives the minimum off pulse width signal d output from the minimum off pulse generating means 30 and performs a negative AND to output the minimum on signal c. And an inverter 43 for inverting the minimum on-signal output from the second NAND gate 42 to output a pulse f of a predetermined width.

The minimum on pulse width generating means 20 receives the minimum on signal and a clock signal and delays the delay time for a predetermined time, and the delay time element 21 when the falling edge of the minimum on signal is detected. The counter 22 is configured to receive a low-level signal output from the reset signal and output a clear signal to the time delay element 21 so that the time delay element 21 outputs a signal.

The minimum off pulse width generating means 30 receives a minimum off signal and a clock signal and delays it for a predetermined time, and the delay time element 31 when the falling edge of the minimum off signal is detected. And a counter 32 that receives a low level signal as a reset signal and outputs a clear signal to the time delay element 31 so that the time delay element 31 outputs a signal.

Next, the operation and effect of the minimum on / off pulse width generation circuit according to one embodiment of the present invention configured as described above will be described. [0033] The input pulse signal passes through the digital filter 10 and is twice as long as the clock. If the input pulse signal does not change during this time, it outputs the same pulse width as the input pulse signal, and if the input pulse signal changes in less than twice the clock, the changed pulse signal is ignored and consequently the short pulse is removed. When the falling edge is detected at the minimum on signal, the delay delay element 21 outputs a low level signal synchronized with a clock. The counter 22 operates while the low level signal is generated and after the time set in the counter 22 the counter 22 clears the time delay element 21. Upon receiving the clear signal, the time delay element 21 outputs the output as a high level signal again and resets the counter 22 to complete the operation. In conclusion, the minimum on pulse width generating means 20 outputs a low signal from the falling edge of the minimum on-signal to the time set in the counter. On the other hand, when the falling edge of the minimum off-signal is detected, the delay delay element ( 31 outputs a low level signal synchronized with a clock. The counter 32 operates while the low level signal is generated, and after the time set in the counter 32, the counter 32 clears the time delay element 31. Upon receiving the clear signal, the time delay element 31 outputs the output as a high level signal again and resets the counter 32 to complete the operation. As a result, the minimum off pulse width generating means 30 outputs a low signal from the falling edge of the minimum on signal to the time set in the counter.

Specifically, a clock signal (clock waveform signals shown in FIGS. 2 (b) and 5 (a)) and an arbitrary pulse input signal (FIG. 2 (a) or FIG. 5) are input to the input terminal of the short pulse removing means. Pulse input signal waveform shown in (b) is removed to remove noise components, i.e., pulses having a width less than or equal to twice the clock pulse width, and delay the pulses having a width greater than twice the clock signal width. Is reversed to the first NAND gate 41 of the combining means 40 of the waveform shown in FIG.

The minimum on-signal (minimum on-signal shown in Fig. 3 (a)) and the clock signal (clock signals shown in Figs. 3 (b) and 5 (a)) are input to the input terminal of the minimum on-pulse generating means 20. When it is input, the low delay signal of the minimum on pulse width signal is detected by the delay delay element 21 of the minimum on pulse width generation means 20 so as to be synchronized with a clock (Figs. 3 (c) and 5 (c)). Generates a minimum ON signal and outputs it to the first NAND gate 41 of the combining means 40, and counts clock pulses at the counter 22 of the minimum ON pulse generating circuit 20 to maintain the output. When the predetermined count ends, the reset signal is received from the delay delay element 21 and a high level clear signal is output to the delay delay element 21.

Then, the minimum off signal (minimum off signal shown in Figs. 4 (a) and 5 (a)) and the clock signal (Figs. 4 (b) and 5 (at) at the input terminal of the minimum off pulse width generating means 30 When the clock signal shown in a) is inputted, the delay delay element 31 of the minimum off pulse width generation means 30 detects the falling edge of the minimum off pulse width signal to synchronize the clock with the low level (Fig. 4 (c)). ) And the minimum off signal shown in FIG. 5 (e) are generated and output to the second NAND gate 42 of the combining means 40, and the clock pulse is generated by the counter 32 of the minimum off pulse width generating means 30. After counting to maintain the output, when a predetermined count is over, a reset signal is received from the delay delay element 31 and a high level clear signal is output to the delay delay element 31.

In the combining means 40, the short pulse removing means 10, that is, the pulse signal from which the short pulse output from the digital filter has been removed (the pulse signal waveforms shown in FIGS. 2 (c) and 5 (d) and the The minimum on pulse width signal (minimum on signal shown in FIGS. 3 (c) and 5 (c)) output from the delay delay element 21 of the minimum on pulse generation means 20 is transferred from the first NAND gate 41. Receiving a negative logic product and outputting a minimum off signal, the minimum off signal (minimum off signal shown in FIG. 5 (d)) output from the first NAND gate 41 and the minimum off pulse generating means. Receives the minimum off pulse width signal (the minimum off signal shown in FIG. 5 (e)) output from the second NAND gate 42 and performs a negative AND to generate a minimum on-signal and output the result; In addition, the inverter 43 outputs the minimum on-signal (the minimum on-signal shown in FIG. 5 (f)) output from the second NAND gate 42. It receives and inverts and outputs a pulse of constant width.

As described above, according to the minimum on / off pulse width generating circuit according to the present invention, a clock signal and an arbitrary pulse signal are received by a short pulse removing means to remove a noise component, and a width larger than twice the width of the clock signal. Pulses are delayed and output by the delayed pulses.The minimum on-signal and the clock signal are received by the minimum on-pulse width generating means, and the falling edge of the minimum on-signal is detected to obtain the minimum on-pulse width signal of the low level synchronized with the clock. Generates and outputs the signal; receives the minimum off signal and the clock signal from the minimum off pulse width generating means, detects the falling edge of the minimum off pulse width signal, generates a low level minimum off pulse width signal synchronized with the clock, and outputs it to the combining means. The combination means generates a pulse signal from which the short pulse output from the short pulse removing means is removed and the minimum on pulse width. Receives the minimum on-pulse width signal output from the means and performs a negative logical product on the combining means to output a minimum off signal, and receives the minimum off signal and the minimum off pulse width signal output from the minimum off pulse generating means. Since negative logic products are performed to generate a minimum on-signal, and the minimum on-signal is inverted to output a pulse of a constant width, a pulse of a constant width is generated and output as a drive signal of the switching element. The switching element can be protected and the switching frequency can be limited to protect the switching element and increase the reliability of the products using the switching element.

Claims (6)

A short pulse removing means (10) for receiving a clock signal and an arbitrary pulse signal, removing a pulse of a noise component, and inverting and outputting a pulse having a width larger than twice the width of the clock signal into a delayed pulse; Receives a clock signal and detects the falling edge of the minimum on-signal, generates a minimum on-pulse width signal of a low level synchronized with the clock, and outputs the minimum on-pulse width generating means (20); A minimum off pulse width generating means 30 which detects the falling edge of the minimum off signal and generates and outputs a low level minimum off pulse width signal synchronized with a clock; and the short pulse output from the short pulse removing means 10; Receives the removed pulse signal, receives the minimum on pulse width signal output from the minimum on pulse width generation means 20, and performs a logical AND to output a minimum off signal. Receiving the minimum off signal and the minimum off pulse width signal output from the minimum off pulse generating means 30 and performing a logical AND to generate a minimum on-signal, and inverting the minimum on-signal And a combination means (40) for outputting a pulse of width. According to claim 1, wherein the combining means 40 receives the pulse signal from which the short pulse output from the short pulse removing means 10 is removed, and at the same time the minimum output from the minimum on pulse width generating means 20 The first NAND gate 41 receives an on pulse width signal and performs a negative logic product to output a minimum off signal, and receives the minimum off signal output from the first NAND gate 41 and at the same time. A second NAND gate 42 for receiving a minimum off pulse width signal output from the off-pulse generating means 30 and performing a negative AND to output a minimum on-signal, and outputting from the second NAND gate 42 The minimum on / off pulse width generation circuit, characterized in that consisting of an inverter (43) for outputting a pulse of a constant width by inverting the minimum on signal. 2. The minimum on / off pulse width generation circuit according to claim 1, wherein the short pulse removing means (10) is a digital filter. 2. The minimum on / off pulse width generating circuit according to claim 1, wherein the short pulse removing means (10) removes a pulse having a width smaller than twice the width of the clock signal. The method of claim 1, wherein the minimum on pulse width generating means (20) receives the minimum on signal and the clock signal and delays the predetermined time for a predetermined time, and when the falling edge of the minimum on signal is detected. A counter 22 which receives a low level minimum on pulse width signal output from the time delay element 21 as a reset signal and outputs a clear signal to the time delay element 21 to output a signal from the time delay element 21. Minimum on / off pulse width generation circuit, characterized in that consisting of). The method of claim 1, wherein the minimum off pulse width generating means (30) receives the minimum off signal and the clock signal and delays the predetermined time for a predetermined time, and when the falling edge of the minimum off signal is detected. The counter delay unit 31 receives a low off-level minimum pulse width signal as a reset signal and outputs a clear signal to the delay unit 31 so as to output a signal from the delay unit 31. A minimum on / off pulse width generation circuit, characterized in that configured.