JP3561171B2 - Demodulation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a demodulation circuit capable of accurately demodulating a pulse-modulated data signal such as a radio clock.
[0002]
[Prior art]
As this type of demodulation circuit, a circuit as shown in the circuit diagram of FIG. 3 is generally used. In the circuit shown in FIG. 3, a data signal is obtained from the pulse modulated wave applied to the input terminal 1 by the detection circuit 3, and the data signal is applied to the comparator 4.
The comparator 4 compares the data signal with the voltage of the reference power supply E2 connected to the inverting input terminal.
Then, when the data signal exceeds the voltage of the reference power supply E2, a high-level output is obtained at the output terminal 2.
The comparator 4 has a role of shaping the waveform of the detected data signal.
However, in the case of a data signal in which data of the same signal level continues for a long time and then data of another signal level is included, an accident that cannot be accurately demodulated often occurs.
[0003]
FIG. 4 is a voltage waveform diagram in each part of the circuit of FIG. 3, but shows an example in which demodulation of a data signal is not performed accurately.
W5 is a pulse-modulated wave applied to a filter circuit 5 connected to the preceding stage of the demodulation circuit, W1 is a pulse-modulated wave at an input terminal 1, and W3 is a data signal obtained by a detection circuit 3 applied to a non-inverting input terminal of a comparator 4. , W2 represent the respective voltage waveforms of the output of the demodulation circuit obtained at the output terminal 2.
The data signal W3 includes the high-level data 12 for a short time from the time t11 to the time t12 after the low-level data continues from the time t10 to the time t11, and thereafter the low-level data continues again. I do.
The DC level 14 of the pulse modulated wave W5 including such a data signal changes by passing through the filter circuit 5, and becomes like the pulse modulated wave W1.
In other words, the DC level 14 near times t11 and t12 after the low-level data has continued for a long time is lower than that near time t10 when the high-level data continues.
This is due to the frequency characteristics of the filter circuit 5.
[0004]
Since the data signal W3 is obtained by removing the carrier 13 from the pulse modulated wave W1, the DC level 14 of the data signal W3 also decreases in the vicinity of the times t11 and t12.
Voltage _{V E2} and the data signal W3 of the comparator 4, a reference power source E2 but are compared, the level of the data 12 in the high level at time t11, t12 near the DC level 14 is lowered to the level of the voltage _{V E2} of the reference power source E2 Therefore, a high-level output cannot be obtained at the output terminal 2 because the output does not reach the output terminal 2.
The same applies to high-level data 15 after time t12.
Therefore, the output W2 of the demodulation circuit is demodulated in a state where the high-level data 12 and 15 between the times t11 and t12 are missing.
The pulse modulated wave W5 passes through the filter circuit 5, so that the high-frequency component and the low-frequency component are removed, and the rising and falling portions are rounded and deformed like the pulse modulated wave W1.
The rising portion and the falling portion of the pulse modulated wave W5 correspond to a change in the signal level of the data signal superimposed on the carrier 13.
In other words, this is a portion where the data signal before being transformed by the filter circuit 5 changes from low level to high level and from high level to low level.
The changing portion of the signal level of the data signal W3 is also deformed according to the deformation of the pulse modulated wave W1, but the comparator 4 shapes the waveform of the data signal W3 to clarify the changing portion of the signal level, and the filter circuit 5 And demodulates the data signal superimposed on the carrier wave 13 before passing through.
[0005]
[Problems to be solved by the invention]
An object of the present invention is to provide a demodulation circuit capable of always performing accurate demodulation even when the DC level of a data signal changes due to the continuation of the same signal level.
[0006]
[Means for Solving the Problems]
In the demodulation circuit of the present invention, a pulse modulation wave detection circuit, a differentiation circuit, an addition circuit, and a flip-flop circuit are sequentially connected, and a data signal obtained by detecting the modulation wave passes through a differentiation circuit to an addition circuit. In addition, the adding circuit adds the first output obtained from the differentiating circuit and the second output that is delayed and inverted as compared with the first output, thereby generating an output indicating a change in the signal level of the data signal. The output of the flip-flop circuit which occurs and changes in synchronization with the output of the adder circuit is obtained at an output terminal.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
The demodulation circuit of the present invention differentiates the data signal obtained by the detection circuit, thereby clarifying a change in the signal level of the data signal.
Further, by adding the first output obtained from the differentiating circuit and the second output delayed and inverted compared to the first output, a pair of outputs indicating the changed portion is obtained from the adding circuit.
This changing portion is a portion where the signal level of the data signal changes from low level to high level and from low level to high level.
The output of the flip-flop circuit synchronized with the pair of outputs becomes a correctly demodulated data signal.
[0008]
【Example】
Hereinafter, description will be made with reference to FIG. 1 which is a circuit diagram showing an embodiment of the demodulation circuit of the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals.
In the demodulation circuit of FIG. 1, a pulse modulation wave detection circuit 3, a differentiation circuit 10, an addition circuit 6, and a flip-flop circuit 7 are sequentially connected.
The differentiating circuit 10 includes an operational amplifier 8, a capacitor C1, a resistor R1, and a reference voltage source E1 connected to a non-inverting input terminal of the operational amplifier 8.
The reference voltage source E1 supplies a bias voltage for setting an operating point of the operational amplifier 8.
The output side of the differentiating circuit 10 is connected to an input terminal P1 on one side of the adding circuit 6 via a resistor R3, to a delay circuit 11 composed of a resistor R2 and a capacitor C2, and to the other input terminal P2 of the adding circuit 6 via an inverting circuit 9. ing.
Although a small-capacity capacitor C3 for removing noise is connected to the input terminal P1, it may be removed in some cases.
The output side of the adder circuit 6 is connected to the set input terminal S and the reset input terminal R of the flip-flop circuit 7, respectively.
The normal output terminal Q of the flip-flop circuit 7 is connected to the output terminal 2 of the demodulation circuit.
[0009]
In the demodulation circuit configured as described above, the pulse modulation wave applied to the input terminal 1 of the demodulation circuit is detected to obtain a data signal.
The data signal is deformed by the pulse modulated wave passing through the filter circuit, but the differentiated portion clarifies the portion where the signal level changes.
The differentiated data signal is applied to one input terminal P1 of the addition circuit 6 via a resistor R3, delayed by a delay circuit 11 and inverted by an inversion circuit 9 and applied to the other input terminal P2 of the addition circuit 6. Can be
The differentiated data signal at input terminal P2 is slightly delayed and inverted compared to the differentiated data signal at input terminal P1.
Then, the differentiated data signals of the input terminals P1 and P2 having the same size are added.
The portion where both differentiated data signals overlap is canceled by each other, so that the adder circuit 6 does not produce an output.
In the portion where the signal level of the data signal changes, the adder circuit 6 produces an output because both differentiated data signals are shifted.
That is, when the signal level of the data signal changes from the low level to the high level, and when the signal level changes from the high level to the low level, the adder circuit 6 generates an output.
This pair of outputs is obtained from another output terminal of the adder circuit 6 and applied to the set input terminal S and the reset input terminal R of the flip-flop circuit 7.
The output of the normal output terminal Q of the flip-flop circuit 7 changes in synchronization with the output of the adder circuit 6, and the data signal accurately demodulated at the output terminal 2 is obtained.
[0010]
Next, a description will be given with reference to FIG. 2 which is a voltage waveform diagram of each part in FIG. The horizontal axis represents a common time axis.
Note that the modulated wave and the data signal have the same shape as in FIG. 4 and are assigned the same reference numerals.
W1 is a pulse modulated wave of the input terminal 1, W3 is a data signal obtained by the detection circuit 3, WP1 is a differentiated data signal, an input applied to the input terminal P1 of the adder 6, and WP2 is a differentiated data signal. Where WR is an input applied to the input terminal P2 of the addition circuit 6 delayed and inverted compared to the input WP1, WR is an output of the addition circuit 6 applied to the reset input terminal R of the flip-flop circuit 7, and WS is a flip-flop. The output of the adder circuit 6 applied to the set input terminal S of the circuit 7 and W2 is the output of the demodulation circuit obtained at the output terminal 2.
The input WP2 has a shape obtained by inverting the input WP1, and is further delayed from the input WP1 by the time t0.
The data signal W3 includes short-time high-level data 12 after low-level data continues for a long time.
[0011]
The data signal W3 changes from low level to high level at time t1, and changes from high level to low level at time t3.
Long low-level data continues from time t3, changes from low to high at time t5, and there is short-time high-level data 12 until time t7.
At time t7, the signal changes from the high level to the low level, and long low-level data continues until time t9, and changes to high-level data 15 from time t9.
The input WP1, which is the differentiated data signal, clarifies the change in the signal level of the data signal W3.
That is, the input WP1 rises sharply at times t1, t5, and t9 when the data signal W3 changes from low level to high level, and at times t3 and t7 when the data signal W3 changes from high level to low level. To be.
The other input WP2, which is the differentiated data signal, is delayed and inverted compared to the input WP1, but corresponds to a waveform obtained by inverting the input WP1 and further delaying the input WP1 by the time t0.
[0012]
Therefore, the input WP2 and the input WP1 overlap each other in an inverted state except for the time between time t1 and time t2, between time t3 and time t4, between time t5 and time t6, and between time t7 and time t8. I have. The time of each non-overlapping interval is the delayed time t0.
When the input WP2 and the input WP1 are added by the adder circuit 6, the adder circuit 6 does not produce an output at the overlapping portion, but produces an output at a non-overlapping time.
Times t1, t5, and t9 at which the input WP2 and the input WP1 do not overlap are the times when the data signal W3 changes from the low level to the high level, and at times t3 and t7, the data signal W3 changes from the high level to the low level. It is time.
That is, the signal level of the data signal W3 changes.
[0013]
The adder circuit 6 generates, from different output terminals, an output obtained when the changing portion of the data signal W3 changes from low level to high level and an output obtained when the changing portion changes from high level to low level.
In FIG. 2, the output WR when going from low level to high level is applied to the reset input terminal R of the flip-flop circuit 7, and the output WS when going from high level to low level is applied to the set input terminal S.
At the normal output terminal Q of the flip-flop circuit 7, an output that changes in synchronization with the pair of outputs WR and WS of the adder circuit 6 is obtained.
The output W2 of the normal output terminal Q obtained at the output terminal 2 is a correctly demodulated data signal.
As described above, only a change in the signal level of the data signal W3 is detected as an output of the adder circuit 6, and a change in the DC level 14 of the data signal W3 having a smaller change than the change is not detected.
Accordingly, the high-level data 12 having a low DC level 14 of the data signal W3 is accurately demodulated at the output W2.
In the embodiment, a pair of outputs of the adder circuit 6 are separated internally to be obtained as two outputs. However, a circuit different from the adder circuit 6 is connected to the outside and the pair of outputs is separated by the circuit. It may be added to the flip-flop circuit 7.
[0014]
【The invention's effect】
As described above, the demodulation circuit of the present invention differentiates the data signal obtained by the detection circuit to clarify the change in the signal level of the data signal.
Then, by adding the first output obtained from the differentiating circuit and the second output that is delayed and inverted compared to the first output, a pair of outputs indicating the changed portion is obtained from the adding circuit. By changing the output of the flip-flop circuit in synchronization with the output, an accurately demodulated data signal can be obtained.
Only the change in the signal level of the data signal is detected by the output of the adding circuit 6, and the change in the DC level of the data signal is not detected.
Therefore, even if the DC level of the data signal changes, the change is not affected, and accurate demodulation can always be performed.
The present invention is a practical invention that can be widely applied to demodulation of various data signals having changed DC levels.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a demodulation circuit of the present invention.
FIG. 2 is a voltage waveform diagram of the circuit of FIG.
FIG. 3 is a circuit diagram of a conventional demodulation circuit.
FIG. 4 is a voltage waveform diagram of the circuit of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Input terminal 2 Output terminal 3 Detection circuit 6 Addition circuit 7 Flip-flop circuit

Claims (2)

A pulse modulation wave detection circuit, a differentiation circuit, an addition circuit, and a flip-flop circuit are sequentially connected, and a data signal obtained by detecting the modulation wave is applied to the addition circuit through a differentiation circuit, and the addition circuit is differentiated. The first output obtained from the circuit and the second output delayed and inverted compared to the first output are added to generate an output indicating a change in the signal level of the data signal. A demodulation circuit which obtains an output of a flip-flop circuit which changes in synchronization with the output terminal of the flip-flop circuit at an output terminal. A pulse modulation wave detection circuit, a differentiation circuit, an addition circuit, and a flip-flop circuit are sequentially connected.The output side of the differentiation circuit is connected to the addition circuit and connected to the addition circuit via a delay circuit and an inversion circuit. The data signal obtained by detecting the modulated wave is added to the addition circuit through the differentiating circuit, and is also added to the adding circuit through the differentiating circuit, the delay circuit, and the inverting circuit, and both are added. A demodulation circuit which generates an output indicating a level change portion and obtains, at an output terminal, an output of a flip-flop circuit which changes in synchronization with the output of the adder circuit.

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