JPH06188697A - Reception data reproduction device - Google Patents

Abstract

PURPOSE:To provide a reception data reproduction device from which accurate digital data are reproduced just after the start of signal input with superior resistance to environment. CONSTITUTION:A state change detection circuit 2 cancels a DC component of an input analog signal and detects the change by differentiating the input analog signal. A polarity comparator circuit 3 compares an output of the state change detection circuit 2 with a reference voltage to detect whether the differentiated waveform of the input analog signal changes in the positive direction or the negative direction. A logic conversion circuit 4 outputs logical 1 when the polarity comparator circuit 3 a change in the input analog signal in the positive direction and outputs logical 0 when the polarity comparator circuit 3 a change in the input analog signal in the negative direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received data reproducing apparatus for reproducing an analog signal output from a demodulator such as a radio into digital data.

[0002]

2. Description of the Related Art Conventionally, an apparatus for receiving a modulated output signal modulated with digital data, demodulating it and reproducing the digital data has been conventionally constructed as described below. FIG. 8 is a diagram showing a configuration of a conventional received data reproducing device 7. FIG. 9 is a diagram showing an input signal waveform of the conventional received data reproducing apparatus 7 and a waveform of reproduced digital data. The conventional received data reproducing device 7 is applied to a demodulator output signal containing a DC component, and reproduces digital data by comparing the average voltage value of the demodulator output signal (input analog signal) with the input analog signal. It is a device.

In FIG. 8, a voltage comparator 71 compares the voltage value of the non-inverting input shown in the figure with the voltage value of the inverting input, and when the voltage value of the non-inverting input is higher than the voltage value of the inverting input. Output a logical value of 1, and vice versa.
Is output. The DC component detection circuit 72 is, for example, a resistor,
A voltage value smoothing circuit composed of a capacitor and the like, which takes the average voltage (DC component) from the demodulator output signal and outputs it.

The operation of the conventional received data reproducing device 7 will be described below. In FIG. 9, the waveform shown in FIG. 9A is the waveform (a) of the input analog signal to the conventional received data reproducing apparatus 7 and the DC component waveform (b). The waveform shown in (B) is digital data (c) reproduced by the conventional received data reproducing device 7. In addition, in FIG.
The waveforms shown in (a) to (c) are the waveforms at the points shown in (a) to (c) of the conventional received data reproducing apparatus 7 shown in FIG. 9, respectively.

The input analog signal has a waveform as shown in the waveform (a) of FIG. 9 (A). The input analog signal is input to the non-inverting input of the voltage comparator 71 and the DC component detection circuit 72. In the DC component detection circuit 72, the input analog signal is smoothed, the average voltage of its waveform is extracted, and is input to the inverting input of the voltage comparator 71 as the DC component of the input analog signal.

The voltage comparator 71 compares the DC component with the input analog signal. Here, as described above, the voltage comparator 71 compares the voltage value of the non-inverting input with the voltage value of the inverting input, and when the voltage value of the non-inverting input is higher than the voltage value of the inverting input, the logical value 1 Is output and logical value 0 in the opposite case
Is output.

Therefore, since the input analog signal waveform (a) and the direct current component waveform (b) have a relationship as shown in FIG. 9 (A), the input analog signal (b) is better than the direct current component waveform (b). In the high portion, the voltage comparator 71 outputs a logical value 1 and the input analog signal (b) is more than the DC component waveform (b).
In the portion where is low, the voltage comparator 71 outputs a logical value 0.
Therefore, the output waveform (digital data) of the voltage comparator 71 has a waveform as shown in FIG.

The waveforms in FIG. 9 will be described below.
In the waveform shown in (A), the range shown in (c) shows a state in which noise is present before the input analog signal is input, and shows a region where reproduction into digital data is unnecessary.
The range shown in (d) shows a region to which an input analog signal is input and which is a target of reproduction into digital data.

In the range shown in (e) in the waveform shown in (B), the DC component of the input analog signal does not rise sufficiently in the DC component detection circuit 72, and the input analog signal is reproduced as digital data in the voltage comparator 71. This is a region that cannot be used as a reference voltage for operating. Therefore, this range is a non-reproducible range of digital data.

The range indicated by (f) is a region in which the DC component changes while taking a value close to that of the input analog signal. Therefore, as shown in the figure, it is a region where the waveform width of the reproduced digital data is unstable. Become. The area indicated by (g) is an area in which the DC component of the output of the DC component detection circuit 72 or the demodulator is high due to a temperature change or the like. Therefore, as shown in FIG. It is a non-reproducible area. The area indicated by (h) is an area in which the output of the DC component detection circuit 72 or the demodulator is destabilized due to, for example, a temperature change. Therefore, as shown in FIG. It is in the stable range.

[0011]

Since the conventional received data reproducing apparatus is constructed as described above, it has the following problems. Immediately after the device starts up,
Alternatively, when the input analog signal is supplied, digital data cannot be reproduced until the comparison voltage of the input analog signal rises. Further, there is a problem that the width of the waveform of the reproduced digital data becomes unstable during the rising of the DC component.

Further, it is vulnerable to fluctuations in the output voltage of the demodulator or the like due to temperature changes, etc., and if there is such fluctuations in the output voltage, the value of the reproduced digital data becomes unstable.
Alternatively, there is a problem that the waveform width of the digital data becomes unstable, and as a result, the error rate of the reproduced digital data increases. This problem is important, for example, in portable wireless data terminals used under particularly severe environmental conditions.

The present invention has been made in view of the above-mentioned problems of the prior art, and can accurately reproduce digital data immediately after the apparatus is started up or a signal is input. It is an object of the present invention to provide a received data reproducing device that is resistant to temperature changes or fluctuations in the DC component of demodulated output.

[0014]

In order to achieve the above object, the received data reproducing apparatus of the present invention has the pulse train band-limited and further the band-limited of the received signal which may be superimposed on the DC component. Depending on the change point detecting means for detecting the rising time and the falling time of the pulse signal, and the detected one set of the rising time and the falling time, or the detected one set of the falling time and the rising time. And a pulse generation circuit that generates a pulse signal corresponding to a specified time.

The changing point detecting means includes a phase inverting means for inverting the phase of the received signal, and a delay means for giving a time delay to the inverted output signal or the non-inverted output signal output from the phase inverting means. Of the inverted output signal and the non-inverted output signal, an output signal with a delay and an output signal without a delay are added, and the rising portion of the reception signal and the rising portion of the reception signal around a certain voltage are added. Adding means for outputting a change point detection signal corresponding to the falling portion, a first reference voltage having a predetermined voltage value, and
The second reference voltage, which is a voltage value lower than the first reference voltage, and the voltage value of the change point detection signal are compared, and when the voltage of the change point detection signal is higher than the first reference voltage, and When the voltage of the change point detection signal is lower than the second reference voltage, a rising edge point and a falling edge point, or a comparing means for detecting a falling edge point and a rising edge point are provided for each case. It is characterized by being done.

The change point detecting means differentiates the received signal and outputs a change point detection signal corresponding to a rising portion and a falling portion of the received signal with a certain voltage as a center, and differentiating means. The first reference voltage, which is a predetermined voltage value, and the second reference voltage, which is a voltage value lower than the first reference voltage, and the voltage value of the change point detection signal are compared, and from the first reference voltage, Also when the voltage of the change point detection signal is high, and when the voltage of the change point detection signal is lower than the second reference voltage, the rising time point and the falling time point corresponding to each case, or It is characterized by comprising a comparison means for detecting a falling time point and a rising time point.

[0017]

[Function] The input analog signal is phase-inverted, one of the signals whose phases are inverted to each other is delayed, and both are added by an adder circuit to cancel the fluctuation of the DC component of the input analog signal and to differentiate it. To detect the change point. By comparing this change point with the reference voltage, signals indicating the rising and falling timings of the digital data are generated, and the digital data is reproduced by this signal.

[0018]

EXAMPLE A first example of the present invention will be described below. FIG. 1 is a diagram showing a schematic configuration of a data communication system to which a first received data reproducing apparatus 1 of the present invention is applied. The data communication system shown in FIG. 1 includes a transmission system 5, a spatial transmission system, and a reception system 6. Transmission system 5
Is composed of a carrier signal generating circuit 51, a modulator 52, a data terminal 53, and an output amplifier (PA) 54.
The reception system 6 includes a receiver 61, a demodulator 62, and the first reception data reproduction device 1.

The outline of the operation of the data communication system shown in FIG. 1 will be described below. First, in the transmission system 5, the carrier wave signal generated by the carrier wave signal generation circuit 51 is transmitted to the modulator 5
4800 input from the data terminal 53
It is modulated by digital data of about bps. Here, as the modulation method in the modulator 52, the FSK modulation method or the like is used.

The signal modulated by the modulator 52 is amplified by the output amplifier 54, becomes a radio wave through the antenna, and is spatially transmitted to the receiving system 6. This radio wave is received by the receiver 61 of the receiving system 6 via the antenna and demodulated by the demodulator 62. Here, the output signal of the demodulator 62 does not become a digital signal due to the transmission band limitation on the transmission system 5 side, but becomes an analog signal (input analog signal) with a rounded waveform. First received data reproduction device 1
Is connected to the demodulator 62 in order to reproduce such an input analog signal into digital data equivalent to the time when it was output at the data terminal 53.

The first received data reproducing apparatus 1 of the present invention will be described below. FIG. 2 is a diagram showing a configuration of the first reception data reproducing device 1. FIG. 3 is a diagram showing a circuit of the first reception data reproducing device 1. In FIG. 2, the state change detection circuit 2 detects the change by canceling the DC component of the input analog signal and differentiating the input analog signal. The positive / negative comparison circuit 3 compares the output of the state change detection circuit 2 with a reference voltage to detect whether the differential waveform of the input analog signal is changing in the positive direction or in the negative direction. The logic conversion circuit 4 outputs a logical value 1 when the positive / negative comparison circuit 3 detects a change in the positive direction of the input analog signal, and outputs a logic value 1 when a change in the negative direction of the input analog signal is detected. The value 0 is output.

The structure and operation of the positive / negative comparison circuit 3 will be described. In FIG. 3, the positive / negative comparison circuit 3 includes resistors (R _{1 to} R ₅ ), transistors (Tr ₁ ), delay circuits (D) 21, capacitors (C ₁ ), NAND logic circuits (L ₁ , L ₂ ), And an operational amplifier (A ₁ ). Here, the delay circuit 21 is a time constant circuit composed of a resistor and a capacitor, and gives a delay of, for example, digital data (1/4) bit. Therefore, in the present embodiment, the delay time is about 1 / (4800 × 4) = 52 μsec ... (Equation 1). This time constant should be changed according to the data rate of digital data. The transistor (Tr ₁ ) and the resistors (R _{1 to} R ₃ ) form a circuit that inverts the phase of the input analog signal. By this circuit, signals having the relationship in which the phase shift of the same signal is inverted are output to the emitter and collector of the transistor (Tr ₁ ).

The resistors (R ₄ , R ₅ ), the operational amplifier (A ₁ ) and the capacitor (C ₁ ) form an adding circuit. That is, the operational amplifier (A ₁ ) is a resistor (R ₄ ,
The sum of the signals input from R ₅ ) is output. The capacitor (C ₁ ) is inserted to block the DC component of the output signal of the operational amplifier (A ₁ ). This adding circuit constitutes a differentiating circuit together with the phase inverting circuit and the delay circuit 21. The operation of this differentiating circuit is as follows. The input analog signal input to the phase inverting circuit has its inverted output output from the collector side of the transistor (Tr ₁ ) and its non-inverted output output from the emitter side.

Of these two outputs, the non-inverted output is given the above-mentioned delay by the delay circuit 21, is input to the adder circuit through the resistor R ₅ , and the inverted output is added through the resistor R _4. Input to the circuit. FIG. 4 is a diagram showing an input analog signal, an input signal of the adder circuit, and an output signal of the adder circuit. FIG. 5 is a diagram showing an input analog signal and a signal waveform of each part of the first reception data reproducing device 1. In FIG. 4, the waveform shown in (A) is an input analog signal.
The waveform shown in (B) is the waveform of the resistor R ₄ input signal of the adding circuit. The waveform shown in (C) is the waveform of the resistor R ₅ input signal of the adding circuit. The waveform shown in (D) is the output signal waveform of the adder circuit. Here, the resistor R ₅ input signal waveform shown in (C) is delayed by the time shown in (d) from the resistor R ₄ input signal waveform shown in (B).

Further, in the figure, (+ a) (V) and (-a)
The voltage indicated by (V) indicates the potential difference (DC deviation) from the DC component of each waveform with respect to the midpoint of the power supply voltage. The DC deviation of the waveform shown in (B) is inverted, so that the sign is reversed from that of the other waveforms. The power supply voltages of the analog arithmetic circuit and the digital logic circuit are the same. As can be easily understood by referring to FIG. 5, when the waveform of the resistor R ₄ input signal shown in (B) and the resistor R ₅ input waveform shown in (C) are added, as shown in (D) In the rising part of the input analog signal, a differential waveform is generated from the midpoint of the power supply voltage in the direction of lower voltage, and in the falling part of the input analog signal, a differential waveform is generated from the midpoint of the power supply voltage in the direction of higher voltage. The voltage deviation is canceled and the DC deviation becomes (0) V. The output of this differentiating circuit is input to the inverting amplifier at the next stage.

The resistors (R _{6 to} R ₉ ), the operational amplifier (A ₂ ) and the capacitor (C ₂ ) form an inverting amplifier. This inverting amplifier inverts and amplifies the differential circuit output signal shown in FIG. Here, the resistors R ₇ and R ₈ and the capacitor C ₂ form a voltage dividing circuit for setting the positive input of the operational amplifier A ₂ from the power supply voltage to the voltage at which the operating point is the best in order to use the operational amplifier A ₂ with a single power supply. I am configuring. The resistors R ₆ and R ₉ are the feedback resistors of this inverting amplifier. The waveform shown in FIG. 4D is inverted by this inverting amplifier, amplified by a predetermined amplification degree defined by the resistors R ₆ and R ₉ , and input to the positive / negative comparison circuit 3 in the next stage.

The positive / negative comparison circuit 3 includes resistors (R _10-
R _12), a capacitor (C _3, C _4), and consists of an operational amplifier (A _3, A _4). Resistor R ₁₀ to R ₁₂ and capacitor C _3, C ₄ are making a comparison voltage used for comparison of the inverting amplifier output value. That is, the output of the inverting amplifier is compared with the negative input voltage value of the operational amplifier A ₃ and the terminal voltage of the capacitor C ₃ , and the operational amplifier A is operated while the voltage is high.
The output of ₃ becomes a voltage close to (0) V, and becomes the power supply voltage while it is low.

The relationship between the output waveforms of the operational amplifier A ₃ and the inverting amplifier is shown in FIGS. 5 (B) and 5 (C). Here, FIG.
The waveform shown in (A) is the waveform of the input analog signal. Note that this waveform is the same as that shown in FIG. The symbols (A) to (E) attached to the waveforms of FIG. 5 indicate that the waveforms are the waveforms of the respective points of the first received data reproducing apparatus 1 attached in FIG. .

The operational amplifier A ₃ outputs a signal of (0) V (L level) corresponding to the differential waveform of the output waveform of the inverting amplifier in the direction of higher voltage. Here, the voltage value indicated by (0) V in (B) is the potential difference from the power supply voltage to the voltage at which the operating point is the best.

The output of the inverting amplifier is compared with the voltage value of the positive input of the operational amplifier A ₄ and the terminal voltage of the capacitor C ₄ , and while the voltage is low, the output of the operational amplifier A ₄ is (0) V.
The voltage value is close to, and the voltage value close to the power supply voltage while it is high. The relationship between the output waveforms of the operational amplifier A ₄ and the inverting amplifier is shown in FIGS. 5B and 5D. The operational amplifier A ₄ outputs a signal of (0) V (L level) corresponding to the differential waveform of the inverting amplifier output waveform in the direction of lower voltage. The output signal of the positive / negative comparison circuit 3 is input to the logic conversion circuit 4.

The logic conversion circuit 4 is a set / reset flip-flop composed of _two NAND logic circuits (L ₁ , L ₂ ). The logic conversion circuit 4 is a NAN
When (0) V is input to the D logic circuit L ₁ , the output (E) becomes the power supply voltage (logic value 1), and when (0) V is input to the NAND logic circuit L ₂ , the output (E) becomes ( 0) V (logical value 0).

The relationship between the output waveforms of the operational amplifiers A ₃ and A _{4 and} the output waveform of the logic conversion circuit 4 is shown in FIGS. 5 (C), (D),
And (E). As shown in (e) of FIG. 5, the logic conversion circuit 4 is set at the fall of the output waveform of the operational amplifier A ₃ , and the logic conversion circuit 4 is reset at the fall of the output waveform of the operational amplifier A ₄ .

In the positive / negative comparison circuit 3, the operational amplifier A is selected by appropriately selecting the resistors R _{10 to} R _12.
Stabilize the waveform width of digital data by setting the potential difference between the comparison voltage of _{3 and} the comparison voltage of the operational amplifier A ₄ and the voltage of (½) of the power supply voltage to be equal and less susceptible to noise. It is possible to play.

Since the first received data reproducing apparatus 1 is constructed as described above, it is possible to reproduce from the first part of the input of the analog signal, and the first conventional data reproducing apparatus shown in the prior art. The received data reproducing device 7 does not have the waveform error region as shown in FIG. Further, since both outputs of the phase inversion circuit are added, it is possible to cancel the DC component in the input analog signal, and similarly, there is no waveform width unstable region. Therefore, it is possible to reproduce digital data that is stable and has no waveform error even with respect to an input analog having a DC component, and is particularly suitable for mobile equipment under severe temperature and environmental conditions.

In order to further simplify the circuit of the first received data reproducing apparatus 1, the output signal of the adder circuit is input to the positive / negative comparison circuit 3 without passing through the inverting amplifier. In the positive / negative comparison circuit 3, the values of R _{10 to} R ₁₂ are set appropriately, and the value of the comparison voltage applied to the operational amplifiers A ₃ and A ₄ is set appropriately. When the output signal of the operational amplifier A ₃ is (0) V, the logic conversion circuit 4 outputs a logical value 0, and the operational amplifier A 3
_The logic conversion circuit 4 may be configured to output a logical value 1 when the output signal of ₄ is (0) V.

The second embodiment of the present invention will be described below. The second received data reproducing apparatus 8 in the second embodiment is the same as the phase inverting circuit in the received data reproducing apparatus 1.
The state change detection circuit 2 composed of a delay circuit and an adder circuit is replaced with a differentiating circuit composed of an operational amplifier and the inverting amplifier is omitted, and the configuration is changed according to this replacement.

FIG. 6 is a diagram showing a circuit of the second received data reproducing apparatus 8 of the present invention. 6, an operational amplifier (A _21), the capacitor (C _21, C _22), and a resistor (R _21, R ₂₂₎ constitute a differential circuit 12 for differentiating the input analog signal. The differentiating circuit 12 corresponds to the state change detecting circuit 2 in the received data reproducing device 1. In the differential circuit, a non-inverting input is input to the voltage of the operational amplifier A ₂₁ (V _ref) is for operating the operational amplifier A ₂₁ a single power supply, a voltage comprising a power supply voltage to the best operating point ing. This voltage V _ref is created by dividing the power supply voltage with resistors (R _{23 to} R ₂₆ ).

The operational amplifiers (A ₂₂ , A ₂₃ ) and the resistors (R _{23 to} R ₂₆ ) form a positive / negative comparison circuit 13. Here, the operational amplifier A ₂₂ has its inverted input signal and reference voltage V
Comparing _{ref +} , the operational amplifier A _{23 operates} as a voltage comparing circuit (comparator) that compares the non-inverting input signal with the reference voltage V _ref- . The positive / negative comparison circuit 13 corresponds to the positive / negative comparison circuit 3 in the reception data reproducing device 1. The NAND logic circuits (L ₂₁ , L ₂₂ ) form a set / reset flip-flop (SR-FF) 14. The SR-FF 14 corresponds to the logic conversion circuit 4 in the reception data reproducing device 1.

FIG. 7 is a diagram showing a signal waveform in each part of the second received data reproducing apparatus 8 shown by attaching the same reference numerals in FIG. In FIG. 7, the waveform shown in (A) is the waveform of the analog signal input to the second received data reproducing device 8. The waveform shown in (B) is the output waveform of the operational amplifier A ₂₁ . The waveform shown in (C) is the output waveform of the operational amplifier A ₂₃ . When this signal is (0) V, the set / reset flip-flop outputs the logical value 1. The waveform shown in (D) is the output waveform of the operational amplifier A ₂₂ . When this signal is (0) V, the set / reset flip-flop outputs a logical value 0.

The operation of the second received data reproducing device 8 will be described below with reference to FIG. The analog signal shown in FIG. 7 (A) input to the second received data reproducing device 8 is differentiated by the differentiating circuit 12 to have a waveform shown in (B). The operational amplifier A ₂₂ of the positive / negative comparison circuit 13 compares the voltage of this waveform with the comparison voltage V _{ref +} shown in FIG. 7 (B). On the other hand, the operational amplifier A ₂₃ of the positive / negative comparison circuit 13 compares the voltage of this waveform with the comparison voltage V _ref− shown in FIG. _7B .

Here, the comparison voltages V _{ref +} and V _ref- are _{created by dividing the} power supply voltage with the resistors R _{23 to} R ₂₆ . The comparison voltages V _{ref +} and V _ref− have the same potential difference with respect to the voltage at which the power supply voltage becomes the best operating point, as in the reception data reproducing device 1, and are set to voltages that are less susceptible to noise.

Output waveforms of the operational amplifiers A ₂₃ and A ₂₂ are shown in FIGS. 7C and 7D, respectively. As shown in the figure, the operational amplifier A ₂₃ outputs (0) V according to the change in the voltage of the output waveform of the positive / negative comparison circuit 13 to the lower side, and the operational amplifier A ₂₂
Outputs (0) V in accordance with the change in the voltage of the output waveform of the positive / negative comparison circuit 13 to the higher side. The SR-FF 14 outputs the value shown in FIG. 7E in response to the input signal from the positive / negative comparison circuit 13.

According to the second received data reproducing apparatus 8, although the apparatus can be constructed with a simpler structure than the received data reproducing apparatus 1, the digital data can be reproduced similarly to the received data reproducing apparatus 1. Can be configured. Further, by appropriately adding an inverting amplifier in the circuit of the second received data reproducing device 8, the meaning of the signals input to the differentiating circuit 12, the positive / negative comparing circuit 13, and the SR-FF 14 can be arbitrarily set. is there. The circuits of the respective parts of the first received data reproducing apparatus 1 and the second received data reproducing apparatus 8 of the present invention can be replaced with circuits having equivalent functions. The received data reproducing apparatus of the present invention can have various configurations such as the modified examples described in the above embodiments. Further, each of the embodiments described above is merely an example.

[0044]

As described above, according to the present invention, it is possible to accurately reproduce digital data immediately after the start-up of the device or the start of signal input.
Alternatively, it is possible to provide a reception data reproducing device that is resistant to fluctuations in the DC component of the demodulation output.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a configuration of a data communication system to which a first received data reproducing device of the present invention is applied.

FIG. 2 is a diagram showing a configuration of a first received data reproducing device.

FIG. 3 is a diagram showing a circuit of a first received data reproducing device.

FIG. 4 is a diagram showing waveforms of an input analog signal, an input signal of an adding circuit, and an output signal of the adding circuit.

FIG. 5 is a diagram showing an input analog signal and a signal waveform of each part of the first reception data reproducing device.

FIG. 6 is a diagram showing a circuit of a second received data reproducing device of the present invention.

7 is a diagram showing a signal waveform in each part of the second received data reproducing apparatus shown by attaching the same symbols to FIG.

FIG. 8 is a diagram showing a configuration of a first conventional received data reproducing device.

FIG. 9 is a diagram showing an input signal waveform of a first conventional received data reproducing apparatus and a waveform of reproduced digital data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st received data reproduction | regeneration apparatus 2 ... State change detection circuit 3 ... Positive / negative comparison circuit 4 ... Logic conversion circuit 8 ... 2nd received data reproduction apparatus 12 ... Differentiation circuit 13 ... Positive / negative comparison circuit 14 ... SR-FF

Claims (3)

[Claims] 1. A change point detecting means for detecting a rising time point and a falling time point of a band-limited pulse signal of a received signal in which a pulse train is band-limited and may be further superimposed on a DC component. Received data having a pulse generation circuit that generates a pulse signal corresponding to the detected set of rising and falling times or the set of detected falling and rising times Playback device. 2. The change point detecting means includes a phase inverting means for inverting the phase of the received signal, and a delay means for giving a time delay to the inverted output signal or the non-inverted output signal output from the phase inverting means. Of the inverted output signal and the non-inverted output signal,
An addition means for adding an output signal to which a delay is applied and an output signal to which a delay is not applied, and outputting a change point detection signal corresponding to a rising portion and a falling portion of the received signal centered on a certain voltage; , A first reference voltage that is a predetermined voltage value, and a second reference voltage that is a voltage value lower than the first reference voltage, and the voltage value of the change point detection signal are compared to obtain a first reference voltage. When the voltage of the change point detection signal is higher than that, and when the voltage of the change point detection signal is lower than the second reference voltage, the rising time point and the falling time point, or 2. The received data reproducing apparatus according to claim 1, further comprising: a comparing unit that detects a falling time point and a rising time point. 3. The changing point detecting means differentiates the received signal and outputs a changing point detecting signal corresponding to a rising portion and a falling portion of the received signal with a certain voltage as a center, and differentiating means. The first reference voltage, which is a predetermined voltage value, and the second reference voltage, which is a voltage value lower than the first reference voltage, and the voltage value of the change point detection signal are compared, and from the first reference voltage, Also when the voltage of the change point detection signal is high, and when the voltage of the change point detection signal is lower than the second reference voltage, the rising time point and the falling time point corresponding to each case, or 2. The received data reproducing apparatus according to claim 1, further comprising a comparing unit that detects a falling time point and a rising time point.