JPH06131071A - Oscillation noise removing circuit - Google Patents

Abstract

PURPOSE:To provide an oscillation noise removing circuit which is capable of generating a system clock from which the influence of noise is eliminated even if noise of any level is superposed on the output of an oscillator. CONSTITUTION:When a NAND gate 20 detects the rise of a digital signal (b) and a delay signal (d') and RS flip-flops 16, 17 are reset, the NAND gate 20 becomes disable and NOR gates 21, 22 become enable till the next rises of the both signals come. Similarly, the NOR gates 21, 22 detect the falls of the both signals and RS flip-flops 16, 17 are set, the NOR gates 21, 22 become disable and the NAND gate 20 becomes enable till the next falls of the both signals come. Therefore, a system clock SYSCLK form which noise is eliminated is derived from the RS flip-flops 16, 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation noise eliminating circuit suitable for eliminating noise superimposed on an oscillation output.

[0002]

2. Description of the Related Art In recent years, electronic devices (televisions, VTRs) tend to be highly functional. Therefore, recent electronic devices use a plurality of microcomputers and execute complicated arithmetic processing in a short time to realize functional enhancement. by the way,
The arithmetic processing of the microcomputer is designed to be executed in synchronization with the system clock, and the system clock is made using the sine wave output of an oscillator to which a crystal oscillator or the like is externally attached. The above-mentioned oscillator has a characteristic that it is easily affected by power supply noise, etc. Therefore, if noise is superimposed on the sine wave output, the system clock will cause level inversion according to this noise, and as a result, the microcomputer will There is a problem that it malfunctions. Therefore, attention has been paid to the point that the sine wave output is converted into a digital signal through the next-stage inverter, and the inverter is provided with hysteresis to absorb noise, thereby minimizing malfunction of the microcomputer.

[0003]

However, although the microcomputer operates normally for noise that does not exceed the hysteresis width of the inverter, the microcomputer still malfunctions for noise that exceeds the hysteresis width of the inverter. There is a problem, and therefore, the advent of a device that can normally operate a microcomputer against any noise has been desired.

[0004]

The present invention has been made to solve the above-mentioned problems, and is characterized in that an oscillator for generating a sine wave signal of a predetermined frequency and the sine wave are provided. An inverter that converts the signal into a digital signal,
A delay circuit delaying the digital signal so that the noise-corresponding portion of the delay signal does not overlap the noise-corresponding portion of the digital signal on the same time axis when noise is superimposed on the sine wave signal, and an RS flip-flop. And detecting the rising edges of the digital signal and the delayed signal to detect the RS
A rising detection circuit that generates a signal for resetting a flip-flop and prohibits the input of the digital signal and the delayed signal based on the reset output of the RS flip-flop, and a falling edge of the digital signal and the delayed signal. A fall detection circuit that detects and generates a signal for setting the RS flip-flop, and inhibits the input of the digital signal and the delay signal based on the set output of the RS flip-flop. The point is to derive a system clock from which noise is removed from the flip-flop.

[0005]

According to the present invention, when the rising edge detection circuit detects the rising edges of the digital signal and the delayed signal and the RS flip-flop is reset, the rising edge detection circuit is disabled until the next rising edge of both signals arrives. The fall detection circuit is enabled. Similarly, when the falling detection circuit detects the falling of both signals and the RS flip-flop is set, the falling detection circuit is disabled and the rising detection circuit is enabled until the next falling of both signals arrives. Becomes Therefore, the system clock with noise removed is derived from the RS flip-flop.

[0006]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing waveforms at various parts of FIG. In this embodiment, the circuit shown in FIG. 1 is used for the microcomputer.

In FIG. 1, (1) is an oscillator comprising an inverter (2), a resistor (3), an oscillator (4) such as a crystal / ceramic, and capacitors (5) and (6). ), A sine wave signal a having a predetermined frequency is generated. (7) is an inverter with hysteresis, which converts a sine wave signal a to a digital signal b
Is to be converted to. Here, if noise that does not exceed the hysteresis width of the inverter (7) is superimposed on the sine wave signal a, the inverter (7) can sufficiently absorb the noise. Reference numeral (8) is a delay circuit including an inverter (9), a capacitor (10) and an inverter (11) having hysteresis, and delays the digital signal b by a predetermined time. That is, the delay circuit (8) integrates the inverted waveform of the digital signal b passed through the inverter (9) with the capacitor (10) to create the signal c, and further inverts the signal c with the inverter (11). The delay signal c'for the digital signal b is created by. Further, (12) is an inverter (13), a capacitor (14) and an inverter (1
The delay circuit 5) further delays the delay signal c ′ by a predetermined time. That is, the delay circuit (1
2) operates in the same manner as the delay circuit (8) and delay signal c '
To produce a delayed signal d '. Here, the delay circuits (8) and (12) use the digital signal b even when the influence of noise superimposed on the sine wave signal a appears in the delay signal d ′.
And the delay signal d ′ has a delay characteristic capable of delaying the digital signal b by a time width such that noise-corresponding portions do not overlap on the same time axis. Of course, if the noise has a level that can be absorbed by the hysteresis of the inverters (11) and (15), the influence of noise does not appear in the delay signal d ′, so that the noise-corresponding portion of the digital signal b influences the logical operation in the subsequent stage. Never give.

The NAND gates (16) and (17) form an RS flip-flop, and the system clock SY
It generates SCLK. The system clock S
YSCLK is used not only in the microcomputer but also as a delay signal g through the inverters (18) and (19) and is fed back to the NAND gate and NOR gate described later.

The above-mentioned NAND gate (20) is a rising edge detection circuit which generates a signal e which resets the RS flip-flop when the rising edges of the digital signal b and the delay signal d'are detected. The NAND gate (20)
Indicates that when the microcomputer is released from reset, that is, when the reset signal * RES is "1", the microcomputer is enabled, and when the RS flip-flop is reset, that is, the delay signal g is "0", the microcomputer is disabled. Become. That is, in the reset period of the RS flip-flop after the NAND gate (20) detects the rising edges of the digital signal b and the delay signal d ′, the noise-corresponding portion of the digital signal b and the delay signal d ′ is the NAND gate (2
It is blocked at 0) and does not affect the RS flip-flop. In the set period of the RS flip-flop, the delay signal g becomes "1" and the NAND gate (20) is enabled, but the noise corresponding portions of the digital signal b and the delay signal d'are on the same time axis. Since they do not overlap with each other, the noise-corresponding portions of the digital signal b and the delay signal d ′ are blocked by the NAND gate (20) and do not affect the RS flip-flop.

The above-mentioned NOR gates (21) and (22) are fall detection circuits which generate a signal f for setting the RS flip-flop when the fall of the digital signal b and the delay signal d'is detected. The NOR gate (2
2) is a reset signal * RES when the microcomputer is released from reset, that is, via the inverter (23)
When the inverted output of the above is "0", it is enabled, and at the same time, the NOR gate (21) is disabled when the RS flip-flop is set, that is, when the delay signal g becomes "1". That is, the NOR gate (2
In the set period of the RS flip-flop after 1) has detected the falling edges of the digital signal b and the delayed signal d ′,
The noise-corresponding portions of the digital signal b and the delayed signal d ′ are N
It is blocked by the OR gate (21) and does not affect the RS flip-flop. Further, in the reset period of the RS flip-flop, the delay signal g becomes “0” and the NOR gate (21) is enabled, but the noise corresponding portions of the digital signal b and the delay signal d ′ are on the same time axis. The noise-corresponding portions of the digital signal b and the delay signal d'are blocked by the NOR gate (21) and do not affect the RS flip-flop.

The operation of the circuit of FIG. 1 configured as above will be described with reference to the waveforms of FIG. The alternate long and short dash line in FIG. 2 indicates the hysteresis width of the inverters (7), (11) and (15). First, when the signal * RES becomes "0" to reset the microcomputer, the signals e and f become "1" and "0" respectively, so the system clock SYSCL
K becomes "1". At this time, the NAND gate (20) and the NOR gate (22) are in the disabled state. After that, when the signal * RES becomes "1" to release the reset from the microcomputer, only the signal f changes to "1". At this time, the NAND gate (20) and the NOR gate (22) are enabled.

On the other hand, when noise exceeding the hysteresis width of the inverter (7) is superposed on the sine wave signal a, the inverter (7) cannot absorb the noise and the digital signal b undergoes level inversion according to the noise. ing.
The digital signal b is delayed by the delay circuits (8) and (12), but in the case of this embodiment, noise is converted to the inverter (11).
The delay signal d ′ cannot be completely absorbed due to the hysteresis of (15).
Indicates that the level inversion still occurs in response to noise. However, since the level inversion part (same level part) based on noise of the digital signal b and the delay signal d ′ does not overlap on the same time axis, the NAND gate (20) outputs the digital signal b and the delay signal d ′ based on noise. There is no rise detection. Similarly, a NOR gate (21)
Does not detect the fall of the digital signal b and the delay signal d ′ based on noise.

When the delay signal d'rises at time t1 after the digital signal t0 rises at time t0, NA is obtained at time t1.
The ND gate (20) detects the rising edge, and the signal e falls to "0". In response to this, the RS flip-flop is reset and the system clock SYSCLK falls to "0". When the delay signal g falls at time t2 after the inversion time of the inverters (18) and (19), the NAND gate (20) is disabled and the signal e rises to "1", and at the same time, the NOR gate (21). Is enabled. In this state, even if the digital signal b and the delay signal d ′ cause level inversion due to noise, NA
Since the ND gate (20) and the NOR gate (21) cut off the input, the system clock SYSCLK in the subsequent stage is not affected.

Next, when the delay signal d'falls at time t4 after the digital signal b falls at time t3, N is reached at time t4.
The OR gate (21) detects the fall and the signal f falls to "0". In response to this, the RS flip-flop is set, and the system clock SYSCLK rises to "1". When the delay signal g rises at time t5 after the inversion time of the inverters (18) and (19), the NAND gate (20) is enabled, and at the same time, the NOR gate (21) is enabled and the signal f becomes ". 1 "
Rise to. In this state, the digital signal b and the delayed signal d '
Even if the level inversion occurs due to noise, the NAND gate (20) and the NOR gate (21) block the input, so that the system clock SYSCLK in the subsequent stage is not affected.

By repeating the above operation, even if noise exceeding the hysteresis of the inverters (7), (11) and (15) is superimposed on the oscillation output of the oscillator (1), the noise is completely removed from the RS flip-flop. The generated system clock SYSCLK can be generated. Then, the microcomputer operates normally based on the system clock SYSCLK.

[0016]

According to the present invention, no matter what level of noise is superposed on the oscillator output, the level-inverted portions of the digital signal and the delay signal due to noise are blocked by the rising detection circuit and the falling detection circuit. A normal system clock irrelevant to noise is derived from the RS flip-flop, and there is an advantage that a device that uses the system clock can be reliably operated normally.

[Brief description of drawings]

FIG. 1 is a diagram showing an oscillation noise elimination circuit of the present invention.

FIG. 2 is a time chart showing waveforms of respective parts of FIG.

[Explanation of symbols]

 (1) Oscillator (7) Inverter (8) (12) Delay circuit (16) (17) (20) NAND gate (21) (22) NOR gate

Claims (2)

[Claims] 1. An oscillator for generating a sine wave signal of a predetermined frequency, an inverter for converting the sine wave signal into a digital signal, and when noise is superimposed on the sine wave signal, a noise corresponding portion of the delay signal is the A delay circuit that delays the digital signal so as not to overlap a noise-corresponding portion of the digital signal on the same time axis, an RS flip-flop, and a RS flip-flop that detects the rising edges of the digital signal and the delayed signal. A rising edge detection circuit that generates a signal for resetting and prohibits the input of the digital signal and the delayed signal based on the reset output of the RS flip-flop, and detects the falling edges of the digital signal and the delayed signal. A signal for setting the RS flip-flop is generated and based on the set output of the RS flip-flop. There and a trailing edge detection circuit for prohibiting the input of the digital signal and the delay signal, oscillator noise rejection circuit, which comprises deriving a system clock obtained by removing noise from the RS flip-flop. 2. The oscillation noise elimination circuit according to claim 1, wherein the delay circuit comprises a delay capacitor and an inverter having hysteresis.