JP3108226B2 - Oscillation noise elimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation noise removing circuit suitable for removing noise superimposed on an oscillation output.

[0002]

2. Description of the Related Art In recent years, electronic devices (televisions, VTRs) have become more sophisticated. Therefore, recent electronic devices use a plurality of microcomputers and execute complex arithmetic processing in a short time to realize enhanced functions. by the way,
The arithmetic processing of the microcomputer is executed in synchronization with a system clock, and the system clock is generated by using a sine wave output of an oscillator externally provided with a crystal oscillator or the like. The above-described oscillator has characteristics that are easily affected by power supply noise and the like. Therefore, when noise is superimposed on the sine wave output, the level of the system clock is inverted according to the noise, and as a result, the microcomputer is not operated. There is a problem of malfunction. Accordingly, attention has been paid to the point that the sine wave output is converted into a digital signal via the next-stage inverter, and the inverter is provided with hysteresis to absorb noise and minimize malfunction of the microcomputer.

[0003]

However, the microcomputer normally operates for noise that does not exceed the hysteresis width of the inverter, but the microcomputer still malfunctions for noise that exceeds the hysteresis width of the inverter. There is a problem, and there has been a long-awaited demand for a device capable of operating a microcomputer normally against any noise.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is characterized by an oscillation circuit for generating a sine wave signal of a predetermined frequency,
An inverter that converts the sine wave signal into a digital signal, and when noise is superimposed on the sine wave signal, such that the noise-corresponding portion of the delay signal does not overlap the noise-corresponding portion of the digital signal on the same time axis. A delay circuit that delays the digital signal, an RS flip-flop, a rising detection circuit that detects a rising edge of the digital signal and the delayed signal and issues a signal for resetting the RS flip-flop; A fall detection circuit that detects a fall of the delay signal and generates a signal for setting the RS flip-flop, and disables the rise detection circuit based on a reset output of the RS flip-flop. And the falling detection circuit is enabled, and the RS flip-flop is set. Based on the force by the falling detection circuit disabled state while an enable state the rising edge detection circuit is to derive a system clock obtained by removing noise from the RS flip-flop.

[0005]

According to the present invention, when the rise detection circuit detects the rise of the digital signal and the delay signal and the RS flip-flop is reset, the rise detection circuit is disabled until the next rise of both signals comes. The falling detection circuit is enabled. Similarly, when the falling detection circuit detects the falling of both signals and the RS flip-flop is set, the falling detection circuit is disabled and the rising detection circuit is enabled until the next falling of both signals arrives. Becomes Therefore, a system clock from which noise has been removed is derived from the RS flip-flop.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing waveforms at various points in FIG. In this embodiment, the circuit shown in FIG. 1 is used for a microcomputer.

In FIG. 1, (1) is an oscillator composed of an inverter (2), a resistor (3), an oscillator (4) such as crystal / ceramic, and capacitors (5) and (6). ) To generate a sine wave signal a of a predetermined frequency. (7) is an inverter having hysteresis, which converts a sine wave signal a into a digital signal b.
Is converted to Here, if noise that does not exceed the hysteresis width of the inverter (7) is superimposed on the sine wave signal a, the inverter (7) can sufficiently absorb the noise. (8) is a delay circuit including an inverter (9), a capacitor (10), and an inverter (11) having hysteresis, and delays the digital signal b by a predetermined time. That is, the delay circuit (8) integrates the inverted waveform of the digital signal b through the inverter (9) with the capacitor (10) to create a signal c, and further inverts the signal c with the inverter (11). Thus, a delay signal c ′ for the digital signal b is created. (12) is an inverter (13), a capacitor (14) and an inverter (1) having hysteresis.
5), which further delays the delay signal c 'by a predetermined time. That is, the delay circuit (1
2) operates in the same manner as the delay circuit (8) to operate the delay signal c '.
Is generated. Here, the delay circuits (8) and (12) are capable of controlling the digital signal b even when the effect of noise superimposed on the sine wave signal a appears in the delay signal d '.
It is assumed that the digital signal b has a delay characteristic that can delay the digital signal b by a time width such that the noise-corresponding portions of the delay signal d ′ do not overlap on the same time axis. Of course, if the noise can be absorbed by the hysteresis of the inverters (11) and (15), the effect of the noise does not appear in the delay signal d '. I will not give.

The NAND gates (16) and (17) constitute an RS flip-flop, and the system clock SY
SCLK is generated. The system clock S
The YSCLK is used as a delay signal g via inverters (18) and (19) as well as used inside the microcomputer, and is fed back to a NAND gate and a NOR gate described later.

The above-mentioned NAND gate (20) is a rise detecting circuit for generating a signal e for resetting the RS flip-flop when detecting the rise of the digital signal b and the delay signal d '. The NAND gate (20)
Indicates that the microcomputer is enabled when the reset is released, that is, when the reset signal * RES is "1", and disabled when the RS flip-flop is reset, that is, when the delay signal g becomes "0". Become. That is, during the reset period of the RS flip-flop after the NAND gate (20) detects the rise of the digital signal b and the delay signal d ', the noise-corresponding portion of the digital signal b and the delay signal d' is the NAND gate (2
0) and does not affect the RS flip-flop. Also, during the set period of the RS flip-flop, the delay signal g becomes "1" and the NAND gate (20) is enabled, but the noise-corresponding portions of the digital signal b and the delay signal d 'are on the same time axis. Therefore, the portions corresponding to the noise of the digital signal b and the delay signal d 'are cut off by the NAND gate (20), and do not affect the RS flip-flop.

The above-mentioned NOR gates (21) and (22) are fall detecting circuits for generating a signal f for setting the RS flip-flop when detecting the fall of the digital signal b and the delay signal d '. The NOR gate (2
2) is a reset signal * RES via the inverter (23) when the microcomputer is released from reset.
Is in an enabled state when the inverted output is "0", and at the same time, the NOR gate (21) is disabled when the RS flip-flop is set, that is, when the delay signal g becomes "1". That is, the NOR gate (2
After 1) detects the fall of the digital signal b and the delay signal d ′, during the set period of the RS flip-flop,
The noise-corresponding portion of the digital signal b and the delayed signal d ′ is N
It is cut off by the OR gate (21) and does not affect the RS flip-flop. During the reset period of the RS flip-flop, the delay signal g becomes "0" and the NOR gate (21) is enabled, but the noise-corresponding portions of the digital signal b and the delay signal d 'are on the same time axis. Therefore, the portions corresponding to the noise of the digital signal b and the delay signal d 'are cut off by the NOR gate (21) and do not affect the RS flip-flop.

The operation of the circuit of FIG. 1 configured as described above will be described with reference to the waveforms of FIG. The dashed line in FIG. 2 indicates the hysteresis width of the inverters (7), (11), and (15). First, when the signal * RES becomes "0" to reset the microcomputer, the signals e and f become "1" and "0", respectively, so that the system clock SYSCL
K becomes "1". At this time, the NAND gate (20) and the NOR gate (22) are disabled. Thereafter, when the signal * RES changes to "1" to release the reset of the microcomputer, only the signal f changes to "1". At this time, the NAND gate (20) and the NOR gate (22) are enabled.

On the other hand, when noise exceeding the hysteresis width of the inverter (7) is superimposed on the sine wave signal a, the inverter (7) cannot completely absorb the noise, and the digital signal b undergoes level inversion according to the noise. ing.
The digital signal b is delayed by the delay circuits (8) and (12). In the case of the present embodiment, the noise is reduced by the inverter (11).
It cannot be absorbed by the hysteresis of (15) and the delayed signal d '
Is a state in which level inversion has still occurred according to noise. However, since the level inversion portions (same level portions) of the digital signal b and the delay signal d ′ based on the noise do not overlap on the same time axis, the NAND gate (20) outputs the digital signal b and the delay signal d ′ based on the noise. No rise detection is performed. Similarly, a NOR gate (21)
Does not detect the falling of the digital signal b and the delay signal d ′ based on the noise.

When the delay signal d 'rises at time t1 after the rise of the digital signal t0 at time t0, the NA at time t1
The ND gate (20) detects the rise, and the signal e falls to "0". In response, the RS flip-flop is reset, and the system clock SYSCLK falls to "0". When the delay signal g falls at time t2 after the inversion time of the inverters (18) and (19), the NAND gate (20) is disabled and the signal e rises to "1", and at the same time, the NOR gate (21) Is enabled. In this state, even if the digital signal b and the delayed signal d ′ undergo level inversion based on noise, NA
Since the ND gate (20) and the NOR gate (21) cut off the input, the subsequent system clock SYSCLK is not affected.

Next, when the delay signal d 'falls at time t4 after the digital signal b falls at time t3, N
The OR gate (21) detects the fall, and the signal f falls to “0”. In response, the RS flip-flop is set, and the system clock SYSCLK rises to "1". When the delay signal g rises at time t5 after the inversion time of the inverters (18) and (19), the NAND gate (20) is enabled, and at the same time the NOR gate (21) is enabled and the signal f becomes " 1 "
Stand up. In this state, the digital signal b and the delay signal d '
Causes a level inversion based on noise, the NAND gate (20) and the NOR gate (21) cut off the input, so that the subsequent system clock SYSCLK is not affected.

By repeating the above operation, even if noise exceeding the hysteresis of the inverters (7), (11) and (15) is superimposed on the oscillation output of the oscillator (1), the noise is completely removed from the RS flip-flop. The generated system clock SYSCLK can be generated. The microcomputer operates normally based on the system clock SYSCLK.

[0016]

According to the present invention, no matter what level of noise is superimposed on the oscillator output, the level inversion portion of the digital signal and the delay signal based on the noise is cut off by the rise detection circuit and the fall detection circuit. , A normal system clock irrespective of noise is derived from the RS flip-flop, and an advantage that a device using the system clock can be reliably operated normally is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an oscillation noise elimination circuit of the present invention.

FIG. 2 is a time chart showing waveforms of respective parts in FIG.

[Explanation of symbols]

 (1) Oscillator (7) Inverter (8) (12) Delay circuit (16) (17) (20) NAND gate (21) (22) NOR gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/04 H03B 1/04 H03B 5/06 H03B 5/32 H03K 5/01 H03K 12/00

Claims (2)

(57) [Claims] An oscillator for generating a sine wave signal having a predetermined frequency; an inverter for converting the sine wave signal into a digital signal; and a noise-corresponding portion of a delay signal when noise is superimposed on the sine wave signal. A delay circuit for delaying the digital signal, an RS flip-flop, and a rising edge of the digital signal and the delay signal so that the digital signal does not overlap with a noise-corresponding portion of the digital signal on the same time axis.
Generates a signal to reset the RS flip-flop
Rise detection circuit to detect the fall of the digital signal and the delay signal
Generates a signal to set the RS flip-flop
Falling detection circuit, and based on a reset output of the RS flip-flop,
The rising edge detection circuit is disabled and
The falling edge detection circuit is enabled, and based on the set output of the RS flip-flop,
The rising edge detection circuit is enabled and the rising edge detection circuit is enabled.
An oscillation noise removing circuit , wherein a system clock from which noise has been removed is derived from the RS flip-flop by disabling a down detection circuit. 2. The oscillation noise removing circuit according to claim 1, wherein said delay circuit includes a delay capacitor and an inverter having hysteresis.