JPH04162726A - Insulated-gate field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To easily shorten the length of a channel by assigning the opposite conductivity type to the edge of a gate electrode to that of an impurity diffused region for a drain region. CONSTITUTION:The conductivity type of edge 5'' of a gate electrode 5 is set to be the opposite to that of an impurity diffused region 3 for a drain region. That is, if the conductivity type of a doped polysilicon edge 5'' of the electrode 5 is a p type, the conductivity type of the region 3 is an n type. On the contrary, if the conductivity type of the edge 5'' is an n type, the conductivity type of the region 3 is a p type. The doped polysilicon 5'' except the edge 5'' of the electrode 5 may be the same conductivity type as that of the edge 5'', or opposite to it. Accordingly, an electric field effect due to a drain voltage is alleviated. Thus, the length of a channel can be easily shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate field effect semiconductor device, particularly a so-called LDD (Lightly Doped D
The present invention relates to an insulated gate field effect semiconductor device having a (rain) structure.

[Conventional technology]

Figure 2 shows a conventional insulated gate field effect transistor (hereinafter referred to as r MOSFET J) with an LDD structure.
Hail the main parts of the structure.

In the conventional MOSFET shown in FIG.
A gate electrode 55 for controlling a channel region CH between the source and drain is provided on the surface of the 0 with an insulating layer 56 interposed therebetween, making it an insulated gate type. This gate electrode 55 is made of polysilicon (polycrystalline silicon) doped with impurities, and is composed of a main body part 55' and an edge part 55#, and the edge part 55# is formed on the side surface of the main body part 55'. This is the so-called Idowall. The impurity diffusion regions 51 and 52 are formed of impurities implanted using the gate electrode 55 as a mask, and the channel side end portions are formed by the low impurity concentration region 51a,
It is 52a. The low impurity concentration regions 51a and 52a are formed by ion implantation and diffusion of impurities in a state where only the main body 55' of the gate electrode 55 is present, and after this, an edge 55'' is added to the main body 55'. The portion formed by ion implantation and diffusion of impurities in this state is combined with the previously formed portion to form impurity diffusion regions 51 and 52. In the subsequent process, the edge 55'' is used as a mask. Therefore, this MOSFET has an edge 55'' above the low impurity concentration regions 51a and 52a.
This low impurity concentration region 52a, called a DD structure, functions to suppress hot electron deterioration and improve reliability.

[Problem to be solved by the invention]

However, the MO3FET has a problem in that it is difficult to shorten the channel length. It is difficult to miniaturize and increase integration.

This is the edge 55'' - the insulating layer 56 - the low impurity concentration region 52
A MO3 structure is formed, but here, since the conductivity type of the edge 55'' of the gate electrode 55 is the n-type and the conductivity type of the low impurity concentration region 52a, the electric field due to the drain voltage is The effect is easy to achieve, and it is difficult to shorten the channel length.

In view of the above circumstances, the present invention provides an LD with a short channel length.
An object of the present invention is to provide an insulated gate field effect semiconductor device having a D structure.

[Means to solve the problem]

In order to solve the above problems, an insulated gate field effect semiconductor device of the present invention has impurity diffusion regions for a source region and a drain region formed on the surface of a semiconductor substrate. A gate electrode is provided via an insulating layer to control a channel region between the regions, and the gate electrode is made of polysilicon doped with impurities, and the channel side end of the impurity diffusion region for the drain region is a low impurity concentration region. In a configuration in which the edge of the gate electrode extends above this low impurity concentration region, the conductivity type of the edge of the gate electrode is set to be opposite to the conductivity type of the impurity diffusion region for the drain region. I have to.

This invention will be explained in more detail below.

When the conductivity type of the doped polysilicon edge of the gate electrode is p type, the conductivity type of the impurity diffusion region for the drain region is n type. Conversely, when the conductivity type of the edge is n type, the conductivity type of the impurity diffusion region for the drain region is p type. The doped polysilicon portion other than the edge of the gate electrode may be of the same conductivity type as the edge, or may be of the opposite conductivity type.

Usually, the channel-side end of the impurity diffusion region for the source region is also a low impurity concentration region like the drain region, but the source region does not need to have a low impurity concentration region.

[For production]

In the insulated gate field effect semiconductor device of the present invention, since the conductivity type of the edge of the gate electrode is opposite to the conductivity type of the impurity diffusion region for the drain region, the threshold voltage increases by about 1.1V. In the case of the present invention, in the MO3 structure of the edge of the gate electrode, the insulating layer, and the low impurity concentration region, the work function φ is as shown in FIG.
MS# is 0.85eV, and conventionally, as shown in FIG. 4, the work function is φMS'ζ-0.25eV, and the difference between the two is about 1. There is leV. As the threshold voltage becomes higher, the electric field effect caused by the drain voltage becomes less effective than in the past, so the channel length can be shortened. A semiconductor device that can be operated appropriately with a channel length of 21 or less can be realized.

〔Example〕

Next, an example of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a MOSFET according to an embodiment of the invention.

In the MOSFET shown in FIG. 1, n-type impurity diffusion regions 2.3 for source and drain regions are formed on the surface of a semiconductor substrate 1, and a channel region CH between the source and drain is formed on the surface of the semiconductor substrate 1. A gate electrode 5 for controlling is provided via an insulating layer 6 to form an n-channel insulated gate type. This gate electrode 5 is made of polysilicon doped with impurities (doped polysilicon) and is composed of a main body 5' and an edge 5'', and this edge 5'' is formed on the side surface of the main body 5'. This is the so-called Idowall. The impurity diffusion region 2.3 is formed of impurities implanted using the gate electrode 5 as a mask, and the end portion on the channel side is formed in the low impurity concentration regions 2a, 3.
It is a. The low impurity concentration regions 2a and 3a are connected to the gate electrode 5.
It is formed by ion-implanting and diffusing impurities in a state where only the main body portion 55' is present, and the high impurity concentration region 2b is formed.
, 3b are then formed by ion-implanting and diffusing impurities with the edge 5'' added to the main body 5'. In the subsequent process of forming high impurity concentration regions 2b and 3b,
Since # serves as a mask, an edge 5'' extends above the low impurity concentration regions 2a and 3a.

A source electrode 11 is in contact with the high impurity concentration region 2b of the source region, and a drain electrode 12 is in contact with the high impurity concentration region 3b of the drain region. Note that 13 is a protective film.

This MOSFET thus has an LDD structure with a low impurity concentration (low doping) region 3a at the end of the drain region, and this low impurity concentration region 3a has the function of suppressing hot electron deterioration and increasing reliability. Fulfill.

In the MOSFET, the edge 5# of the gate electrode 5 is of the p' type, which is the opposite conductivity type to the low impurity concentration region 3a of the drain region, and as mentioned above, the length of the channel region CH can be shortened. It is.

Note that the edge portion 5# is formed as a side wall on the side surface of the main body portion 5' that was previously formed, but in this case,
For example, the polysilicon layer deposited for sidewall formation is made into a p"polysilicon layer sufficiently doped with n-type impurities, and then etched to form the sidewalls. Conventionally, impurities are not doped. Since the sidewall was made using a polysilicon layer, the n-type impurity was introduced into the edge polysilicon portion in the subsequent n-type impurity implantation process, making it n-type.

Of course, in the case of the present invention, n-type impurities are introduced into the edge 5'' in the n-type impurity implantation step, but the n-type impurities are doped in advance in a sufficient amount and the conductivity type is reversed. It won't happen.

This invention is not limited to the above embodiments. For example, in Figure 1, a p-channel type MOSF in which n and p are reversed.
Other embodiments include an ET or a MOSFET in which n'' of the main body portion 5' of the gate electrode 5 in FIG. 1 is p+ and the entire gate electrode 5 is p''.

〔Effect of the invention〕

As described above, in the LDD structure insulated gate field effect semiconductor device according to the present invention, the conductivity types of the edge of the gate electrode and the impurity diffusion region for the drain region are different, and the field effect due to the drain voltage is is relaxed, allowing for well-behaved devices with short channel lengths.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a MOSFET according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the main structure of a conventional MOSFET, and FIG. 3 is a semiconductor device according to the present invention. FIG. 4 is an explanatory diagram showing the energy state in the MO3 structure in a conventional insulated gate semiconductor device having an LDD structure. 1... Semiconductor substrate 2... Impurity diffusion region for source region 3... Impurity diffusion region 3a for drain region
...Low impurity concentration region 5...Gate electrode 5"...
・Edge (of gate electrode) 6...Insulating layer CH・
...Channel area agent Patent attorney Takehiko Matsumoto 1st [! 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 Impurity diffusion regions for a source region and a drain region are respectively formed on the surface of a semiconductor substrate, and a gate electrode for controlling a channel region between the source and drain is provided on the surface of the semiconductor substrate via an insulating layer, The gate electrode is made of polysilicon doped with impurities, and the channel side end of the impurity diffusion region for the drain region is a low impurity concentration region, and the edge of the gate electrode is above this low impurity concentration region. An insulated gate field effect semiconductor device according to the present invention, wherein the conductivity type of the edge of the gate electrode is opposite to the conductivity type of the impurity diffusion region for the drain region.