JPH04160457A - Dma controller - Google Patents

Abstract

PURPOSE:To decrease the number of elements and to facilitate the incorporation of a microcomputer by providing one set of control registers regardless of the number of channels. CONSTITUTION:An entirety control part 2 saves the contents of a control register part 9 on a memory in the case of channel transition, and generates and sends control information on the channel to a data control part 4. The data control part 4 is controlled to write the contents of the control register 9 in a memory area indicated by a control information address register part and reads contents whose transfer is to be started next out to the control register part 9. Then the entirety control part 2 generates a control signal to be sent to the data control part 4 with this information and performs DMA transfer with an external device through an external bus 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA controller with a plurality of transfer channels.

[Conventional technology]

A block diagram of a conventional DMA controller is shown in FIG. The figure shows the case of a DMA controller having four transfer channels. In the figure, (1) is a transfer request control unit that mediates transfer requests from external devices input to the transfer request signal terminal (6:) and sends a transfer start request to the overall control unit (2); (2) is an overall control unit (8) which reads control information from a control register unit (8) upon receiving a transfer start request from a transfer request control unit (1) and generates a control signal to cause the data control unit (4) to execute the transfer; (4) is a control register section that holds control information regarding the transfer method, transfer control, channel status, etc. of each transfer channel, and (4) is a control register section that stores control signals sent by the overall control section (2), external devices, and data. , address, data control unit that exchanges various control signals and executes transfer, (6) is a transfer request signal terminal that inputs a transfer request from an external device, (6) is a data control unit that exchanges data between units inside the DMA controller, An internal bus (γ) is an internal bus for exchanging addresses and various control signals, and an external bus (γ) is for exchanging data, addresses, and various control signals with external devices such as DMA controllers such as cPTJ and memory.

FIG. 5 is an internal block diagram of the control register section (8) in FIG. 4. In the figure, (301) is a group of control registers such as an address register, a byte count register, a transfer mode register, and a channel status register, which store control information for each channel.

Next, the operation will be explained. When there is a transfer request from an external device to the transfer request signal terminal (6), the transfer request control unit (
1) mediates the request. If the transfer request is accepted, the transfer request control unit (1) requests the general control unit (2) to start the transfer, requests the transfer, sends the channel number on which the transfer is to be started, and sends the general control unit (2) a request to start the transfer. 2) controls the data control unit (4) according to the information held in the register group corresponding to the channel number among the register groups of the control register unit (8).
) generates a control signal to be sent to the The data control section (4) is controlled by this control signal and performs DMA transfer with an external device via an external bus (7).

[Problem to be solved by the invention]

Since the conventional DMA controller is configured as described above, in order to store the information necessary for transfer, it is necessary to provide as many control registers as the number of channels, which increases the number of elements that make up the control register section. This DMA
When realizing the controller as a semiconductor integrated circuit, the chip area increases, making it difficult to incorporate the S%KDMA controller into a microcomputer.

This invention was made to solve the above-mentioned problems, and the control register section can be set to 1 regardless of the number of channels.
It is an object of the present invention to provide a DMA controller that is particularly suitable for being built into a microcomputer by performing transfer by providing only a set of sets, reducing the number of elements constituting the DMA controller.

[Means to solve problems]

The DMA controller according to the present invention includes a set of control registers that hold control information related to the transfer method, transfer control, channel state, etc. of the transfer channel that is executing the transfer, and There is a control information address register for each channel that holds the start address of the control information in the control information register, and when a transfer request occurs and the channel is switched, the contents of the control register group are transferred to the channel in the control information address register or to the transfer channel before switching. Writes the contents indicated by the corresponding register to the memory area designated as the start address,
Next, the control means generates a control signal for reading out the contents of a memory area whose start address is the contents indicated by the register corresponding to the channel to which transfer is to be started in the control information address register to the control register group. It is something that [Operation] When a channel changes, the DMA controller of the present invention transfers the control information of the channel stored in the control register section before the channel is switched to the contents of the register corresponding to this channel among the control information address registers. Writes the control information of this channel from the memory whose starting address is the content indicated by the register corresponding to the channel to which transfer is to be started in the control information address register to the control register section. Store in. DMA transfer is executed based on the information stored in this control register section.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a DMA controller that is an embodiment of the present invention. In the figure, a DM with four transfer channels
This is the case of A controller. In the figure, (1) arbitrates transfer requests from external devices input to the transfer request signal terminal (5), and controls the overall control unit (2) K transfer start request and the channel number on which the transfer is to be started. When a transfer request control unit (2) receives a transfer start request from the transfer request control unit (1), if a channel transition occurs, the transfer request control unit (2) saves the contents of the control register unit (9) to memory and transfers it from the memory. The operation of reading the control information of the channel to be started and looking into the control register section (9), and the operation of reading the control information from the control register section (9) and generating a control signal that causes the data control section C4 to execute the transfer. Overall control unit (9
) is a control register section that holds control information regarding the transfer method, transfer control, channel status, etc. of the channel in progress, and (4) is controlled by the control signal sent from the overall control section (2). A data control unit that exchanges data, addresses, and various control signals with external spices and executes transfers;
[8] is a control information address register section that holds the start address of the control information of the channel stored in the memory of each transfer channel; (6) is a transfer request signal terminal for manually inputting a transfer request from an external device; ) is an internal bus that exchanges data, addresses, and various control signals between units inside the IIMA controller, and (7) is an internal bus that allows the DMA controller to exchange data, addresses, and various control signals with external devices such as the CPU, controller 10, and memory. This is an external bus.

FIG. 2 is an internal block diagram of the control register section (9) in FIG. 1. In the figure, (901) is an address register that stores control information of the channel that is currently transferring;
A group of control registers such as a byte count register, transfer mode register, and channel status register.

FIG. 3 is an internal block diagram of the control information address register p section+81 in FIG. In the figure, (801
) is a control information address register that holds the start address of channel control information stored in the memory of each transfer channel.

Next, the operation will be explained. When there is a transfer request from an external device to the transfer request signal terminal (6), the transfer request control unit (
1) mediates the request. When the transfer request is accepted, the transfer request control unit (1) requests the overall control unit (2) to start the transfer and request the transfer, and sends the channel number on which the transfer is to be started. When a channel transition occurs, the overall control unit (2) saves the contents of the control register unit (9) in memory, and transfers the control information of the channel about to start transfer from the memory to the control register unit (9). It generates a control signal for reading into the data controller (2) and sends it to the data control unit (2). The data control unit (2) is controlled by this control signal, and transfers the contents of the control register unit (9) to the control information address register (8) corresponding to the transfer channel before the channel is switched. Write the contents indicated by 801) into the memory area as the start address, and then write the control information address register (801) corresponding to the channel to which transfer is to be started in the control information address register section (8).
The content indicated by 801) is read out from the memory area whose starting address is the content indicated by 801) into the control register unit (9). After this, the overall control section (2) controls the control register section (9
) generates a control signal to be sent to the data control unit (4). The data control unit (4) is controlled by this control signal and communicates with external devices through the external bus (7).
Perform MA transfer.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to provide only one set of control registers regardless of the number of channels.
The number of elements constituting the A controller can be reduced, and in particular, the DMA controller can be easily incorporated into a microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a DMA controller that is an embodiment of the present invention, FIG. 2 is an internal block diagram of the control register section in FIG. 1, and FIG. 3 is an internal block diagram of the control information address register section in FIG. 1. Internal block diagram, Figure 4 is the conventional D
A block diagram of the MA controller, FIG. 5 is an internal block diagram of the control register section in FIG. 4. In the figure, (1) is a transfer request control section, (2) is an overall control section, C4) is a data control section, (8) is a control information address register section, (9) is a control register section, (801) indicates a control information address register, and (901) indicates a control register group. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.ノ Figure 1 Figure 5 Procedural amendment C voluntary) Ear shoes 2, title of the invention DMA:! /). -3, Relationship with the case of the person making the amendment Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent address: Tokyo 2-2-3-6 Marunouchi, Chiyoda-ku
, Detailed description of the invention in the specification subject to amendment. line, page 6 @ line 8, page 9, lines 8-9. In line ①, ``Contents, starting address'' should be corrected to ``Contents, original song address.'' (!1 Correct "byte count register transfer mode" t "byte count register, transfer mode" in line #I6 of statement page 1.)

Claims (1)

[Scope of Claims] In a DMA controller having a plurality of transfer channels, a set of control registers retaining control information regarding a transfer method, transfer control, channel state, etc. of the transfer channel during transfer; a control information address register for each channel that holds the start address of the control information stored in the memory of each transfer channel; and a control information address register for each channel that holds the start address of the control information stored in the memory of each transfer channel; Out of the registers, the contents indicated by the register corresponding to the transfer channel before the channel is switched are written to the memory area having the start address, and then the register corresponding to the channel to start transfer among the control information address registers is written. A DAM controller comprising: a control means for generating a control signal for reading the contents of a memory area having the contents indicated by as a start address into the control register group.