JPH04154124A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04154124A JPH04154124A JP2279832A JP27983290A JPH04154124A JP H04154124 A JPH04154124 A JP H04154124A JP 2279832 A JP2279832 A JP 2279832A JP 27983290 A JP27983290 A JP 27983290A JP H04154124 A JPH04154124 A JP H04154124A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- gate
- substrate
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 14
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000460 chlorine Substances 0.000 claims abstract description 13
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 13
- 239000011261 inert gas Substances 0.000 claims abstract description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 17
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 15
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021529 ammonia Inorganic materials 0.000 abstract description 2
- 239000002994 raw material Substances 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000001590 oxidative effect Effects 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置の製造方法に係り、特に窒化膜上の酸化膜と
ゲート酸化膜を同時に形成する方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of simultaneously forming an oxide film on a nitride film and a gate oxide film.
窒化膜上の酸化膜厚のゲート酸化膜厚に対する比を大き
く形成する方法の提供を目的とし。The object of the present invention is to provide a method for forming a large ratio of the thickness of an oxide film on a nitride film to the thickness of a gate oxide film.
Si基板及び該Si基板上に形成された窒化膜を、塩素
或いは塩素を含む化合物と酸素と不活性ガスを含む10
00°C以上の雰囲気にさらすことにより、該Si基板
上にゲート酸化膜を形成し、かつ同時に該窒化膜上に酸
化膜を形成する半導体装置の製造方法により構成する。The Si substrate and the nitride film formed on the Si substrate are treated with chlorine or a compound containing chlorine, oxygen, and an inert gas.
A semiconductor device manufacturing method is employed in which a gate oxide film is formed on the Si substrate and an oxide film is simultaneously formed on the nitride film by exposing the semiconductor device to an atmosphere of 00° C. or higher.
また、前記塩素を含む化合物は塩化水素であり。Further, the compound containing chlorine is hydrogen chloride.
該塩化水素の前記酸素に対する比は、酸素1容に対して
塩化水素0.001容以上、1容以下である半導体装置
の製造方法により構成する。The ratio of the hydrogen chloride to the oxygen is 0.001 volume or more and 1 volume or less of hydrogen chloride per 1 volume of oxygen.
また、前記窒化膜及び前記窒化膜上の酸化膜(Jフロー
ティングゲートとコントロールゲート間C層間絶縁膜の
一部である半導体装置の製造方法により構成する。Further, the nitride film and the oxide film on the nitride film (which is part of the C interlayer insulating film between the J floating gate and the control gate) are formed by a method for manufacturing a semiconductor device.
本発明は半導体装置の製造方法に係り、特に窒化膜上の
酸化膜とゲート酸化膜を同時に形成する方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for simultaneously forming an oxide film on a nitride film and a gate oxide film.
近年の半導体デバイスの高集積化の要求に伴いデバイス
の横方向の縮小のみならず縦方向の薄膜化も要求されて
いる。ところが、電源電圧は一定であり1層間絶縁膜に
かかる電解強度は高くなりそのため、薄くて膜質のよい
絶縁膜か要求されている。With the recent demand for higher integration of semiconductor devices, there is a demand not only for devices to be smaller in the horizontal direction but also to be thinner in the vertical direction. However, since the power supply voltage is constant, the electrolytic strength applied to one interlayer insulating film increases, and therefore a thin insulating film of good quality is required.
従来、 E P ROM(Erasable Pro
grammableRead−Only Memory
)の層間絶縁膜は、フローティングゲートであるポリシ
リコンを酸化して形成していたか、ポリシリコン酸化膜
はフローティングゲートのエツジ部での電界集中の影響
により、このエツジ部からフローティングゲート中の電
荷か抜けてしまうという問題かあった。そこで、エツジ
部での電界集中の影響を避けるため1層間絶縁膜として
酸化膜/窒化膜/酸化膜の3層膜か用いられるようにな
ってきている。Conventionally, E P ROM (Erasable Pro
grammableRead-Only Memory
) was formed by oxidizing the polysilicon that is the floating gate, or because the polysilicon oxide film is affected by electric field concentration at the edge of the floating gate, the charges in the floating gate are removed from the edge of the floating gate. There was a problem with it falling out. Therefore, in order to avoid the influence of electric field concentration at the edge portion, a three-layer film of oxide film/nitride film/oxide film has been used as an interlayer insulating film.
第3図はEPROMの断面図を示し、IはSi基板、2
は素子分離膜、3は第1のゲート酸化膜。Figure 3 shows a cross-sectional view of the EPROM, where I is a Si substrate, 2
3 is an element isolation film, and 3 is a first gate oxide film.
4はフローティングゲート、5は第1の酸化膜。4 is a floating gate, and 5 is a first oxide film.
6は窒化膜、8は第2の酸化膜、9は第2のゲート酸化
膜、 10はコントロールゲート、11ゲート電極、1
2はソース・トレイン領域、13は絶縁膜、 14はソ
ース・ドレイン電極を表す。6 is a nitride film, 8 is a second oxide film, 9 is a second gate oxide film, 10 is a control gate, 11 is a gate electrode, 1
2 represents a source/train region, 13 represents an insulating film, and 14 represents a source/drain electrode.
第1の酸化膜5と窒化膜6と第2の酸化膜8はフローテ
ィングゲート4とコントロールゲート1゜間の層間絶縁
膜を形成している。各膜の厚さは。The first oxide film 5, nitride film 6, and second oxide film 8 form an interlayer insulating film between the floating gate 4 and the control gate 1°. What is the thickness of each membrane?
例えば2次の如くである。For example, it is quadratic.
第1の酸化膜5:100人
窒化膜6:100人
第2の酸化膜8:20人
第2の酸化膜は、 900 ℃程度の水蒸気雰囲気で窒
化膜6を酸化することにより形成する。First oxide film: 5:100 Nitride film: 6:100 Second oxide film: 8:20 The second oxide film is formed by oxidizing the nitride film 6 in a water vapor atmosphere at about 900°C.
ところで、工数削減をもくろみ、第2の酸化膜の形成と
同時に周辺トランジスタの第2のゲート酸化膜9を形成
しようとすると問題を生じる。即ち、窒化膜6上に第2
の酸化膜8を20人の厚さに形成する時、Si基板l上
には第2のゲート酸化膜9か約2000人の厚さに形成
されてしまう。これてはゲート酸化膜が厚過ぎて周辺ト
ランジスタとして機能しない。また、第2のゲート酸化
膜9の厚さを200〜300人とするように酸化条件を
設定すると、今度は第2の酸化膜8の厚さが12人程度
と薄くなり、フローティングゲート4から電荷か抜けて
しまうという問題を生じる。By the way, if an attempt is made to form the second gate oxide film 9 of the peripheral transistor at the same time as the formation of the second oxide film in order to reduce the number of steps, a problem will arise. That is, the second layer is formed on the nitride film 6.
When the second gate oxide film 8 is formed to a thickness of about 200 nm, a second gate oxide film 9 is formed on the Si substrate 1 to a thickness of about 2000 nm. In this case, the gate oxide film is too thick to function as a peripheral transistor. Furthermore, if the oxidation conditions are set so that the thickness of the second gate oxide film 9 is 200 to 300, the thickness of the second oxide film 8 will be as thin as about 12, and the floating gate 4 will be A problem arises in that charge is lost.
従って、従来方法では窒化膜6上の第2の酸化膜8と、
Si基板1上の第2のゲート酸化膜9を同時に形成する
ことができず、窒化膜6上の第2の酸化膜8とSi基板
1上の第2のゲート酸化膜9は別々に工程で形成する必
要かあり、工程か煩雑になっていた。Therefore, in the conventional method, the second oxide film 8 on the nitride film 6,
The second gate oxide film 9 on the Si substrate 1 cannot be formed at the same time, and the second oxide film 8 on the nitride film 6 and the second gate oxide film 9 on the Si substrate 1 are formed in separate steps. This made the process complicated.
本発明は、窒化膜6上の第2の酸化膜8とSi基板1上
の第2のゲート酸化膜9を同時に形成し。In the present invention, the second oxide film 8 on the nitride film 6 and the second gate oxide film 9 on the Si substrate 1 are formed simultaneously.
第2のゲート酸化膜9を機能する程度に薄く、シかも第
2の酸化膜8をフローティングゲート4から電荷か抜け
ない程度に厚く形成する方法を提供することを目的とす
る。It is an object of the present invention to provide a method for forming the second gate oxide film 9 to be thin enough to function, and to form the second oxide film 8 to be thick enough to prevent charges from leaking from the floating gate 4.
上記課題は、Si基板l及び該Si基板l上に形成され
た窒化膜6を、塩素或いは塩素を含む化合物と酸素と不
活性ガスを含むl000℃以上の雰囲気にさらすことに
より、該Si基板l上にゲート酸化膜9を形成し、かつ
同時に該窒化膜6上に酸化膜8を形成する半導体装置の
製造方法によって解決される。The above problem can be solved by exposing the Si substrate 1 and the nitride film 6 formed on the Si substrate 1 to an atmosphere of 1000° C. or higher containing chlorine or a compound containing chlorine, oxygen, and an inert gas. This problem is solved by a method of manufacturing a semiconductor device in which a gate oxide film 9 is formed on the nitride film 6 and an oxide film 8 is formed on the nitride film 6 at the same time.
また、前記塩素を含む化合物は塩化水素であり。Further, the compound containing chlorine is hydrogen chloride.
該塩化水素の前記酸素に対する比は、酸素l容に対して
塩化水素0.001容以上、1容以下である半導体装置
の製造方法によって解決される。The ratio of hydrogen chloride to oxygen is solved by a semiconductor device manufacturing method in which the ratio of hydrogen chloride to oxygen is 0.001 volume or more and 1 volume or less per 1 volume of oxygen.
また、前記窒化膜6及び前記窒化膜6上の酸化膜8は、
フローティングゲート4とコントロールゲート10間の
層間絶縁膜の一部である半導体装置の製造方法によって
解決される。Further, the nitride film 6 and the oxide film 8 on the nitride film 6 are
This problem is solved by a method of manufacturing a semiconductor device that is part of the interlayer insulating film between the floating gate 4 and the control gate 10.
Si基板1上にゲート酸化膜9及び窒化膜6上に酸化膜
8を同時に形成する際、塩素或いは塩素を含む化合物と
酸素と不活性ガスを含む雰囲気を用いることにより、水
蒸気雰囲気を用いる場合よりも、酸化膜8の厚さのゲー
ト酸化膜9の厚さに対する比を大きくすることができる
。そして、酸化膜8の厚さはフローティングゲート4か
ら電荷か抜けない程度に厚(、ゲート酸化膜9の厚さは
トランジスタとして機能する程度に薄く形成することか
できる。When forming the gate oxide film 9 on the Si substrate 1 and the oxide film 8 on the nitride film 6 at the same time, using an atmosphere containing chlorine or a compound containing chlorine, oxygen, and an inert gas is easier than using a water vapor atmosphere. Also, the ratio of the thickness of oxide film 8 to the thickness of gate oxide film 9 can be increased. The oxide film 8 can be formed to be thick enough that no charge can escape from the floating gate 4 (and the gate oxide film 9 can be formed thin enough to function as a transistor).
さらに、酸化膜8の厚さのゲート酸化膜9の厚さに対す
る比は酸化膜を形成する際の雰囲気の温度か高い程大き
くなり、 1ooo°C以上で大きな効果を生む。一方
、酸化膜の成長速度は雰囲気の温度が高い程大きくなっ
て成長膜厚の制御か難しくなる。そこで、不活性ガスで
酸化性ガスを希釈し。Further, the ratio of the thickness of the oxide film 8 to the thickness of the gate oxide film 9 increases as the temperature of the atmosphere when forming the oxide film increases, and a large effect is produced at a temperature of 100° C. or higher. On the other hand, the growth rate of the oxide film increases as the temperature of the atmosphere increases, making it difficult to control the thickness of the grown film. Therefore, the oxidizing gas is diluted with an inert gas.
不活性ガスの割合を増加して成長速度を抑制するように
する。Increase the proportion of inert gas to suppress the growth rate.
塩素を含む化合物としては塩化水素を用いることかでき
る。酸素に対する塩化水素の比は、酸素1容に対して塩
化水素0゜001容以上、l容以下であり、 0.00
1容未満では効果がなく、1容より多いとSi基板1表
面を荒らしてしまう。Hydrogen chloride can be used as the chlorine-containing compound. The ratio of hydrogen chloride to oxygen is 0.001 volume or more and 1 volume or less of hydrogen chloride to 1 volume of oxygen, and 0.00
If it is less than 1 volume, there is no effect, and if it is more than 1 volume, the surface of the Si substrate 1 will be roughened.
また2本発明の方法は、フローティングゲート4とコン
トロールゲート10間の層間絶縁膜の一部である窒化膜
の上に酸化膜1周辺トランジスタを形成する領域のSi
基板1上にゲート酸化膜を同時に形成する工程に、極め
て有効に適用することかできる。In addition, in the method of the present invention, an oxide film 1 is formed on the nitride film which is a part of the interlayer insulating film between the floating gate 4 and the control gate 10 in a region where a transistor is to be formed.
The present invention can be very effectively applied to the process of simultaneously forming a gate oxide film on the substrate 1.
第2図(a) 〜(f)はEPROM形成の工程順断面
図てあり、さらに詳しくは紫外線消去型ROM形成の工
程順断面図である。以下、これらの図を参照しながら、
紫外線消去型EPROM形成の概略を説明する。FIGS. 2(a) to 2(f) are sectional views in the order of steps for forming an EPROM, and more specifically, sectional views in the order of steps for forming an ultraviolet erasable ROM. Below, referring to these figures,
An outline of the formation of an ultraviolet erasable EPROM will be explained.
第2図(a)参照
Si基基板−LOCO3法により素子分離膜2を形成し
た後、熱酸化法によりSi基板1上に第1のゲート酸化
膜3を形成する。第1のゲート酸化膜3の厚さは2例え
ば、200人である。Refer to FIG. 2(a) Si-based substrate - After an element isolation film 2 is formed by the LOCO3 method, a first gate oxide film 3 is formed on the Si substrate 1 by a thermal oxidation method. The thickness of the first gate oxide film 3 is 2, for example, 200.
気相成長法によりフローティングゲートとなるポリSi
を2例えば、 1000人の厚さに成長し、不純物とし
て燐を導入する。燐を拡散した後、ポリSiをパターニ
ングして、フローティングゲート4を形成する。Poly-Si that becomes a floating gate by vapor phase growth
For example, grow 2 to a thickness of 1000 and introduce phosphorus as an impurity. After diffusing phosphorus, the poly-Si is patterned to form floating gates 4.
第2図(b)参照 フローティングゲート4の表面を熱酸化して。See Figure 2(b) The surface of floating gate 4 is thermally oxidized.
第1の酸化膜(ボトムのポリSi酸化膜)5を形成する
。酸化条件は1例えば2次の如くである。A first oxide film (bottom poly-Si oxide film) 5 is formed. The oxidation conditions are as follows.
酸化雰囲気:窒素またはアルゴンで希釈した乾燥酸素
雰囲気温度: 1000°C
酸化膜の厚さ:100人
次に、全面に例えばアンモニア(NH3)とシラン(S
iH4)を原料ガスとして気相成長法により、窒化膜6
を成長する。成長温度は9例えば、720°C1成長膜
厚は2例えば、100人である。Oxidizing atmosphere: Dry oxygen diluted with nitrogen or argon Temperature: 1000°C Oxide film thickness: 100 people Next, the entire surface is coated with ammonia (NH3) and silane (S).
A nitride film 6 is grown by vapor phase growth using iH4) as a raw material gas.
grow. The growth temperature is 9, for example, 720° C., and the growth film thickness is 2, for example, 100.
第2図(c)参照
レジスト7をマスクにして2周辺トランジスタ領域の窒
化膜6と第1の酸化膜3をエツチングにより除去する。Referring to FIG. 2(c), using the resist 7 as a mask, the nitride film 6 and first oxide film 3 in the two peripheral transistor regions are removed by etching.
窒化膜6の除去はドライエツチングて行い、第1の酸化
膜3の除去はフッ酸系の液によるウェットエツチングに
より行う。The nitride film 6 is removed by dry etching, and the first oxide film 3 is removed by wet etching using a hydrofluoric acid solution.
第2図(d)参照
レジスト7を除去した後、窒化膜6と周辺トランジスタ
領域のSi基板1とを同時に酸化し、窒化膜6上に第2
の酸化膜81周辺トランジスタ領域のSi基板1上に第
2のゲート酸化膜9を形成する。After removing the resist 7 (see FIG. 2(d)), the nitride film 6 and the Si substrate 1 in the peripheral transistor area are simultaneously oxidized, and a second
A second gate oxide film 9 is formed on the Si substrate 1 in the transistor region around the oxide film 81.
酸化条件は2例えば 次の如くである。For example, the oxidation conditions are 2. It is as follows.
酸化雰囲気:酸素2容
無水塩化水素1容
窒素IO容
雰囲気温度:1100°C
第2の酸化膜8の厚さ、25人
第2のゲート酸化膜9の厚さ、300人第2図(e)参
照
全面にポリSiを気相成長法により3000人の厚さに
成長し、気相拡散により不純物として燐を導入する。Oxidation atmosphere: 2 volumes of oxygen 1 volume of anhydrous chloride 1 volume of nitrogen IO Atmosphere temperature: 1100°C Thickness of second oxide film 8, 25 people Thickness of second gate oxide film 9, 300 people Figure 2 (e ) Poly-Si is grown on the entire reference surface to a thickness of 3000 nm by vapor phase growth, and phosphorus is introduced as an impurity by vapor phase diffusion.
その後ポリSiをパターニングして2.第2の酸化膜8
上にコントロールゲート10.第2のゲート酸化膜9上
にゲート電極11を形成する。After that, pattern the poly-Si and 2. Second oxide film 8
Control gate 10 on top. A gate electrode 11 is formed on second gate oxide film 9.
ゲート電極11両側のSi基板1に不純物として。As an impurity in the Si substrate 1 on both sides of the gate electrode 11.
例えば、ヒ素を導入し、ソース・ドルイン領域12を形
成する。For example, arsenic is introduced to form the source/druin region 12.
第2図(f)参照
全面に絶縁膜13として、気相成長法によりSiO□膜
を成長し、ソース・トレイン領域12に開口してソース
・ドレイン電極14を形成する。Referring to FIG. 2(f), an SiO□ film is grown as an insulating film 13 over the entire surface by vapor phase growth, and a source/drain electrode 14 is formed with openings in the source/train region 12.
このようにして、紫外線消去型ROMか形成できる。In this way, an ultraviolet erasable ROM can be formed.
なお、窒化膜6上に第2の酸化膜89周辺トランジスタ
領域のSi基板1上に第2のゲート酸化膜9を同時に形
成する際、雰囲気温度と時間を変えて第2の酸化膜8の
膜厚と第2のゲート酸化膜9の膜厚の関係を詳細に調べ
た。Note that when simultaneously forming the second oxide film 89 on the nitride film 6 and the second gate oxide film 9 on the Si substrate 1 in the peripheral transistor region, the second oxide film 8 is formed by changing the ambient temperature and time. The relationship between the thickness and the thickness of the second gate oxide film 9 was investigated in detail.
その結果を第1図に示す。比較のため、従来例も示す。The results are shown in FIG. A conventional example is also shown for comparison.
曲線(a)〜(d)の条件は次の如くである。The conditions for curves (a) to (d) are as follows.
(a) 1100°C酸素2容、無水塩化水素1容。(a) 1100°C 2 volumes of oxygen, 1 volume of anhydrous hydrogen chloride.
窒素10容
(b) 1000°C(上に同じ)
(c) 900℃ (上に同じ)
(d) 900°C水蒸気 (従来例)第1図よ
り、従来の水蒸気に変えて無水塩化水素添加の酸素を用
いることにより、第1の酸化膜の膜厚の第2のゲート酸
化膜の膜厚に対する比を大きくすることができることが
わかる。10 volumes of nitrogen (b) 1000°C (same as above) (c) 900°C (same as above) (d) 900°C steam (Conventional example) From Figure 1, anhydrous hydrogen chloride is added instead of conventional steam. It can be seen that by using oxygen of 10%, the ratio of the thickness of the first oxide film to the thickness of the second gate oxide film can be increased.
さらに、雰囲気温度を上げることによってもその比を大
きくすることかてき、 1000°Cとする時。Furthermore, the ratio can be increased by increasing the ambient temperature, which is 1000°C.
効果か大きい。The effect is great.
一方、雰囲気の温度が高いと酸化膜の成長速度か大きく
制御しにくくなるので、窒素あるいはアルゴンのような
不活性ガスにより希釈する。On the other hand, if the temperature of the atmosphere is high, the growth rate of the oxide film becomes large and difficult to control, so it is diluted with an inert gas such as nitrogen or argon.
なお、酸素に対する塩化水素の比は、酸素1容に対して
塩化水素0.001容以上、1容以下であるべきである
。0.001容未満では効果がなく、1容より多いとS
i基板1表面を荒らしてしまう。Note that the ratio of hydrogen chloride to oxygen should be 0.001 volume or more and 1 volume or less of hydrogen chloride per 1 volume of oxygen. There is no effect if it is less than 0.001 volume, and if it is more than 1 volume, it is S.
The surface of the i-board 1 will be roughened.
なお、塩化水素に代えて塩素ガスを用いることもてきる
。Note that chlorine gas may be used instead of hydrogen chloride.
第4図は第2の酸化膜のリーク特性を第2の酸化膜の膜
厚をパラメータとして示したもので、酸化膜/窒化膜/
酸化膜の3層膜にかかる電界強度に対して、その中を流
れる電流の電流密度の関係を示す。Figure 4 shows the leakage characteristics of the second oxide film using the film thickness of the second oxide film as a parameter.
The relationship between the electric field strength applied to the three-layer oxide film and the current density of the current flowing therein is shown.
第2の酸化膜の膜厚か12人の場合はリークか大きく問
題であるが、22人の場合の程度であれば、実用上問題
か少ない。If the thickness of the second oxide film is 12 people, leakage is a major problem, but if it is about the same as 22 people, it is practically a problem.
さらに、第5図は第2の酸化膜の膜厚とフローティング
ゲート4からの電荷損失の関係を示したもので、第2の
酸化膜の膜厚30人の場合を基準として示している。電
荷損失は2例えばトランジスタの閾値電圧V l hの
経時変化から評価することかできる。Further, FIG. 5 shows the relationship between the thickness of the second oxide film and the charge loss from the floating gate 4, and is shown based on the case where the thickness of the second oxide film is 30 people. The charge loss can be evaluated, for example, from the change over time in the threshold voltage V l h of the transistor.
第2の酸化膜の膜厚か30人より大きいと、電荷損失が
必ずしもゼロになるわけではないか、実用上問題がない
。一方、第2の酸化膜の膜厚が小さ過ぎると電荷損失が
大きく問題となる。If the thickness of the second oxide film is greater than 30, the charge loss will not necessarily be zero, and there will be no practical problem. On the other hand, if the thickness of the second oxide film is too small, charge loss becomes large and becomes a problem.
本発明の方法は、フローティングゲート4とコントロー
ルゲート10間の眉間絶縁膜の一部である窒化膜の上に
酸化膜2周辺トランジスタを形成する領域のSi基板1
上にゲート酸化膜を同時に形成するような1例えば、紫
外線消去型EPROMの製造工程に適用する時、極めて
有効となり、工数を削減し、製造を容易にする効果を奏
するものである。In the method of the present invention, an oxide film 2 is formed on a Si substrate 1 in a region where a peripheral transistor is to be formed on a nitride film which is a part of an insulating film between the floating gate 4 and a control gate 10.
When applied to the manufacturing process of, for example, an ultraviolet erase type EPROM in which a gate oxide film is simultaneously formed on top of the film, it is extremely effective, and has the effect of reducing the number of steps and facilitating manufacturing.
以上説明したように1本発明によれば1層間絶縁膜を構
成する窒化膜上の酸化膜と周辺トランジスタのゲート酸
化膜を同時に形成することか可能となり1例えば、紫外
線消去型EPROMの製造工程に適用する時、工数を削
減して製造を容易にする効果を奏し、しかもフローティ
ングゲートからの電荷損失を少なくして信頼性の向上に
寄与するものである。As explained above, according to the present invention, it is possible to simultaneously form the oxide film on the nitride film constituting the interlayer insulating film and the gate oxide film of the peripheral transistor. When applied, it has the effect of reducing man-hours and facilitating manufacturing, and also reduces charge loss from the floating gate, contributing to improved reliability.
第1図は第2のゲート酸化膜の膜厚と第2の酸化膜の膜
厚の関係を示す図。
第2図(a) 〜(f)はEPROM形成の工程順断面
図。
第3図はEPROMの断面図。
第4図は第2の酸化膜のリーク特性。
第5図は第2の酸化膜の膜厚と電荷損失の関係を示す図
である。
図こおいて。
1はSi基板。
2は素子分離膜。
3はゲート酸化膜であって第1のゲート酸化膜。
4はフローティングゲート。
5は酸化膜であって第1の酸化膜。
6は窒化膜。
7はレジスト
8は酸化膜であって第2の酸化膜。
9はゲート酸化膜であって第2のゲート酸化膜。
10はコントロールゲート。
11はゲート電極。
12はソース・ドレイン領域。
13は絶縁膜。
14はソース・ドレイン電極
第2カゲート醗化腰の膜厚と第2の酸化膜の膜厚の関係
第 1 図
EPF?OMの断面図
第 5 図
(b)
第2図(活の1)
(e)
(f)
EPROM形成の工程順断面図
第2図(’fの2)
tw強度E (MV/cm)
第2の醇化膜のリーフ特・1注
¥14 図
腰
浮(A)
第2の醇イヒ欣の膠厚ど電荷頂矢の開怪第 5 図FIG. 1 is a diagram showing the relationship between the thickness of the second gate oxide film and the thickness of the second oxide film. FIGS. 2(a) to 2(f) are sectional views showing steps of forming an EPROM. FIG. 3 is a cross-sectional view of the EPROM. Figure 4 shows the leakage characteristics of the second oxide film. FIG. 5 is a diagram showing the relationship between the thickness of the second oxide film and charge loss. Figure here. 1 is a Si substrate. 2 is an element isolation film. 3 is a gate oxide film, which is a first gate oxide film. 4 is a floating gate. 5 is an oxide film, which is a first oxide film. 6 is a nitride film. 7, resist 8 is an oxide film, which is a second oxide film. 9 is a gate oxide film, which is a second gate oxide film. 10 is a control gate. 11 is a gate electrode. 12 is a source/drain region. 13 is an insulating film. 14 shows the relationship between the film thickness of the second oxide film of the source/drain electrodes and the film thickness of the second oxide film. Cross-sectional view of OM Figure 5 (b) Figure 2 (active 1) (e) (f) Step-by-step cross-sectional view of EPROM formation Figure 2 ('f 2) tw strength E (MV/cm) 2nd Reef of the liquefied membrane special・1 note ¥14 Figure Koshibu (A) The second liquefied membrane of the glue thickness and the opening of the electric charge top arrow Figure 5
Claims (1)
れた窒化膜(6)を、塩素或いは塩素を含む化合物と酸
素と不活性ガスを含む1000℃以上の雰囲気にさらす
ことにより、該Si基板(1)上にゲート酸化膜(9)
を形成し、且つ同時に該窒化膜(6)上に酸化膜(8)
を形成することを特徴とする半導体装置の製造方法。 〔2〕前記塩素を含む化合物は塩化水素であり、該塩化
水素の前記酸素に対する比は、酸素1容に対して塩化水
素0.001容以上、1容以下であることを特徴とする
請求項1記載の半導体装置の製造方法。 〔3〕前記窒化膜(6)及び前記窒化膜(6)上の酸化
膜(8)は、フローティングゲート(4)とコントロー
ルゲート(10)間の層間絶縁膜の一部であることを特
徴とする請求項1記載の半導体装置の製造方法。[Scope of Claims] [1] The Si substrate (1) and the nitride film (6) formed on the Si substrate (1) are heated to a temperature of 1000° C. or higher containing chlorine or a compound containing chlorine, oxygen, and an inert gas. A gate oxide film (9) is formed on the Si substrate (1) by exposing it to an atmosphere of
and simultaneously form an oxide film (8) on the nitride film (6).
1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device. [2] The chlorine-containing compound is hydrogen chloride, and the ratio of the hydrogen chloride to the oxygen is 0.001 volume or more and 1 volume or less of hydrogen chloride per 1 volume of oxygen. 1. The method for manufacturing a semiconductor device according to 1. [3] The nitride film (6) and the oxide film (8) on the nitride film (6) are part of an interlayer insulating film between the floating gate (4) and the control gate (10). 2. The method of manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
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JP2279832A JP2639202B2 (en) | 1990-10-18 | 1990-10-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
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JP2279832A JP2639202B2 (en) | 1990-10-18 | 1990-10-18 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04154124A true JPH04154124A (en) | 1992-05-27 |
JP2639202B2 JP2639202B2 (en) | 1997-08-06 |
Family
ID=17616545
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JP2279832A Expired - Fee Related JP2639202B2 (en) | 1990-10-18 | 1990-10-18 | Method for manufacturing semiconductor device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11121450A (en) * | 1997-10-17 | 1999-04-30 | Samsung Electron Co Ltd | Formation of dual oxide film |
US6878594B2 (en) | 1997-07-16 | 2005-04-12 | Fujitsu Limited | Semiconductor device having an insulation film with reduced water content |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS61294871A (en) * | 1985-06-21 | 1986-12-25 | コミツサリア ア レネルジイ アトミツク | Production of integrated circuit |
-
1990
- 1990-10-18 JP JP2279832A patent/JP2639202B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS61294871A (en) * | 1985-06-21 | 1986-12-25 | コミツサリア ア レネルジイ アトミツク | Production of integrated circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6878594B2 (en) | 1997-07-16 | 2005-04-12 | Fujitsu Limited | Semiconductor device having an insulation film with reduced water content |
US7232720B2 (en) | 1997-07-16 | 2007-06-19 | Fujitsu Limited | Method for fabricating a semiconductor device having an insulation film with reduced water content |
US7422942B2 (en) | 1997-07-16 | 2008-09-09 | Fujitsu Limited | Method for fabricating a semiconductor device having an insulation film with reduced water content |
JPH11121450A (en) * | 1997-10-17 | 1999-04-30 | Samsung Electron Co Ltd | Formation of dual oxide film |
Also Published As
Publication number | Publication date |
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JP2639202B2 (en) | 1997-08-06 |
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