JPH04152657A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable mixing to be promoted at a joint between a lower wiring layer and an upper wiring layer so as to obtain a contact stable in resistance by a method wherein a conductive sputter etching preventing film of metal or polycrystalline silicon is formed on an interlayer insulating film which covers the lower aluminum wiring layer. CONSTITUTION:A conductive sputter etching preventing film 101 of metal or polycrystalline silicon is formed on an interlayer insulating film 5 which covers a lower aluminum wiring layer 4, a conductive film 7 serving as an upper wiring layer connected to the lower wiring layer 4 through a contact hole 6a bored in the etching preventive film 101 and the interlayer insulating film 5 is formed, and an upper wiring layer is formed of the conductive film 7 and the etching preventive film 101. Therefore, when deteriorated part in the surface of the lower wiring layer 4 exposed inside the contact hole 6a is removed through sputter etching, even if the interlayer insulating film 5 is formed of silicon oxide, oxygen produced by the decomposition of the film 5 can be reduced, and the formation of the oxide of an insulating film on the surface of the lower wiring layer 4 can be reduced to the irreducible minimum.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same.
More specifically, the present invention relates to improvements in a multilayer wiring structure in a semiconductor device and a method for forming a multilayer wiring structure in a semiconductor device.

[Conventional technology]

In a semiconductor device, after forming an element structure on a semiconductor substrate, various types of wiring are usually required to electrically connect the elements and to connect the elements to an external circuit.

Conventionally, this type of connection wiring has been made using a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, and
Aluminum films, aluminum alloy films, etc. are used, and in particular, in recent high-speed, highly integrated devices, it is necessary to reduce wiring resistance. A wiring structure is considered essential.

FIG. 5 shows a DRAM (DynamiDRAM) as an example of a conventional semiconductor device having this type of aluminum multilayer wiring structure.
c. Random Access Memory) This is a schematic diagram showing the general configuration of the device.

That is, in the configuration of the conventional device shown in FIG. 5, reference numeral 1 is a silicon semiconductor substrate, 2 is a DRAM element (stack cell) formed on the main surface of the silicon semiconductor substrate 1, and 3 is a DRAM element (stack cell) formed on the main surface of the silicon semiconductor substrate 1. This is a base insulating film deposited to cover the DRAM element (stack cell) 2. Also,
Reference numeral 4 denotes a first layer aluminum wiring selectively formed on the base insulating film 3; 5, an interlayer insulating film deposited on the base insulating film 3 including the first layer aluminum wiring 4; 6, the first layer insulating film 3; In order to connect the layer aluminum wiring 4 and the upper second layer aluminum wiring,
This is a connection portion including a contact hole 6a opened in the interlayer insulating film 5. Furthermore, 7 is a second layer of aluminum wiring selectively formed on the interlayer insulating film 5, and 8 is a second layer of aluminum wiring formed selectively on the interlayer insulating film 5; Interlayer insulating film 5 including second layer aluminum wiring 7
A protective insulating film is deposited on top.

In the conventional semiconductor device shown in FIG. This is an important technical point that affects the level.

Next, the manufacturing flow of the conventional semiconductor device shown in the structure shown in FIG. 5 will be described, focusing in particular on the method of forming the connecting portions between the interconnections in each layer.

As mentioned above, the multilayer wiring structure is generally a combination of polycrystalline silicon wiring, high melting point metal wiring, high melting point metal silicide wiring, aluminum wiring, and aluminum alloy wiring. Simplifying this,
As shown in FIG. 5, the case of an "aluminum two-layer wiring structure" in which both the first and second layer wirings are mainly aluminum wiring will be described.

FIGS. 6 [I] to [■] are sectional views sequentially schematically showing the formation flow of the two-layer aluminum wiring structure.

[I] Process On the main surface of the silicon semiconductor substrate l, an element isolation oxide film 301. l-transfer gate electrode 302° impurity diffusion layer 303. Word 1i1304. memory node 3
05. Capacitor insulating film 306. A DRAM element (stacked cell) 2 consisting of a cell plate 307 and a cell plate 307 is formed.

[Step 113.

After depositing a base insulating film 3 on the entire surface of the silicon semiconductor substrate l on which the DRAM element (stacked cell) 2 is formed, contact holes 308 are selectively formed in required portions by photolithography and etching techniques. Open the hole.

Next, the first layer aluminum wiring 4 is selectively formed on the base insulating film 3 including the contact hole 308 portion.

In recent submicron devices, a) prevention of junction leakage due to abnormal reaction (alloys bike) between the aluminum wiring and the silicon substrate (impurity diffusion layer) at the contact portion;

b) Prevention of contact failure caused by silicon in the aluminum alloy film being deposited on the contact portion by solid phase epitaxial growth.

C) Improved resistance to stress migration, which can cause wire breakage due to film stress in the interlayer insulating film or protective insulating film formed on the upper layer of the aluminum wiring.

For these reasons, the first layer aluminum wiring 4 includes a barrier metal film 310 such as titanium nitride (TiN) or titanium-tungsten (Tie), and Aj2-3i, Aj2.
A wiring having a structure in combination with an aluminum alloy film 311 such as -3i-Cu is employed.

Each of these layers 310 and 311 is normally deposited by sputtering and selectively patterned as the first layer aluminum wiring 4 by photolithography and etching.

Cm] process.

An interlayer insulating film 5 is deposited over the entire surface of the base insulating film 3 including the first layer aluminum wiring 4.

The interlayer insulating film 5 may be formed by, for example, chemical vapor deposition (
Chemical Vapor Deposition
A lower silicon oxide film 321 deposited by a CVD method (hereinafter referred to as CVD method), an inorganic coated insulating film 322 as an intermediate layer coated, and carbon dioxide as described above.
Upper silicon oxide film 32 deposited by VD method
An insulating film structure in which 3 and 3 are sequentially combined is used.

The lower silicon oxide film 321 is usually made of silane (SiH,) gas and oxygen (0,) gas.

Alternatively, using nitrous oxide (N, 0) gas,
It is deposited by CVD using heat or plasma at a deposition temperature of about 450°C, but recently T E OS has been developed because it has the advantage of good step coverage.
(T6jrB-Ej)1yl-Ortho-Sili
Organic silane-based materials such as cate) are also used.

The inorganic coated insulating film 322 as the intermediate layer is used for planarization, and the inorganic coated insulating film 322 is generally composed mainly of silanol (Si (OH) 4) or the like. Yes, after spin coating, 40
The surface of the silicon oxide film 321 is flattened by baking at a temperature of about 0 to 450° C. to form a silicon oxide film.

However, this inorganic coated insulating film 322 has a relatively high hygroscopicity, and if exposed to the connection parts and side walls, it will have adverse effects such as gas release, so it should be careful not to be exposed to the connection parts and side walls. In addition, fluorine-based gas or argon (A
r) Etch back by dry etching technique using a series of gases.

Then, similarly to the case of the lower silicon oxide film 321, an upper silicon oxide film 323 is deposited by the CVD method.

[rV] step.

Contact holes 6a are selectively opened in the interlayer insulating film 5 by photolithography and etching techniques, corresponding to the connection portions 6 for electrically connecting with the first layer aluminum wiring 4.

That is, the portion other than the connecting portion 6 is covered with a resist pattern 324 by photolithography, and the resist pattern 3 is
24 as an etching mask, for example, by a taper etching technique that combines wet etching with a fluorine-based solution, CHF, and reactive ion etching whose main ingredients are 0□.
Interlayer insulating film 5 is selectively removed to open contact hole 6a.

Note that in this case, the resist pattern 32 used for the mask
4. In addition, reaction products generated during etching are removed by oxygen (0□) plasma, wet chemical treatment, etc. after the etching holes are formed.

[V) Process.

The above-mentioned connection part 6. That is, during the process of forming the contact hole 6a, the corresponding outermost surface portion of the first layer aluminum wiring 4 is exposed to plasma of fluorine gas such as CHF or oxygen (0,) gas. As a result, an aluminum deterioration layer (fluoride layer, oxide layer, etc.) portion 201 with a thickness of approximately 100 mm is formed on the outermost surface of the thin insulating film (portion 201). In order to remove the contact resistance and obtain stable contact resistance, sputter etching using argon (Ar) ions 202 is performed before forming the second layer aluminum wiring 7.

[V1] Process.

Aluminum deterioration layer portion 20 in the first layer aluminum wiring 4
After removing the first layer aluminum wiring 4 by etching, the second layer aluminum wiring 7 is successively deposited in vacuum on the interlayer insulating film 5 including the contact hole 6a by sputtering, and the first layer aluminum wiring 4 is As in the case above, photolithography and etching techniques are used to selectively pattern the wiring as desired.

In this case, the second layer aluminum wiring 7 is as follows:
Aluminum alloy films such as AJ2-St, Aff-3L-Cu, and Aj2-Cu are used.

Furthermore, in order to make electrical contact between the first and second layer aluminum wirings 4 and 7 at this connecting portion 6, after the selective formation of the second layer aluminum wiring 7, a temperature of about 400 to 450°C is applied. Apply heat treatment at temperature.

[■] Process.

Finally, in order to protect these element parts and each wiring part from moisture entering from the outside, a layer is formed on the interlayer insulating film 5 including the second layer aluminum wiring 7 by a CVD method. A protective insulating film 8 such as a silicon oxide film or a silicon nitride film is deposited.

[Problem to be solved by the invention]

The multilayer wiring structure in a conventional semiconductor device is configured as described above, and each first... With the miniaturization of the second aluminum wiring layers 4 and 7, the inner diameter of the contact hole 6a that forms the mutual connection 6 is also reduced. 6, various undesirable problems arise in terms of the stability and reliability of electrical contact at the connection portion 6.

That is, as mentioned above, in the case of the conventional method, the second
Before forming the layered aluminum wiring 7, sputter etching treatment using argon (Ar) ions 202 is performed, and this pretreatment is performed to form the connection portion 6 as shown in FIG. By sputtering and etching the aluminum deterioration layer (fluoride layer, oxide layer, etc.) portion 201 formed on the surface of the first layer aluminum wiring 4 in the contact hole 6a, this is removed from the aluminum. The fluoride, oxide, and particles 203 are scattered to the outside of the connection portion 6 and removed, thereby cleaning the corresponding surface portion of the first layer aluminum wiring 4.

However, at this time, what is sputter-etched by the argon (Ar) ions 202 is not only the original aluminum deterioration layer portion 201, but also the portion shown in FIG.
As shown in b), the part of the interlayer insulating film 5 exposed on the surface side is also sputter etched, and therefore, during the etching process, the interlayer insulating film 5 is not formed. A part of the silicon oxide film is decomposed to generate oxygen (O2) 204, which reacts with the first layer aluminum wiring 4 to form aluminum oxide 205 on the corresponding surface area, or to form an insulator without being decomposed. This caused a phenomenon in which particles of silicon oxide 206 were attached to the corresponding surface portion of the first layer aluminum wiring 4.

Therefore, even if the second layer aluminum wiring 7 is selectively formed continuously in vacuum in this state, as shown in FIG. Aluminum oxide 205 generated during sputtering and etching at the interface between the first layer aluminum wiring 4 and the second layer aluminum wiring 7
．． and silicon oxide 206 particles are present, and in the heat treatment at a temperature of about 400 to 450° C. after the formation of the second layer aluminum wiring 7 described in the above flow, the first. The interfacial mixing of the second aluminum wiring layers 4.7 is not sufficiently performed, resulting in an increase in contact resistance at the connection portion 6 and an oven failure.

And also, the second layer of aluminum! ! By heat treatment at a temperature of about 400 to 450°C after the formation of 7,
Even if the initial contact resistance value can be made normal, as mentioned above, the first. Each second aluminum wiring layer 4.
Since the interfacial mixing at 7 is not sufficient, there is a disadvantage that the reliability of the connection portion 6, such as the electro-migration resistance and the stress-migration resistance, is reduced.

Furthermore, in the case of silicon semiconductor substrates and lower layer wiring other than aluminum, natural oxide films and altered films formed on the surface can be relatively easily removed by cleaning with hydrofluoric acid, other suitable acids, or alkaline cleaning. However, in the case of aluminum wiring whose underlying wiring is susceptible to acid and alkali solutions, such acid and alkali cleaning cannot be performed, and the above-mentioned problems become even more serious.

This invention was made to solve these conventional problems, and its purpose is to promote mixing at the connection between the lower layer wiring and the upper layer wiring to achieve stable contact resistance. At the same time, reliability levels such as electro-migration resistance and stress-migration resistance of the connection portion are improved, and a device configuration with high quality and good manufacturing yield can be obtained. An object of the present invention is to provide a semiconductor device of this type, a method for manufacturing the same, and a multilayer wiring structure in a semiconductor device, as well as a method for forming the same.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention includes a conductive sputter etching prevention film such as a metal film, a polycrystalline silicon film, or a metal silicide film, on an interlayer insulating film covering the lower layer aluminum wiring. After forming these layers, contact holes are formed in each of these layers to connect to the aluminum wiring in the lower layer.

That is, the present invention provides a semiconductor device having a multilayer wiring structure in which lower layer wiring and upper layer wiring are insulated from each other by an interlayer insulation film, in which a metal film or a polycrystalline silicon film is provided on the interlayer insulation film covering the lower wiring. Alternatively, as an upper layer wiring formed by forming a conductive sputter etching prevention film such as a metal silicide film, and connected to the lower layer wiring through a contact hole opened in the conductive sputter etching prevention film and an interlayer insulating film. This is a semiconductor device characterized in that a conductive film is formed therein, and an upper layer wiring is formed of these conductive films and a conductive sputter etching prevention film.

The present invention also provides a method for manufacturing a semiconductor device having a multilayer wiring structure in which lower and upper wiring layers are insulated from each other by an interlayer insulation film, including a step of forming an interlayer insulation film on the lower wiring. , a step of forming a conductive sputter etching prevention film such as a metal film, a polycrystalline silicon film, or a metal silicide film on the interlayer insulation film; and a step of forming the lower layer through the conductive sputter etching prevention film and the interlayer insulation film. A step of selectively opening a contact hole that reaches the wiring, a step of removing by sputter etching a degraded layer on the lower layer wiring that was generated when the contact hole was opened in the previous step, and a step of removing the deteriorated layer on the lower wiring layer after the sputter etching. a step of forming a conductive film to become an upper layer wiring on the conductive sputter etching prevention film containing the conductive sputter etching prevention film, and connecting the conductive film to the lower layer wiring through a contact hole; This method of manufacturing a semiconductor device is characterized in that it includes a step of simultaneously patterning and forming the upper layer wiring to selectively form the upper layer wiring.

[For production]

Therefore, in the present invention, in a semiconductor device having a multilayer wiring structure in which lower layer wiring and upper layer wiring are insulated from each other by an interlayer insulation film, on the interlayer insulation film covering the lower layer wiring,
A conductive sputter-etching prevention film such as a metal film, polycrystalline silicon film, or metal silicide film is formed, and connection is made to the lower layer wiring through a contact hole opened in the conductive sputter-etching prevention film and the interlayer insulating film. After forming a conductive film as an upper layer wiring,
Since the upper layer wiring is formed using these conductive films and the conductive sputter etching prevention film, when removing the degraded layer on the surface of the lower layer wiring exposed in the contact hole at the connection part by sputter etching, the interlayer Even if the insulating film is silicon oxide, the generation of oxygen due to its decomposition is reduced, and the formation of insulating film oxide on the surface of the underlying wiring can be minimized. It is also possible to effectively prevent the adhesion of particles.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to FIGS. 1 to 4.

FIG. 1 is a sectional view schematically showing the general structure of a DRAM device having an aluminum multilayer wiring structure to which an embodiment of the present invention is applied.

Also in the configuration of the embodiment shown in FIG.
2 is a silicon semiconductor substrate, and 2 is a DRAM element (stacked) formed on the main surface of the silicon semiconductor substrate 1.
3 is a base insulating film deposited to cover the DRAM element (stack cell) 2. Further, 4 is a first layer aluminum wiring selectively formed on the base insulating film 3, 5 is an interlayer insulating film deposited on the base insulating film 3 including the first layer aluminum wiring 4, and 6 is the above-mentioned This is a connection portion including a contact hole 6a formed in the interlayer insulating film 5 to connect the first layer aluminum wiring 4 and the upper second layer aluminum wiring. Further, 101 is aluminum as a sputter etching prevention film deposited on the interlayer insulating film 5 to prevent sputter etching on the interlayer insulating film 5;
Or an aluminum alloy film. Furthermore, 7 is a second layer aluminum wiring selectively formed on the aluminum or aluminum alloy film 101 as the sputter etching prevention film;
8 is the second layer aluminum wiring 7 in order to protect these element parts and each wiring part from intrusion of moisture etc. from the outside.
．． and a protective insulating film deposited on the interlayer insulating film 5 including the aluminum or aluminum alloy film 101.

Next, the manufacturing flow of the semiconductor device according to the embodiment shown in the structure shown in FIG. 1 will be described, focusing in particular on the method of forming the connecting portions between the interconnections in each layer.

In this case, the multilayer wiring structure is an "aluminum two-layer wiring structure" in which both the first layer and the second layer wiring are mainly aluminum wiring, as shown in Fig. 1 above. To say/do.

FIGS. 2 [I] to [■] are sectional views sequentially schematically showing the formation flow of the aluminum two-layer wiring structure as described above.

[I] to [III] steps.

All of these steps are the same as the corresponding steps in the conventional example.

That is, first, on the main surface of the silicon semiconductor substrate l, an element isolation oxide film 301. ) Transfer gate electrode 302. Impurity diffusion layer 303. Word line 304° storage node 305. Capacitor insulating film 306. A DRAM element (stacked cell) 2 consisting of a cell plate 307 and a cell plate 307 is formed.

Next, a base insulating film 3 is deposited on the entire surface of the silicon semiconductor substrate l on which the DRAM element (stacked cell) 2 is formed, and then contact holes are selectively formed in required portions by photolithography and etching techniques. 308 and the base insulating film 3 including the contact hole 308 part.
A first layer aluminum wiring 4 is selectively formed thereon. The first layer aluminum wiring 4 is made of titanium nitride (TiN).
, a barrier metal film 310 such as titanium/tungsten (Tie), and an aluminum alloy film 311 such as Aj2-3i, AJ2-3L-Cu are used, and each of these layers 310, 311 is , is normally deposited by sputtering and selectively patterned as the first layer aluminum wiring 4 by photolithography and etching.

Furthermore, an interlayer insulating film 5 is deposited on the entire surface of the base insulating film 3 including the first layer aluminum wiring 4. The interlayer insulating film 5
For example, a lower silicon oxide film 321 deposited by the CVD method, an intermediate inorganic coating insulating film 322 deposited by coating, and an upper silicon oxide film 323 deposited by the CVD method. An insulating film structure is used in which these are sequentially combined.

The lower silicon oxide film 321 is usually made of silane (Si)l-) gas and oxygen (0□) gas.

Alternatively, using nitrous oxide (N,0) gas, 300
It is deposited by a CVD method using heat or plasma at a deposition temperature of about 450°C. In this case, an organic silane material such as TEOS, which has a good step coverage, may be used.

The inorganic coating insulating film 322 of the intermediate layer is used for planarization, and the inorganic coating insulating film 322 is generally composed mainly of silanol (Si (OH) 4) or the like. After spin-coating this, 400-450℃
By baking at a certain temperature to form a silicon oxide film, the surface of the silicon oxide film 321 is flattened.

However, this inorganic coating insulating film 322 has relatively high hygroscopicity, and if it is exposed to the connection parts and side walls, which will be described later, it will have an adverse effect such as gas release, so it should not be exposed to the connection parts and side walls. To avoid this, etching back is performed using a dry etching technique using fluorine-based gas or argon (Ar)-based gas.

Then, similarly to the case of the lower silicon oxide film 321, an upper silicon oxide film 323 is deposited by the CVD method.

[1”/] process.

Next, on the entire surface of the interlayer insulating film 5, a conductive sputter etching prevention film of aluminum or An aluminum alloy film 101 is deposited.

[V] Process.

A contact hole is formed in the aluminum or aluminum alloy film 101 and the interlayer insulating film 5 at a portion corresponding to the connection portion 6 that makes electrical connection with the first layer aluminum wiring 4 by photolithography or etching technology. 6a is selectively opened.

That is, the portion other than the connecting portion 6 is covered with a resist pattern 324 by photolithography, and the resist pattern 3 is
24 as an etching mask, for example, by a taper etching technique that combines wet etching with a fluorine-based solution, CHF, and reactive ion etching whose main ingredients are 0□.
The aluminum or aluminum alloy film 101 and the interlayer insulating film 5 are selectively removed to form a contact hole 6 common to both.
The hole a is opened.

Note that in this case, the resist pattern 32 used for the mask
4. In addition, reaction products generated during etching are removed by oxygen (0□) plasma, wet chemical treatment, etc. after the etching holes are formed.

[VT] Process.

The above-mentioned connection part 6. That is, during the process of forming the contact hole 6a, the corresponding outermost surface portion of the first layer aluminum wiring 4 is exposed to fluorine gas such as CHF, or oxygen (0□) gas. When exposed to plasma, an aluminum deterioration layer (fluoride layer, oxide layer, etc.) portion 201 with a thickness of approximately 100 mm is formed on the outermost surface. In order to remove and obtain stable contact resistance, sputter etching using argon (Ar) ions 202 is performed before forming the second layer aluminum wiring 7.

During this sputter etching, as shown in FIG. 3, the aluminum or aluminum alloy film 101 deposited in the (rv) step as a conductive sputter etching prevention film is formed. Therefore, the interlayer insulating film 5 is hardly sputter etched, and an effectively mixed connection interface 207 can be formed.On the other hand, the aluminum or aluminum alloy film 101 is not sputter etched Even if the particles are attached to the surface of the first layer aluminum wiring 4, there is no risk of causing any trouble because they are conductive.

[■] Process.

Aluminum deterioration layer portion 20 in the first layer aluminum wiring 4
After removing the contact hole 308.1 by etching, the contact hole 308.1 is continuously etched in a vacuum. Aluminum or aluminum alloy film 10
A second layer aluminum wiring 7 is deposited on the interlayer insulating film 5 including the first layer 1 by a sputtering method, and as in the case of the first layer aluminum wiring 4, a desired shape is formed by photolithography and etching. Selectively pattern as wiring.

In this case, the second layer aluminum wiring 7 is as follows:
Aluminum alloy films such as Al2-3i, Al2-3t-Cu, and Aρ-Cu are used.

Furthermore, in order to make electrical contact between the first and second layer aluminum wirings 4 and 7 at this connecting portion 6, after the selective formation of the second layer aluminum wiring 7, a temperature of about 400 to 450°C is applied. Apply heat treatment at temperature.

[■] Process.

Finally, in order to protect these element parts and each wiring part from moisture entering from the outside, a layer is formed on the interlayer insulating film 5 including the second layer aluminum wiring 7 by a CVD method. A protective insulating film 8 such as a silicon oxide film or a silicon nitride film is deposited.

In the above embodiment, aluminum, aluminum,
Alternatively, although the aluminum alloy film 101 is used, other metal films such as a titanium film, a polycrystalline silicon film, or a tungsten silicide film may also be used.
Similar actions and effects can be obtained by optionally using a metal silicide film or the like.

In addition, although the above embodiment describes a two-layer aluminum wiring structure, it can also be applied to a multilayer wiring structure of three or more layers.
As shown in FIG. 4, similar actions and effects can be obtained even when a barrier metal is used as an underlying film for two or more layers of wiring. Thus, in the configuration of the embodiment shown in FIG.
1 is aluminum or aluminum alloy film as above, 40
2 is a titanium nitride film, 403 is a titanium film, and 404 is an intermetallic compound (TiAβ, ) layer.

Further, in the above embodiments, the case where the present invention is applied to a semiconductor device in which a DRAM element is formed on a semiconductor substrate has been described, but it goes without saying that the present invention can be easily applied to a semiconductor device having other multilayer wiring structures.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a semiconductor device having a multilayer wiring structure in which lower layer wiring and upper layer wiring are insulated from each other by an interlayer insulation film, a metal layer is placed on the interlayer insulation film covering the lower layer wiring. A conductive sputter etching prevention film such as a polycrystalline silicon film, a metal silicide film, etc. is formed, and the lower wiring is connected to the conductive sputter etching prevention film and a contact hole formed in the interlayer insulating film. After forming a conductive film as an upper layer wiring to be connected, the upper wiring is formed using these conductive films and a conductive sputter etching prevention film. When removing the deteriorated layer on the wiring surface by sputter etching, the interlayer insulating film is hardly etched (for this reason, even if the interlayer insulating film is made of silicon oxide, the decomposition of The generation of oxygen is reduced, the formation of insulating film oxide on the surface of the lower wiring can be suppressed to a minimum, and at the same time, the adhesion of insulating film oxide particles to the surface of the lower wiring can be effectively prevented. As a result, the connection interface between the lower layer wiring and the upper layer wiring is sufficiently mixed, and not only stable contact resistance can be obtained, but also reliability levels such as electro-migration resistance and stress-migration resistance at the connection part can be improved. It has excellent features such as being able to improve performance and obtain high-quality device configurations at a high yield.

[Brief explanation of drawings]

FIG. 1 is a sectional view schematically showing the general structure of a DRAM device having an aluminum multilayer wiring structure to which an embodiment of the present invention is applied, and FIG. 2 [I] to [■] are aluminum 2 Each figure is a cross-sectional view schematically showing the outline of the main manufacturing process of the layered wiring structure, and FIG. FIG. 4 is a cross-sectional view schematically showing the general structure of a DRAM device having an aluminum multilayer wiring structure to which the same and other embodiments are applied. In addition, Figure 5 shows a DR with a conventional aluminum multilayer wiring structure.
1 is a cross-sectional view schematically showing the general configuration of an AM device,
Figure 6 [I] to [■] are aluminum 2 in the same device.
Each of the diagrams schematically shows an overview of the main manufacturing processes of the layered wiring structure, and each of FIGS. 7 and 8 is an enlarged sectional view of the main part to explain the problems in the two-layer aluminum wiring structure. It is. 1... Silicon semiconductor substrate, 2... DRAM element (stack cell), 3...
- Base insulating film, 4... First layer aluminum wiring, 5... Interlayer insulating film, 6... Connection part, 6a...
...Contact hole, 7...Second layer aluminum wiring, 8...Protective insulating film, 101...Aluminum or aluminum alloy film (conductive sputter etching prevention film), 201... Aluminum altered layer portion, 202...Argon (Ar) ion, 203...
-Sputtered aluminum fluoride. Oxide/particles, Oxygen generated by sputtering of interlayer insulating film (
0□), ...Aluminum oxide, ...Silicon oxide/particles generated by sputtering of interlayer insulating film, ...Interface between upper layer aluminum wiring and lower layer aluminum wiring, ...Element Isolation oxide film, ...Transfer gate electrode, ...Impurity diffusion layer, ...Word line, 305...Storage node, ...
...Capacitor insulating film, ...Cell plate, ...Contact hole, ...Barrier metal film, ...Aluminum alloy film, ...Silicon oxide film, ...Inorganic Coated insulating film, ... silicon oxide film, ... resist pattern, ... aluminum or aluminum alloy film (conductive sputter etching prevention film) ... titanium nitride film, ... titanium Film, ... intermetallic compound (Ti Ac1) layer.

Claims (2)

[Claims] (1) In a semiconductor device having a multilayer wiring structure in which lower and upper wiring layers are insulated from each other by an interlayer insulating film, a metal film of a required thickness, polycrystalline silicon, etc. A conductive sputter etching prevention film such as a film or a metal silicide film is formed, and the upper layer wiring is connected to the lower layer wiring through the contact hole opened in the conductive sputter etching prevention film and the interlayer insulating film. What is claimed is: 1. A semiconductor device comprising: a conductive film formed thereon; and an upper layer wiring formed from the conductive film and a conductive sputter etching prevention film. (2) A method for manufacturing a semiconductor device having a multilayer wiring structure in which lower and upper wiring layers are insulated from each other by an interlayer insulating film, comprising: forming an interlayer insulating film over the lower wiring; A step of forming a conductive sputter etching prevention film such as a metal film, a polycrystalline silicon film, or a metal silicide film on the insulating film, and reaching the lower wiring through the conductive sputter etching prevention film and the interlayer insulating film. a step of selectively opening a contact hole; a step of removing, by sputter etching, a degraded layer on the lower wiring that was generated when the contact hole was opened in the previous step; and after the sputter etching, the conductive layer including the contact hole is removed. forming a conductive film to become an upper layer wiring on the conductive sputter etching prevention film, connecting the conductive film to the lower layer wiring through a contact hole, and patterning the conductive film and the conductive sputter etching prevention film at the same time. and selectively forming the upper layer wiring.