JP3029507B2 - Wiring layer connection structure of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring layer connection structure of a semiconductor device for electrically connecting an impurity region formed on a main surface of a semiconductor substrate to an upper wiring layer.

[0002]

2. Description of the Related Art In a semiconductor device, a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, an aluminum film, an aluminum alloy film, etc. are used to electrically connect elements formed on a semiconductor substrate. Are used.

[0003] Electrical connection between elements is performed by selectively opening an insulating film formed on a semiconductor substrate and opening the opening (connection hole).
Is filled with the various wirings described above.

[0004] A wiring layer connection structure of a conventional semiconductor device will be described with reference to FIG. FIG. 13 shows a conventional DRAM.
(Dynamic Random Access Me
FIG. 2 is a sectional structural view of FIG.

An N-type well 7a and a P-type well 7b are formed on the main surface of the silicon semiconductor substrate 1. A DRAM element (stack cell) 2 is formed on the P-type well 7b. The MOS transistor 5 having the P-type impurity regions 6a and 6b is formed on the N-type well 7a. First insulating film 3 is formed to cover DRAM element 2 and MOS transistor 5. In the first insulating film 3, through holes (connection holes) exposing the P-type impurity regions 6a and 6b are formed.

A first wiring 8 having a two-layer structure of a barrier metal film 9 and a conductor film 11 is formed on the first insulating film 3. The first wiring 8 is electrically connected to P-type impurity regions 6a and 6b via through holes 4a and 4b, respectively.

The first insulating film 3 covers the first wiring 8.
An interlayer insulating film 12 is formed thereon. Interlayer insulating film 1
2, a through hole 19 for exposing the first wiring 8 is formed.

A second wiring 13 is formed on interlayer insulating film 12. The second wiring 13 is electrically connected to the first wiring 8 via a through hole 19. The protective insulating film 1 is formed on the interlayer insulating film 12 so as to cover the second wiring 13.
4 are formed. The protective insulating film 14 protects the semiconductor device from moisture or the like entering from the outside.

Next, a method of manufacturing the semiconductor device shown in FIG. 13 will be described. As shown in FIG. 14, the silicon semiconductor substrate 1
Next, an N-type well 7a and a P-type well 7b are formed. The gate electrode 304 and the N-type impurity region 30 are formed on the P-type well 7b.
5a, 305b, bit line 307, storage node 308,
The DRAM device 2 including the capacitor insulating film 309 and the cell plate 310 is formed. On the other hand, the MOS transistor 5 including the P-type impurity regions 6a and 6b is formed on the N-type well 7a.

As shown in FIG. 15, a first insulating film 3 is formed so as to cover DRAM element 2 and MOS transistor 5. Then, through holes 4 reaching P-type impurity regions 6a and 6b using photolithography technology and etching technology.
a and 4b are formed.

As shown in FIG. 16, a barrier metal film 9 and a conductor film 11 are laminated on the first insulating film 3.

The barrier metal film 9 has a P-type impurity region 6a,
6b for stable contact. The barrier metal film 9 is deposited using a sputtering method, and examples of the type of the barrier metal film 9 include titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), and tungsten (W).

The conductor film 11 has a relatively low resistance and excellent step coverage. A film of tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), or the like is formed by a CVD method. It is formed by using.

For example, tungsten hexafluoride (W
F ₆ ) and hydrogen (H ₂ ) at a film formation temperature of 400 to 50
Under a condition of 0 ° C. and a film formation pressure of 5 to 50 Torr, a reduced pressure C
Since the tungsten film 11 formed by the VD method has good step coverage, the aspect ratio (through-hole depth / through-hole diameter) of about 2 to 3
Even if the through holes 4a and 4b have a half-micron level, only the conductor film 11 is deposited,
a, 4b can be embedded with the conductive film 11.

As shown in FIG. 17, a photoresist 15 is formed on the conductor film 11, and the conductor film 11 and the barrier metal film 9 are selectively etched by using a photolithography technique and an etching technique to form a first wiring. 8 is formed. Then, as shown in FIG. 18, the photoresist 15 is removed.

As shown in FIG. 19, an interlayer insulating film 12 is formed so as to cover the first wiring 8. As the interlayer insulating film 12, for example, an insulating film having a structure in which a silicon oxide film 16 formed by a CVD method, an inorganic coating insulating film 17, and a silicon oxide film 18 formed by a CVD method are used is used.

The silicon oxide film 16 is usually made of silane (S
300-450 ° C. using a mixed gas of iH ₄ ) gas and oxygen (O ₂ ) gas or nitrous oxide (N ₂ O) gas.
The film is formed by a CVD method using heat or plasma at the film forming temperature.

In recent years, TEOS (Tetra-E) has a feature that step coverage is good.
A silicon oxide film is formed using an organic silane-based material such as (thyl-Ortho-Silicate).

The inorganic coating insulating film 17 is used for planarization, and the inorganic coating insulating film 17 is generally composed mainly of silanol (Si (OH) ₄ ) or the like.

The inorganic coating insulating film 17 is formed by spin-coating a material containing silanol or the like as a main component on the silicon oxide film 16 and then performing a baking process at a temperature of 400 to 450 ° C. to form a silicon oxide film. The surface of the silicon oxide film 16 is flattened.

Since the inorganic coating insulating film 17 has a high hygroscopicity, forming a side wall of a through-hole adversely affects gas emission and the like. For this reason, the inorganic coating insulating film 17 is etched back using a dry etching technique using a fluorine-based gas or an argon gas so as not to form the side wall of the through hole.

A silicon oxide film 18 is formed so as to cover the inorganic insulating film 17 and the silicon oxide film 16. Silicon oxide film 18 is formed in the same manner as silicon oxide film 16.

As shown in FIG. 20, the interlayer insulating film 12 is selectively removed by etching to form a through hole 19 exposing the first wiring 8. The through hole 19 is formed by first performing a taper etching method (wet etching with a hydrofluoric acid solution) halfway, and then performing a reactive ion etching using a mixed gas mainly composed of CHF ₃ and O ₂ gas. Form.

During the formation of the through hole 19, the first wiring 8
A denatured layer (fluoride or oxide layer) is formed on the exposed surface. Since these become obstacles for obtaining a stable contact resistance, the affected layer is first removed by sputter etching using Ar ions, and as shown in FIG. Is formed using a sputtering method. Then, the underlying film 20 and the aluminum alloy film 21 are selectively removed by etching using a photomechanical technique and an etching technique to form the second wiring 13.

The underlying film 20 enhances resistance to “stress migration” in which the second wiring 13 is disconnected due to a film stress of a protective insulating film or the like formed on the second wiring 13.

The adhesion at the connection interface between the first wiring 8 and the second wiring 13 in the through hole 19 is improved, and the reliability level such as “electromigration” and “stress migration” is improved. It has the action of:

The underlayer film 20 is usually made of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten (W) or the like, and the aluminum alloy film 21 is made of Al-Si, Al-Si-Cu,
Al-Cu or the like is used. 1st through hole 19
400-450 after forming the second wiring 13 in order to make electrical contact between the second wiring 8 and the second wiring 13.
Heat treatment is performed at a temperature of about ° C.

As shown in FIG.
In order to protect the S transistor and the wiring from moisture or the like that enters from the outside, a protective insulating film 14 such as a silicon oxide film or a silicon nitride film is formed on the second wiring 13 by using the CVD method.

[0029]

As shown in FIG. 13, in a conventional semiconductor device, a first wiring 8 and a P-type impurity region 6 are formed.
Electrical connection between a and 6b is performed by forming a barrier metal film 9 in the through holes 4a and 4b and filling the through holes 4a and 4b with a conductor film 11 made of a refractory metal such as tungsten or titanium. I have.

As shown in FIG. 23, in the case of the structure in which the inside of the through hole 4a is embedded with the conductor film 11 made of a high melting point metal (FIG. 23B), in the case of the structure in which the through hole 4a is not embedded with the conductor film 11 (see FIG. 23). 23 (a)), although the contact resistance in the through hole 4a can be reduced, the film stress of the conductive film 11 is concentrated on the P-type impurity region 6a, so that the P-type impurity region 6a and the silicon semiconductor substrate 1 are formed. However, there is a problem that the junction leak current tends to increase at the PN junction.

The present invention has been made to solve such a conventional problem. An object of the present invention is to provide a wiring layer connection structure of a semiconductor device which can reduce a junction leak current.

[0032]

SUMMARY OF THE INVENTION The present invention provides a semiconductor substrate of a first conductivity type having a main surface, an impurity region of a second conductivity type formed on the main surface, and an impurity region formed on the main surface. Wiring of a semiconductor device, comprising: an insulating layer having a connection hole for exposing a wiring; and a wiring layer formed on the insulating layer and electrically connected to the impurity region through the connection hole and containing a refractory metal. In the layer connection structure, the wiring layer
A barrier metal film is formed so as to be in contact with the impurity region inside the connection hole, and the stress buffer film is formed on the barrier metal film. is, KoToru of the wiring layer in the connection hole is a buffer the stress applied to the non <br/> pure product area, constituting the wiring layer
Point metal film is formed on the stress relieving layer is characterized and Turkey to fill the connection hole.

[0033]

In the semiconductor device according to the present invention, the stress buffer film for buffering the stress applied to the impurity region by the wiring layer containing the high melting point metal in the connection hole is formed in the connection hole. The film stress applied to the region can be reduced, and the junction leak current can be reduced.

[0034]

FIG. 1 is a sectional structural view of a first embodiment of a wiring layer connection structure of a semiconductor device according to the present invention. In the silicon semiconductor substrate 1, an N-type well 7a
A mold well 7b is formed.

The DRAM element 2 is formed in the P-type well 7b. On the other hand, in the N-type well 7a, the MOS transistor 5 in which P-type impurity regions 6a and 6b are formed with a space therebetween is formed.

A first insulating film 3 is formed so as to cover DRAM element 2 and MOS transistor 5. First
The first wiring 8 is formed on the insulating film 3. First
The wiring 8 has a three-layer structure of a barrier metal film 9, a stress buffering film 10, and a conductor film 11. In the first insulating film 3, through holes 4a and 4 exposing the P-type impurity regions 6a and 6b are formed.
The first wiring film 8 is buried in the through holes 4a and 4b. Since stress buffering film 10 (for example, a tungsten silicide film) is formed in through holes 4a and 4b, P-type impurity regions 6a and 6b are formed.
Film stress of the conductor film 11 applied to the substrate can be reduced, and the junction leakage current can be reduced.

The interlayer insulating film 12 covers the first wiring 8.
Are formed. The second wiring 1 is formed on the interlayer insulating film 12.
3 are formed. The first wiring 8 is formed on the interlayer insulating film 12.
Through holes 19 are formed to expose
The wiring 13 is electrically connected to the first wiring 8 through the through hole 19. Then, a protective insulating film 14 is formed so as to cover the second wiring 13.

Next, the manufacturing method of the first embodiment of the wiring layer connection structure of the semiconductor device according to the present invention will be described below. FIG.
As shown in FIG.
a, a P-type well 7b is formed, and an element isolation insulating film 301 is formed. Then, the N-type impurity region 3 is formed in the P-type well 7b.
05a, bit line 307 electrically connected to N-type impurity region 305a, N-type impurity region 305b, and storage node 3 electrically connected to N-type impurity region 305b.
08, the capacitor insulating film 309, and the cell plate 31
0 and the DRAM element 2 including the gate electrode 304 were formed. On the other hand, the P-type impurity region 6 is provided in the N-type well 7a.
A MOS transistor 5 having a and 6b was formed.

As shown in FIG. 3, a first insulating film 3 was formed so as to cover the DRAM element 2 and the MOS transistor 5. Then, the first insulating film 3 is selectively removed by etching using photolithography technology and etching technology, and the through holes 4a, 4b reaching the P-type impurity regions 6a, 6b.
Was formed.

As shown in FIG. 4, P
A barrier metal film 9 for making stable contact with the mold impurity regions 6a and 6b was deposited by using a sputtering method. Types of the barrier metal film 9 include titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), and tungsten (W). Next, a stress buffering film 10 (for example, a tungsten silicide film (WSi ₂ )) was formed on the barrier metal film 9 by using a CVD method.

The tungsten silicide film is, for example,
Tungsten hexafluoride (WF ₆ ) and silane (SiH ₄ )
At a film formation temperature of 350 to 450 ° C. and a film formation pressure of 1 to
It can be formed by the low pressure CVD method under the condition of 10 Torr, and the film thickness is desirably about 200 to 1000 °.

Next, a conductor film 11 having a relatively low resistance and excellent step coverage was formed on the stress buffering film 10 by the CVD method. Examples of the type of the conductive film 11 include tungsten (W), titanium (Ti), molybdenum (Mo), and tantalum (Ta).

For example, a tungsten film is formed by low-pressure CVD using tungsten hexafluoride (WF ₆ ) and hydrogen (H ₂ ) at a film forming temperature of 400 to 500 ° C. and a film forming pressure of 5 to 50 Torr. can do. Since the tungsten film formed under these conditions has good step coverage, the through holes 4a and 4b having an aspect ratio (through hole depth / through hole diameter) of about 2 to 3 and a half-micron level are used. However, the through holes 4a and 4b can be filled with the conductor film 11 only by depositing the conductor film 11.

As shown in FIG. 5, a photoresist 15 was formed on the conductor film 11. Then, the conductive film 11, the stress buffering film 10, and the barrier metal film 9 were selectively removed by etching using a photomechanical technique and an etching technique to form a first wiring 8. Then, as shown in FIG. 6, the photoresist 15 was removed.

As shown in FIG. 7, an interlayer insulating film 12 was formed so as to cover the first wiring 8. As the interlayer insulating film 12, for example, a structure having a combination of a silicon oxide film 16 formed by a CVD method, an inorganic coating insulating film 17, and a silicon oxide film 18 formed by a CVD method was used.

The silicon oxide film 16 is usually made of silane (S
300-450 ° C. using a mixed gas of iH ₄ ) gas and oxygen (O ₂ ) gas or nitrous oxide (N ₂ O) gas.
The film is formed by a CVD method using heat or plasma at the film forming temperature.

Further, recently, TEOS (Tetra-E) having a feature that step coverage is good is provided.
A silicon oxide film is formed using an organic silane-based material such as (thyl-Ortho-Silicate).

The inorganic coating insulating film 17 is formed for flattening, and generally contains silanol (Si (OH) ₄ ) as a main component.

After spin-coating a material mainly composed of silanol or the like on the silicon oxide film 16, baking is performed at a temperature of 400 to 450 ° C. to form a silicon oxide film, thereby flattening the silicon oxide film 16. I do.

Since the inorganic coating insulating film 17 has a high hygroscopicity, if the inorganic coating insulating film 17 is used as the side wall of the through hole, adverse effects such as gas release will occur. For this reason, an etch-back process is performed using a dry etching technique using a fluorine-based gas or an argon gas so that the inorganic coating insulating film 17 does not form the side wall of the through hole.

A silicon oxide film 18 was formed on the silicon oxide film 16 and the inorganic coating insulating film 17. The silicon oxide film 18 was formed in the same manner as the silicon oxide film 16.

As shown in FIG. 8, the interlayer insulating film 12 was selectively etched away to form a through hole 19 exposing the first wiring 8. In the through hole 19, first, the interlayer insulating film 12 is partially removed by etching using a taper etching method (wet etching using a hydrofluoric acid solution), and the remainder is formed using a mixed gas mainly composed of CHF ₃ and O ₂ gas. It was formed by removing using reactive ion etching. During the formation of the through hole 19, the first
An altered layer (fluoride or oxide layer) was inevitably formed on the surface of the wiring 8. In order to obtain a stable contact resistance, the affected layer is first removed by sputter etching using Ar ions, and then the underlayer film 20 and the aluminum alloy film 21 are continuously formed in a vacuum as shown in FIG. Formed by using Then, the aluminum alloy film 21 and the underlying film 20 are formed by using photolithography technology and etching technology.
Was selectively removed by etching to form a second wiring 13.

The underlying film 20 enhances resistance to “stress migration” in which the second wiring is disconnected due to a film stress of a protective insulating film or the like formed on the second wiring 13.

The adhesion at the connection interface between the first wiring 8 and the second wiring 13 in the through hole 19 is improved, and the reliability level such as “electromigration” or “stress migration” is improved. It has the action of:

The underlayer film 20 is usually made of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), or the like. Further, as the aluminum alloy film 21, Al-Si, Al-Si-
Cu, Al-Cu or the like is used.

In order to make electrical contact between the first wiring 8 and the second wiring 13 in the through hole 19, a heat treatment is performed at a temperature of about 400 to 450 ° C. after forming the second wiring 13. Was.

As shown in FIG.
In order to protect the S transistor and the wiring from moisture or the like that enters from the outside, a protective insulating film 14 such as a silicon oxide film or a silicon nitride film was formed on the second wiring 13 using a CVD method.

In the first embodiment, tungsten silicide is used as the stress buffering film 10. However, the present invention is not limited to this.
Silicide film, for example, titanium silicide (TiSi
₂ ), molybdenum silicide (MoSi ₂ ) or tantalum silicide (TaSi ₂ ).

The stress buffering film 10 may be a compound film of the conductor film 11, titanium nitride (TiN), molybdenum nitride (MoN), or tantalum nitride (TaN).

The stress buffer film 10 may be made of polycrystalline silicon, amorphous silicon, or germanium (Ge).

In the first embodiment, the case where the stress buffer film 10 and the conductor film 11 are made of different materials has been described. However, the same material may be used as long as the film stress can be reduced.

(Example 1 ) FIG. 11 is a sectional structural view of Example 1 of a wiring layer connection structure of a semiconductor device according to the present invention. The same components as those in the first embodiment shown in FIG. The first wiring 8 includes a barrier metal film 9 and a conductor film 1.
1 has a two-layer structure. The through holes 4a and 4b are shown in FIG.
Is not buried in the conductive film 11 unlike the first embodiment shown in FIG.
This space is filled with a stress buffer film 22 made of an insulating material. As the material of the stress buffering film 22, polyimide resin, silicone resin, silanol (Si (O
H) There is a coating insulating film mainly composed of ₄ ). Reference example
The structure shown in No. 1 was manufactured by the following steps.

As shown in FIG. 3, the through holes 4a, 4a
After the formation of b, a barrier metal film 9 and a conductor film 11 made of tungsten were deposited. The thickness of the conductive film 11 was adjusted so that the through holes 4a and 4b were not filled with the conductive film 11. Then, the insides of the through holes 4a and 4b were filled with the stress buffer film 22. Then, the first wiring 8 was formed by using a photolithography technique and an etching technique.

[0064] (Reference Example 2) FIG. 12 is a sectional view of a reference example 2 of the wiring layer connection structure of a semiconductor device in accordance with the present invention. The same components as those in the first embodiment shown in FIG. In the first embodiment, the stress buffering film 10 is also formed on the first insulating film 3, but in the reference example 2 , the stress buffering film 10 is formed only in the through holes 4a and 4b. The structure shown in FIG. 12 was manufactured as follows.

After the structure shown in FIG. 4 is obtained, the entire surface is etched back to form a conductive film 11 on the first insulating film 3.
The stress buffer film 10 and the barrier metal film 9 were removed. As a result, the conductor film 11, the stress buffer film 10, and the barrier metal film 9 remained only in the through holes 4a, 4b. And
The barrier metal film 9 and the conductor film 11 were stacked on the first insulating film 3 and the first wiring 8 was formed by using photolithography and etching.

[0066]

According to the wiring layer connection structure of the semiconductor device according to the present invention, a stress buffer film for buffering the stress applied to the impurity region by the wiring layer containing the high melting point metal in the connection hole is provided in the connection hole. As a result, the film stress applied to the impurity region can be made smaller than in the prior art, and the junction leakage current can be reduced. Therefore, a highly integrated and highly functional semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a first embodiment of a wiring layer connection structure of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a first step of a manufacturing method of a first embodiment of a wiring layer connection structure of a semiconductor device according to the present invention.

FIG. 3 is a sectional view showing a second step of the method of manufacturing the first embodiment of the wiring layer connection structure of the semiconductor device according to the present invention;

FIG. 4 is a sectional view showing a third step of the method of manufacturing the first embodiment of the wiring layer connection structure of the semiconductor device according to the present invention;

FIG. 5 is a sectional view showing a fourth step of the method for manufacturing the wiring layer connection structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view showing a fifth step of the method for manufacturing the wiring layer connection structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a sectional view showing a sixth step of the method of manufacturing the first embodiment of the wiring layer connection structure of the semiconductor device according to the present invention;

FIG. 8 is a sectional view showing a seventh step of the method for manufacturing the wiring layer connection structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a sectional view showing an eighth step of the method for manufacturing the first embodiment of the wiring layer connection structure of the semiconductor device according to the present invention;

FIG. 10 is a sectional view showing a ninth step of the method for manufacturing the wiring layer connection structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a sectional structural view of Reference Example 1 of a wiring layer connection structure of a semiconductor device according to the present invention.

FIG. 12 is a sectional structural view of Reference Example 2 of a wiring layer connection structure of a semiconductor device according to the present invention.

FIG. 13 is a sectional structural view of a wiring layer connection structure of a conventional semiconductor device.

FIG. 14 is a cross-sectional view showing a first step in a conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 15 is a cross-sectional view showing a second step in the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 16 is a cross-sectional view showing a third step of the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 17 is a cross-sectional view showing a fourth step in the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 18 is a cross-sectional view showing a fifth step of the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 19 is a cross-sectional view showing a sixth step of the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 20 is a cross-sectional view showing a seventh step of the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 21 is a cross-sectional view showing an eighth step of the conventional method of manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 22 is a cross-sectional view showing a ninth step of the conventional method for manufacturing a wiring layer connection structure of a semiconductor device.

FIG. 23 is a cross-sectional view illustrating a state where a film stress is applied to an impurity region.

[Explanation of symbols]

 Reference Signs List 1 silicon semiconductor substrate 3 first insulating film 4a, 4b through hole 6a, 6b P-type impurity region 7a N-type well 8 first wiring 9 barrier metal film 10 stress buffering film 11 conductive film

Continuation of the front page (56) References JP-A-64-55861 (JP, A) JP-A-5-114578 (JP, A) JP-A-4-324661 (JP, A) JP-A 64-25410 (JP) JP-A-1-231318 (JP, A) JP-A-2-18950 (JP, A) JP-A-62-135050 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (1)

(57) [Claims] A first conductivity type semiconductor substrate having a main surface; a second conductivity type impurity region formed on the main surface; and a connection hole formed on the main surface to expose the impurity region. A wiring layer formed on the insulating layer and electrically connected to the impurity region through the connection hole, the wiring layer including a refractory metal; In the structure, the wiring layer includes a barrier metal film, a stress buffering film, and a high melting point.
Consists of a metal film, in the interior of the connection hole, the barrier metal film is shaped so as to be in contact with the impurity region
Made is, the stress buffer layer is formed on the barrier metal film, buffers the stress the wiring layer in the connection hole has on the impurity region, the refractory metal film constituting the wiring layer It is formed on the stress relieving layer, and wherein the Turkey to fill the connection hole, the wiring layer connection structure of the semiconductor device.