JPH0661228A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve coating of difference in level of a wiring layer of the lamination structure having a barrier metal in the lower layer while guaranteeing good wiring contact in order to prevent deterioration in performance and reliability of a semiconductor device with reference to the structure and the formation method of a laminated wiring layer containing a barrier metal to be used for a inner wiring of a semiconductor device. CONSTITUTION:This semiconductor device and manufacturing method thereof has a semiconductor device having an inner wiring of the lamination structure where a barrier metal layer 5, a silicon layer 6 and a main conductive layer 7 consisting of aluminum or its alloy or a high melting point metal are by turns laminated from a lower layer and a process for forming the barrier metal layer 5 on a substrate by a sputtering method. Next, this is a manufacturing method of a semiconductor device having a process for forming the silicon layer 6 by an overall chemical gas phase growth means and a process for forming the main conductive layer 7 consisting of aluminum or its alloy or a high melting point metal by a sputtering method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure and a forming method of a laminated wiring layer containing a barrier metal used for internal wiring of a semiconductor device.

In recent years, the degree of integration of LSI has been increasing,
The internal wiring, contact holes for wiring connection, through holes, etc. have been extremely miniaturized. In such a situation, it is of course necessary to reduce the wiring resistance and the contact resistance to prevent the characteristic deterioration of the semiconductor device, but it is necessary to improve the step coverage of the wiring layer to improve the electromigration, the stress migration, and the step. Preventing disconnection due to breakage or the like has become particularly important for maintaining reliability of the semiconductor device.

On the other hand, as the degree of integration is increased and the element is miniaturized as described above, the junction of the impurity diffusion layers constituting the element is also formed shallowly based on the scaling law, so that the substrate silicon is formed. In order to prevent the junction from being destroyed due to the mutual diffusion with, it becomes necessary to use the internal wiring of the laminated structure having the barrier metal layer as the lower layer. Therefore, it is strongly desired to improve the step coverage of the wiring layer having the laminated structure having the barrier metal layer.

[0004]

2. Description of the Related Art Conventionally, a sputtering method has been used as a means for forming a laminated wiring layer used for an internal wiring having a barrier metal layer as a lower layer, and in particular, a main conductive layer made of aluminum (Al) or an alloy thereof is used. A high temperature bias sputtering method has been used to improve the step coverage in the contact holes and through holes.

However, even in this method, in order to obtain excellent step coverage, the surface on which the main conductive layer is deposited is completely made of titanium (Ti), titanium nitride (TiN) or the like, and aluminum or the like is formed on the surface. It is necessary that there is a base film that is easy to form an alloy layer with the material of the main conductive layer and has high surface mobility of the main conductive layer, that is, so-called good wettability. (Monthly Semiconductor
(See World 1989.12, Kiyoshi Watanabe, et al.) However, a barrier metal layer consisting of a Ti layer and a TiN layer, which is generally used, is formed under the laminated wiring by the normal sputtering method as described above. Therefore, in a contact hole, a through hole, or the like, which has poor step coverage and has a small aspect ratio and a large aspect ratio, there is a portion where the barrier metal layer is not formed on the side wall thereof. The step coverage of the main conductive layer such as Al or Al alloy formed by the high temperature bias sputtering is necessarily deteriorated. This state is shown in the schematic sectional view of FIG. 4 showing the conventional problem.

As shown in this figure, a contact hole (through hole) 53 having a large aspect ratio is formed in an insulating film 52 on a conductive substrate 51 made of a semiconductor or lower wiring by a sputtering method. Since the barrier metal layer 54 has poor step coverage, a barrier metal layer lacking portion 55 where the barrier metal layer 54 is not deposited is formed on a part of the side wall. Then, after that, the main conductive layer 56 such as Al or Al alloy generated by the high temperature bias sputtering method is deposited along the barrier metal layer 54 having good wettability so that the contact hole (through hole) 53 is filled. In the main conductive layer 56 thus formed, a void 57 starting from the barrier metal layer lacking portion 55 on the side wall of the contact hole (through hole) 53 is formed, resulting in a contact failure such as an increase in resistance or disconnection. However, there is a problem in that the performance and reliability of the semiconductor device are deteriorated because a reliable contact is not guaranteed.

[0007]

SUMMARY OF THE INVENTION Therefore, the present invention improves the step coverage of a wiring layer having a laminated structure having a barrier metal layer as an underlying layer, guarantees good wiring contact, and deteriorates the performance and reliability of a semiconductor device. The purpose is to prevent.

[0008]

To solve the above problems, a barrier metal layer made of, for example, a laminated film of titanium and titanium nitride, a silicon layer, an aluminum or its alloy, or a main conductive layer made of a refractory metal is formed in order from the lower layer. A semiconductor device according to the present invention, which has internal wiring of a laminated structure formed by stacking layers, or a barrier metal layer, a silicon layer from the bottom,
When forming a laminated wiring layer used for internal wiring of a laminated structure in which main conductive layers made of aluminum or its alloy or refractory metal are sequentially laminated, a sputtering method is used to form a laminated film of titanium and titanium nitride on a substrate. Forming a barrier metal layer, then forming a silicon layer by means of chemical vapor deposition over the entire surface, and then forming a main conductive layer made of aluminum or its alloy or refractory metal by means of sputtering such as high temperature bias sputtering. This is achieved by the method for manufacturing a semiconductor device according to the present invention, which has steps.

[0009]

In other words, the present invention deposits a main conductive layer of Al, an Al alloy containing Al as a main component, a refractory metal or the like on an amorphous or polycrystalline silicon (Si) layer by a high temperature bias sputtering method. When
The surface layer portion of the Si layer is alloyed with the main conductive layer to have very good surface mobility (wettability), and therefore the deposition thickness of the main conductive layer can be made uniform, and
When the layer is formed by chemical vapor deposition (CVD) over the entire surface, the step coverage is extremely good, and the Si film is grown to a substantially uniform thickness on the side wall surface and bottom surface of the contact hole (through hole) with a high aspect ratio. It was based on two facts that could be done.

Specifically, after a barrier metal layer is deposited on the insulating film including the inside of the contact hole (through hole) by a conventional sputtering method, the barrier metal layer is formed on the insulating film including inside of the contact hole (through hole). Full surface CV
An amorphous or polycrystalline Si layer is grown by the D method. As described above, since the vapor phase grown Si layer has an excellent step coverage, the inner surface of the contact hole (through hole), that is, the side wall surface and the bottom surface are all covered with the Si layer having a substantially uniform thickness, and the Si layer is absent. No part is generated.

Next, a main conductive layer of Al, Al alloy, refractory metal or the like is deposited by, for example, a high temperature bias sputtering method excellent in flatness. Here, the main conductive layer having good wettability with respect to Si moves along the surface of the Si layer and is deposited on the side wall surface and the bottom surface of the contact hole (through hole) having the Si layer at a uniform rate. And at this time, as described above, Si
Since the layer is formed on the sidewall surface and the bottom surface of the contact hole (through hole) to have a substantially uniform thickness and there is no lack thereof, the main conductive layer is uniformly deposited from the entire inner surface of the contact hole (through hole). It is uniformly filled with the main conductive layer without leaving voids inside. .

Thus, increase in wiring resistance and contact resistance in the contact hole (through hole) portion, disconnection (due to migration and step break) are avoided, and wiring and contact hole (through hole) are miniaturized to achieve high integration. Degradation of the performance and reliability of the semiconductor device is prevented.

[0013]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. FIG. 1 is a schematic sectional view of an embodiment of the structure of the present invention,
2 and 3 are process sectional views of an embodiment of the method of the present invention. The same object is denoted by the same reference numeral throughout the drawings.

In FIG. 1, 1 is a Si substrate having one conductivity type of p or n, and 2 is n ⁺ or p having a shallow junction.
Impurity diffusion region having opposite conductivity type of ⁺ , 3 is a lower layer insulating film made of silicon oxide (SiO ₂ ) or the like and having a thickness of about 6000 to 8000Å, 4 is a contact hole having a diameter of about 8000Å, 5 is a film thickness from the lower part A first barrier metal layer with a thickness of 1300 to 1800 Å consisting of a Ti film with a thickness of 300 Å and a TiN film with a film thickness of 1000 to 1500 Å, 6 is 100 to 200 Å which is almost uniform in each part.
Amorphous or polycrystalline first Si having a thickness of about 1
Layer, 7 is, for example, made of Al-1% Si alloy and has a thickness of 6000 to 7000Å
1st layer Al wiring, 8 is an interlayer insulating film made of phosphosilicate glass (PSG) with a thickness of about 1 μm, 9 is a through hole with a diameter of about 8000 Å, 10 is the same structure as the first barrier metal layer A second barrier metal layer having 11; an amorphous or polycrystalline second Si layer having the same thickness as the first Si layer;
Reference numeral 12 indicates a second layer Al wiring made of, for example, Al-0.5% Cu alloy and having a thickness of about 1 μm.

The semiconductor device according to the present invention has, for example, a structure as shown in FIG. 1 described above, and is manufactured according to the present invention as described below with reference to FIGS. 2 and 3. Formed by the method.

Referring to FIG. 2A, that is, 2000 is formed on the surface of the Si substrate 1 having one conductivity type.
An impurity diffusion region 2 of opposite conductivity type having a shallow junction of about Å is formed, and this substrate 1 is covered with a lower layer insulating film 3 made of, for example, CVD-SiO ₂ and having a thickness of about 6000 to 8000Å. In the substrate to be processed, the contact hole 4 having a diameter of about 8000Å which exposes the impurity diffusion region 2 is formed by a known method, and first, on the substrate,
The thickness is 300Å by the usual sputtering method as before.
A Ti film having a thickness of about 1300 to 1800Å is formed by sequentially depositing a Ti film having a thickness of about 1000 to 1500Å and a first barrier metal layer 5 having a Ti / TiN structure having a thickness of about 1300 to 1800Å. Here, since the step coverage of the Ti film and the TiN film by the usual sputtering method is not sufficient, the side wall surface of the contact hole 4 having an aspect ratio of about 1 as described above has a lacking portion of the first barrier metal layer 5. Yields 13.

Then, referring to FIG. 2 (b), monosilane (SiH ₄ ) or disilane is formed on the substrate.
By a normal full-scale CVD method using (Si ₂ H ₆ ) as a growth gas,
A thin amorphous or polycrystalline first Si layer 6 having a thickness of about 100 to 200 Å is formed. Here, Si by the above CVD method
Since the step coverage of the layer is very excellent,
The layer 6 is not only on the lower insulating film 3 having the first barrier metal layer 5, but also on the lacking portion 13 of the first barrier metal layer 5.
The inner surface of the contact hole 4 having the above, that is, the side wall surface and the bottom surface are also formed with a substantially uniform thickness.

The growth conditions in the above-mentioned full-face CVD of Si are as follows, for example. Growth gas Si ₂ H ₆ 60 sccm Carrier gas N ₂ 100 sccm Growth pressure 0.4 Torr Growth temperature 450 ° C See Fig. 2 (c) Next, the thickness of Al-1% Si alloy is formed on the above substrate by high temperature bias sputtering method. The first of about 6000-7000Å
The Al wiring layer 107 is deposited. The conditions for high temperature bias sputtering are: substrate heating temperature: 400 to 500 ° C, substrate bias: −
Set to about 400 to -600V.

Here, the first Al wiring layer 107 is the same as the first Al wiring layer 107.
Since the surface is moved along the Si layer 5 to be deposited to a uniform thickness, the side wall surface and the bottom surface of the contact hole 4 in which the first Si layer 6 is formed to have a uniform thickness without any missing portion. Also, the Al layer 107 is deposited at a uniform rate, and the inside of the contact hole 4 is uniformly filled with the Al layer 107 without leaving a void. Although the generation of voids can be avoided by using a normal sputtering method, the high temperature bias sputtering is more complete.

Further, the first Al wiring layer 107 may be formed by whole surface chemical vapor deposition. In this case, since most of the chemical vapor deposition is a surface reaction, the adhesion to the Si layer 5 is enhanced, so that it is more desirable when the Si layer 5 is used as an adhesion layer.

Next, referring to FIG. 2 (d), a resist pattern (not shown) formed by a usual photo process is used as a mask to perform Al by a reactive ion etching (RIE) process using a chlorine-based gas.
The layer 107 is patterned, and then the first Si layer 6 and the first barrier metal layer 5 are patterned by the RIE process using a fluorine-based gas to form the barrier metal layer 5 and the first Si layer.
A first layer 6 and a first Al wiring layer 107, which are sequentially stacked.
The layer Al wiring 7 is formed. Here, the first barrier metal layer 5 existing at the bottom of the contact hole 4 is made of Al and the substrate.
It serves as a barrier to mutual diffusion with Si.

Next, as shown in FIG. 2E, an interlayer insulating film 8 made of PSG or the like having a thickness of about 1 μm is formed on the above-mentioned substrate by a normal CVD method. 1 layer
A through hole 9 having a diameter of about 8000Å is formed to expose the Al wiring 7.

Next, as shown in FIG. 3 (a), a Ti film having a thickness of about 300 Å and a thickness of about 1000 to 1500 Å are formed by an ordinary sputtering method in the same manner as when the first layer Al wiring 7 is formed on the substrate. Thickness consisting of TiN film
Form the second barrier metal layer 10 of about 1300 to 1800Å,
Next, a thickness of 100
~ 200 Å thin amorphous or polycrystalline second Si
Form layer 11. Here, since the step coverage of the Ti film and the TiN film by the ordinary sputtering method is not sufficient, the portion where the second barrier metal layer 10 is absent on the side wall surface of the through hole 9 having the aspect ratio of 1 or more as described above. Yields 14.
Further, since the step coverage of the Si layer 11 by the CVD method is very excellent, the second Si layer 11 can be formed not only on the interlayer insulating film 8 having the second barrier metal layer 10 but also on the second layer. The inner surface, that is, the side wall surface and the bottom surface of the through hole 9 having the lacking portion 14 of the barrier metal layer 10 is also formed to have a substantially uniform thickness.

Then, referring to FIG. 3 (b), Al is formed on the substrate by a high temperature bias sputtering method.
-Second layer Al wiring layer made of 0.5% Cu alloy and having a thickness of about 1 μm
Deposit 112. The conditions for high temperature bias sputtering are:
Substrate heating temperature: 400 to 500 as in the case of Al wiring layer
C, substrate bias: set to about -400 to -600V.

Since the second Al wiring layer 112 also moves along the surface of the second Si layer 10 and is deposited to have a uniform thickness,
Al layer is evenly formed on the side wall surface and the bottom surface of the through hole 9 in which the second Si layer 10 is formed to have a uniform thickness without any missing portion.
112 is deposited, and the through hole 9 is uniformly filled with the Al layer 112 without leaving a void inside.

Next, referring to FIG. 1, a rate pattern (not shown) formed by a usual photo process is used as a mask to perform a second reactive ion etching (RIE) process using a chlorine-based gas.
Patterning the Al wiring layer 112, and then patterning the second Si layer 11 and the second barrier metal layer 10 by RIE processing with a fluorine-based gas, and then the second barrier metal layer 10 and the second Si layer. The second layer Al wiring 12 is formed by sequentially laminating the layer 11 and the second Al wiring layer 112, and thereafter, a coating insulating film (not shown) is formed to form a semiconductor device having a multilayer Al wiring structure according to the present invention. Is completed. Here, the second barrier metal layer 10 existing at the bottom of the through hole 9 is made of Al
It serves as a barrier that prevents Si and Cu from diffusing each other.

In the laminated Al wiring having the barrier metal layer as the lower layer of the present invention formed by the manufacturing method according to the present invention as shown in the above examples, Al-1% serving as the main conductive layer is formed.
Al wiring layer made of Si alloy or Al-5% Cu alloy (107,
112) and the barrier metal layer (4, 10 etc.) have a very good step coverage and are formed on the sidewalls and bottom surfaces of the contact hole 4 and the through hole 9 with a uniform thickness.
A Si layer (6, 11 etc.) is provided. As a result, the Al wiring layers (107, 112, etc.) having a high wettability with respect to Si, which are deposited on the upper portion thereof by a sputtering method such as a high temperature bias sputtering method, move on the surface along the Si layer. Are deposited from the side wall surface and the bottom surface of the contact hole 4 or the through hole 9 at a substantially uniform rate. Then, the contact hole 4 or the through hole 9 is uniformly filled with an Al wiring layer (107, 112, etc.) without leaving a void inside.

Although Al alloys such as Al-Si and Al-Cu are used for the main conductive layers of the lower and upper internal wirings in the above embodiments, pure Al may be used for the main conductive layers, as a matter of course. It is also effective when using a refractory metal by sputter deposition for the main conductive layer. The CVD-Si layer also serves as an adhesion layer on the insulating film when the main conductive layer of tungsten or the like is formed by the entire surface vapor phase growth means.

[0029]

As described above, according to the present invention, when the internal wiring having the laminated structure having the barrier metal layer as the lower layer is used, the main conductive layer of, for example, an Al alloy is formed in the fine contact holes or through holes. Can be buried uniformly without leaving voids, and increase in wiring resistance or contact resistance in the contact hole or through hole portion can be prevented, and disconnection due to step disconnection, electromigration, stress migration, etc. can be prevented.

Therefore, the present invention is intended to prevent deterioration of performance and reliability of a highly integrated semiconductor device in which contact holes and through holes are miniaturized and internal wiring having a laminated structure having a barrier metal layer as an underlying layer is used. There is a big contribution.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of the structure of the present invention.

FIG. 2 is a process sectional view (1) of an embodiment of the method of the present invention.

FIG. 3 is a process sectional view of an embodiment of the method of the present invention (No. 2)

FIG. 4 is a schematic cross-sectional view showing a conventional problem

[Explanation of symbols]

 1 Si Substrate 2 Impurity Diffusion Region 3 Lower Layer Insulation Film 4 Contact Hole 5 First Barrier Metal Layer 6 First Si Layer 7 First Layer Al Wiring 8 Interlayer Insulation Film 9 Through Hole 10 Second Barrier Metal Layer 11 Second Si layer 12 Second layer Al wiring 13, 14 Barrier metal layer lacking portion 107 First Al wiring layer 112 Second Al wiring layer

Claims (5)

[Claims] 1. A barrier metal layer, a silicon layer, and
A semiconductor device having internal wiring of a laminated structure in which main conductive layers made of aluminum or its alloy or refractory metal are sequentially laminated. 2. The semiconductor device according to claim 1, wherein the barrier metal layer is made of a laminated film of titanium and titanium nitride. 3. A barrier metal layer, a silicon layer,
When forming a laminated wiring layer used for internal wiring of a laminated structure in which main conductive layers made of aluminum or its alloy or refractory metal are sequentially laminated, a step of forming a barrier metal layer on a substrate by sputtering means, and then the whole surface A semiconductor device comprising a step of forming a silicon layer by chemical vapor deposition means, and then a step of forming a main conductive layer made of aluminum or its alloy or refractory metal by sputtering means or whole surface chemical vapor deposition means. Manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the sputtering means for forming the main conductive layer is a high temperature bias sputtering method. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the barrier metal layer is made of a laminated film of titanium and titanium nitride.