JPH0228253B2 - - Google Patents
Info
- Publication number
- JPH0228253B2 JPH0228253B2 JP58223566A JP22356683A JPH0228253B2 JP H0228253 B2 JPH0228253 B2 JP H0228253B2 JP 58223566 A JP58223566 A JP 58223566A JP 22356683 A JP22356683 A JP 22356683A JP H0228253 B2 JPH0228253 B2 JP H0228253B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- metal
- film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000001947 vapour-phase growth Methods 0.000 claims description 9
- 229910001507 metal halide Inorganic materials 0.000 claims description 6
- 150000005309 metal halides Chemical class 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 150000004820 halides Chemical class 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 239000012808 vapor phase Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 51
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 150000002222 fluorine compounds Chemical class 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910001512 metal fluoride Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、集積回路などの半導体装置の製造
方法に係わり、特に配線層が二層またはこれ以上
におよぶ多層配線構造の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device such as an integrated circuit, and particularly to a method of forming a multilayer wiring structure having two or more wiring layers.
［発明の技術的背景とその問題点］
従来多層配線を形成する方法として、一般に第
１図に示す様に半導体素子を形成した基板１１上
に絶縁膜１２を介して第１層目の配線層１３，１
３1，１３2を形成した後、絶縁膜１４を被着し、
該絶縁膜１４に接続孔（スルーホール）を形成し
て、第２層目の配線層１５を形成する方法が用い
られている。シリコン集積回路の如き半導体装置
の配線金属としては、通常スパツタリング方法に
より被着したAlあるいはAlを主成分とする合金
が用いられている。[Technical Background of the Invention and Problems Therewith] Conventionally, as shown in FIG. 1, a method for forming multilayer wiring is to deposit a first wiring layer on a substrate 11 on which a semiconductor element is formed via an insulating film 12. 13,1
After forming 3 1 and 13 2 , an insulating film 14 is deposited,
A method is used in which a connection hole (through hole) is formed in the insulating film 14 and the second wiring layer 15 is formed. As wiring metal for semiconductor devices such as silicon integrated circuits, Al or an alloy mainly composed of Al deposited by a sputtering method is usually used.
しかし、半導体装置の高密度化が進み、多層配
線が微細化するにつれてエレクトロマイグレーシ
ヨンによる配線の断線が問題となつている。特
に、多層配線の微細化においては、配線層間を接
続するためのスルーホールを微細化する必要があ
り、このため異方性ドライエツチングが用いられ
るようになり、スルーホールが必然的に急峻な深
い穴となる。この結果スパツタリング法で被着し
たAl膜では、いわゆるシヤドウイングのために
被覆性が著しく悪くなり、電気的導通がとれなか
つたり、エレクトロマイグレーシヨンによる断線
が短時間で生ずるなどの問題があつた。 However, as the density of semiconductor devices increases and multilayer wiring becomes finer, wire breakage due to electromigration has become a problem. In particular, in the miniaturization of multilayer wiring, it is necessary to miniaturize the through holes for connecting wiring layers, and for this reason anisotropic dry etching has come to be used. It becomes a hole. As a result, the Al film deposited by the sputtering method had problems such as extremely poor coverage due to so-called shadowing, failure to establish electrical continuity, and short-term disconnection due to electromigration.
このような問題を解決するために、第２図に示
すように、絶縁膜１４に形成したスルーホール内
に選択的に金属膜１６を埋込んでから第２層目の
配線層１５を形成する方法が考えられている。こ
のような金属膜１６の埋込みは、金属ハロゲン化
物ガスを用いた選択気相成長法により可能であ
る。例えばWF6ガスを用いたＷ膜の選択成長法
が注目されている。 In order to solve this problem, as shown in FIG. 2, a metal film 16 is selectively buried in the through holes formed in the insulating film 14, and then a second wiring layer 15 is formed. A method is being considered. Such embedding of the metal film 16 is possible by selective vapor deposition using metal halide gas. For example, a method of selectively growing a W film using WF 6 gas is attracting attention.
この方法を用いれば、スルーホールの段差を減
らすことにより、配線の断切れやエレクトロマイ
グレーシヨンによる断線を防止することができ
る。 By using this method, it is possible to prevent wiring breakage and disconnection due to electromigration by reducing the step difference in the through hole.
ところがこの方法においては、配線層間の接触
抵抗が高いという別の問題がある。例えば第１層
配線をAl配線とし、この上を絶縁膜でおおつて
スルーホールをあけた後、基板温度約350℃、反
応室内圧力約10-2Torrに設定してWF6ガスによ
るＷ膜の選択成長を行うと、成長初期において
AlとWF6ガスとの反応によつて抵抗の高いAlの
フツ化物が生成される。このフツ化物は蒸気圧が
低いために、成長するＷ膜とAl配線との間に残
される。その結果、第１層Al配線と第２層Al配
線の接触抵抗は１×10-7Ω・cm2程度となり、Al配
線同志が直接接触した場合に比べて約２桁も高い
接触抵孔値を示すことになる。このことは、特に
微細配線構造とした場合の素子の高速動作を妨げ
る限因となる。 However, this method has another problem in that the contact resistance between wiring layers is high. For example, the first layer wiring is Al wiring, and after covering it with an insulating film and making a through hole, the substrate temperature is set to approximately 350°C and the reaction chamber pressure is approximately 10 -2 Torr, and the W film is insulated using WF 6 gas. When selective growth is performed, in the early stage of growth
A highly resistive Al fluoride is produced by the reaction between Al and WF 6 gas. Since this fluoride has a low vapor pressure, it remains between the growing W film and the Al wiring. As a result, the contact resistance between the first layer Al wiring and the second layer Al wiring is approximately 1×10 -7 Ω・cm 2 , which is about two orders of magnitude higher than when the Al wirings are in direct contact with each other. will be shown. This is a limiting factor that hinders high-speed operation of the device, especially when it has a fine wiring structure.
［発明の目的］
本発明の目的は、微細なスルーホールに対して
も断線のない高い信頼性を有する多層配線を十分
に低い層間接触抵抗をもつて実現しうる半導体装
置の製造方法を提供することにある。[Object of the Invention] An object of the present invention is to provide a method for manufacturing a semiconductor device that can realize highly reliable multilayer wiring with sufficiently low interlayer contact resistance without disconnection even in the case of minute through holes. There is a particular thing.
［発明の概要］
本発明は、下地配線層上の絶縁膜に設けられた
スルーホール内部に金属ハロゲン化物ガスを用い
た気相成長法により金属膜を選択的に成長させる
に当つて、下地配線層表面部を金属またはその化
合物とし、かつ少くとも初期条件として、反応室
内圧力を前記接続孔に露出する下地配線層の表面
部の金属と金属ハロゲン化物ガスとの反応により
生じるハロゲン化物の蒸気圧に比べて低く設定し
たことを特徴とする。[Summary of the Invention] The present invention provides a method for selectively growing a metal film inside a through hole provided in an insulating film on an underlying wiring layer by a vapor phase growth method using a metal halide gas. The layer surface portion is a metal or its compound, and at least as an initial condition, the pressure in the reaction chamber is set to the vapor pressure of the halide generated by the reaction between the metal on the surface portion of the underlying wiring layer exposed to the connection hole and the metal halide gas. It is characterized by being set lower than .
［発明の効果］
本発明によれば、選択気相成長によりスルーホ
ール内に埋め込まれる金属膜と下地配線層との間
に高抵抗層が介在することが抑制され、多層配線
の層間の接触抵抗を十分小さくすることができ
る。従つて配線の段切れやエレクトロマイグレー
シヨンによる劣化が防止されるだけでなく、微細
な多層配線をもつた高速動作が可能な半導体装置
を得ることができる。[Effects of the Invention] According to the present invention, interposition of a high resistance layer between the metal film embedded in the through hole and the underlying wiring layer is suppressed by selective vapor deposition, and the contact resistance between layers of multilayer wiring is reduced. can be made sufficiently small. Therefore, it is possible to not only prevent wiring breakage and deterioration due to electromigration, but also to obtain a semiconductor device having fine multilayer wiring and capable of high-speed operation.
［発明の実施例］ 本発明の実施例を図面を参照して説明する。[Embodiments of the invention] Embodiments of the present invention will be described with reference to the drawings.
第３図ａ〜ｃは本発明の一実施例を示す工程断
面図である。まず第３図ａに示す様に、素子が形
成されたSi基板２１の上に絶縁膜２２を介して第
１層目のAl膜またはAlを主成分とする合金膜か
らなる配線（以下単にAl配線と呼ぶ）２３を１
［μｍ］の厚さに形成する。このAl配線２３の表
面には200〜1000Åの金属膜２４（２４1，２４2）
が積層してある。この金属膜２４は、後の金属ハ
ロゲン化物ガスを用いた選択気相成長工程でAl
のハロゲン化物よりも蒸気圧の高いハロゲン化物
を生成するものであればよく、高融点金属である
Mo、Ｗ、Tiあるいはこれらの化合物を利用する
ことができる。 FIGS. 3a to 3c are process cross-sectional views showing one embodiment of the present invention. First, as shown in FIG. 3a, a first layer of Al film or an alloy film mainly composed of Al (hereinafter simply referred to as Al (called wiring) 23 to 1
It is formed to a thickness of [μm]. A metal film 24 (24 1 , 24 2 ) with a thickness of 200 to 1000 Å is on the surface of this Al wiring 23.
are stacked. This metal film 24 is formed by Al in a later selective vapor phase growth process using metal halide gas.
Any metal that produces a halide with a higher vapor pressure than the other halide is sufficient, and is a high melting point metal.
Mo, W, Ti or a compound thereof can be used.
次に全面に絶縁膜２５を１［μｍ］の厚さ被着
し、配線間を接続するためのスルーホール２６を
絶縁膜２５の所望の位置に公知の写真食刻法によ
り形成する。この場合の絶縁膜２５としては、プ
ラズマ気相成長法あるいはバイアススパツタリン
グ法などにより形成したSiO2膜などを用いる。 Next, an insulating film 25 with a thickness of 1 μm is deposited on the entire surface, and through holes 26 for connecting wiring lines are formed at desired positions in the insulating film 25 by a known photolithography method. As the insulating film 25 in this case, an SiO 2 film or the like formed by plasma vapor deposition method or bias sputtering method is used.
次に第３図ｂに示す如く、スルーホール２６内
に、六弗化タングステン（WF6）ガスとH2ガス
を用いた気相成長法によりタングステンＷ膜２７
を0.3〜１［μｍ］の厚さに被着する。この時のＷ
膜２７の被着条件としては、基板温度250〜400
［℃］、反応室内の圧力１×10-2［Torr］以下、
WF6ガスの分圧１×10-4〜５×10-2［Torr］の範
囲が望ましい。 Next, as shown in FIG. 3b, a tungsten W film 27 is grown in the through hole 26 by vapor phase growth using tungsten hexafluoride (WF 6 ) gas and H 2 gas.
to a thickness of 0.3 to 1 [μm]. W at this time
The deposition conditions for the film 27 include a substrate temperature of 250 to 400°C.
[℃], pressure in the reaction chamber 1×10 -2 [Torr] or less,
The partial pressure of WF 6 gas is preferably in the range of 1×10 −4 to 5×10 −2 [Torr].
次に第３図ｃに示す如く、Ｗ膜２７を介して第
１層Al配線２３に接続する第２層Al配線２８を
形成する。 Next, as shown in FIG. 3c, a second layer Al wiring 28 is formed which is connected to the first layer Al wiring 23 via the W film 27.
この様にして得られた２層配線構造は、スルー
ホール２６の口経が１［μｍ］程度の微細なもの
でも、第２層Al配線２８の段切れや、エレクト
ロマイグレーシヨンによる断線などのない信頼性
の高いものとなる。 The two-layer wiring structure obtained in this way does not cause breakage of the second layer Al wiring 28 or disconnection due to electromigration, even if the diameter of the through hole 26 is as small as 1 [μm]. It becomes highly reliable.
また、第１層Al配線２３の表面には金属膜２
４が形成されているため、Ｗ膜２７の気相成長工
程で抵抗の高いAlのフツ化物が生成されること
はなく、WF6と金属膜２４の反応により生成さ
れる金属のフツ化物は蒸気圧が高くて容易に飛散
してしまうため、第１層Al配線２３と第２層Al
配線２８の接続部に高抵抗のフツ化物層が残らな
い。従つて配線層間の接触抵抗が小さいものとな
り、第１層Al配線上のスルーホールに直接Ｗ膜
を選択成長して第２層Al配線を形成した場合に
比べて、半導体装置の高速動作が可能となる。 Further, a metal film 2 is provided on the surface of the first layer Al wiring 23.
4 is formed, high-resistance Al fluoride is not generated in the vapor phase growth process of the W film 27, and the metal fluoride generated by the reaction between WF 6 and the metal film 24 is vaporized. Since the pressure is high and it easily scatters, the first layer Al wiring 23 and the second layer Al
No high-resistance fluoride layer remains at the connection portion of the wiring 28. Therefore, the contact resistance between the wiring layers is small, and the semiconductor device can operate at higher speeds than when the second layer Al wiring is formed by selectively growing a W film directly on the through hole on the first layer Al wiring. becomes.
なお、上記実施例では、第１層Al配線２３の
表面全面に金属膜２４を積層しているが、この金
属膜２４は少くともスルーホール２６部分にあれ
ば目的は達成される。従つて例えば、第１層Al
配線を形成した後絶縁膜でおおつてスルーホール
をあけ、この後イオン注入等によりスルーホール
に露出したAl配線表面部にのみ高融点の金属
Mo、Ｗなどを注入するようにしてもよい。 In the above embodiment, the metal film 24 is laminated over the entire surface of the first layer Al wiring 23, but the purpose can be achieved as long as the metal film 24 is at least on the through hole 26 portion. Therefore, for example, the first layer Al
After the wiring is formed, it is covered with an insulating film and a through hole is made, and then a metal with a high melting point is applied only to the surface of the Al wiring exposed in the through hole by ion implantation etc.
Mo, W, etc. may also be implanted.
次に本発明の別の実施例を第４図ａ〜ｃにより
説明する。なお、第３図ａ〜ｃと対応する部分に
は同一符号を付して詳細な説明は省く。この実施
例では、第４図ａのように第１層Al配線２３の
表面に何らの物質膜を積層することなく、絶縁膜
２５を形成してスルーホール２６をあける。そし
てWF6ガスを用いた気相成長法により、第４図
ｂのようにスルーホール２６内にＷ膜２７を埋込
む。ここでＷ膜２７の埋込み工程の条件が従来と
異なる。例えば基板温度を250〜400［℃］、WF6
ガス分圧を１×10-4〜５×10-2［Torr］に設定
し、かつ少くとも成長の初期において反応室内圧
力を例えば10-4〜10-5［Torr］という十分低い値
に設定して気相成長を行う。このような低い反応
室内圧力の下でＷ膜２７の選択成長を行うことに
より、WF6ガスとAlとの反応により生成される
Alのフツ化物の多くが飛散する結果、Ｗ膜２７
と第１層Al配線２３の間にあまり高抵抗層が残
らない。この後先の実施例と同様、第４図ｃに示
すように第２層Al配線２８を形成する。 Next, another embodiment of the present invention will be described with reference to FIGS. 4a to 4c. Note that portions corresponding to those in FIGS. 3a to 3c are designated by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, as shown in FIG. 4A, an insulating film 25 is formed without stacking any material film on the surface of the first layer Al wiring 23, and a through hole 26 is formed. Then, a W film 27 is embedded in the through hole 26 by vapor phase growth using WF 6 gas, as shown in FIG. 4b. Here, the conditions for the process of embedding the W film 27 are different from those of the conventional method. For example, set the substrate temperature to 250 to 400 [℃], WF 6
Set the gas partial pressure to 1×10 -4 to 5×10 -2 [Torr], and set the reaction chamber pressure to a sufficiently low value of, for example, 10 -4 to 10 -5 [Torr] at least at the initial stage of growth. and perform vapor phase growth. By selectively growing the W film 27 under such a low reaction chamber pressure, the W film 27 is produced by the reaction between the WF 6 gas and Al.
As a result of most of the Al fluoride scattering, the W film 27
Not much high-resistance layer remains between the layer and the first layer Al wiring 23. Thereafter, as in the previous embodiment, a second layer Al wiring 28 is formed as shown in FIG. 4c.
この実施例によつても、従来に比べて配線層間
の接触抵抗を十分に小さいものとすることが可能
である。 Also in this embodiment, it is possible to make the contact resistance between wiring layers sufficiently smaller than in the conventional case.
なお、本発明は上述した実施例に限定されるも
のではない。例えば、第１層の配線材料はAlに
限るものではなく、Mo、Ｗ、Ta等の金属膜でも
よい。特にフツ化物の蒸気圧が高い材料を用いれ
ば金属の選択成長の際の反応室内圧力を低くする
だけの第４図の実施例で十分な効果が得られる。
また、上記実施例では、スルーホール部への金属
膜の気相成長をWF6ガスを用いたＷ膜の成長の
場合について説明したが、Mo、Ta、Nbなどの
弗化物による気相成長を用いても同様の効果が得
られる。さらに、これらの金属の塩化物を利用し
てもよい。 Note that the present invention is not limited to the embodiments described above. For example, the wiring material of the first layer is not limited to Al, but may be a metal film such as Mo, W, or Ta. In particular, if a material with a high fluoride vapor pressure is used, sufficient effects can be obtained with the embodiment shown in FIG. 4, which merely lowers the pressure in the reaction chamber during selective growth of metal.
In addition, in the above example, the vapor phase growth of the metal film on the through-hole portion was explained using W film growth using WF 6 gas, but vapor phase growth using fluorides such as Mo, Ta, and Nb was also described. Similar effects can be obtained by using Furthermore, chlorides of these metals may also be used.
また、上記実施例では２層配線について述べた
が、３層以上の多層配線に適用しても同様な効果
が得られる。この場合例えば、第１層と第３層配
線とを接続するに当つて、第１のスルーホール
（第１層配線と第２層配線との接続）の面上に第
２のスルーホール（第２層配線と第３層配線との
接続）を設けても平坦な配線構造が得られ、接続
面積の小さい信頼性の高い多層配線が形成でき
る。さらに、スルーホール部が平坦な配線構造に
なつているためスルーホール上にも一様な厚さの
平坦な絶縁膜が形成できる結果、第２層配線と第
３層配線との絶縁特性が大幅に改善される。 Furthermore, although the above embodiments have been described with respect to two-layer wiring, similar effects can be obtained even when applied to multi-layer wiring with three or more layers. In this case, for example, when connecting the first layer and the third layer wiring, the second through hole (the connection between the first layer wiring and the second layer wiring) is formed on the surface of the first through hole (the connection between the first layer wiring and the second layer wiring). A flat wiring structure can be obtained even if a connection between a two-layer wiring and a third-layer wiring is provided, and a highly reliable multilayer wiring with a small connection area can be formed. Furthermore, since the through-hole part has a flat wiring structure, a flat insulating film with a uniform thickness can be formed on the through-hole, which greatly improves the insulation properties between the second layer wiring and the third layer wiring. will be improved.
その他、本発明の要旨を逸脱しない範囲で種々
変形して実施することができる。 In addition, various modifications can be made without departing from the gist of the present invention.
第１図および第２図は従来の製造方法による多
層配線構造を示す断面図、第３図ａ〜ｃは本発明
の一実施例を説明するための工程断面図、第４図
ａ〜ｃは他の実施例を説明するための工程断面図
である。
２１……Si基板、２２……絶縁膜、２３（２３
１，２３2）……第１層Al配線、２４（２４1，２
４2）……金属膜、２５……絶縁膜、２６……ス
ルーホール、２７……Ｗ膜、２８……第２層Al
配線。
1 and 2 are cross-sectional views showing a multilayer wiring structure according to a conventional manufacturing method, FIGS. 3 a to c are process cross-sectional views for explaining an embodiment of the present invention, and FIGS. FIG. 7 is a process sectional view for explaining another example. 21...Si substrate, 22...Insulating film, 23 (23
1 , 23 2 )...First layer Al wiring, 24 (24 1 , 2
4 2 )... Metal film, 25... Insulating film, 26... Through hole, 27... W film, 28... Second layer Al
wiring.
Claims (1)
た半導体基板上に接続孔をもつ絶縁膜を形成する
工程と、金属ハロゲン化合物ガスを用いて前記接
続孔に選択的に金属膜を気相成長させる工程と、
前記金属膜を介して下地配線層に接続する上部配
線層を形成する工程とを有する半導体装置の製造
方法において、前記下地配線層の少なくとも表面
部を金属またはその化合物とし、前記金属膜を気
相成長させる工程は、少なくとも初期条件とし
て、反応室内圧力を前記接続孔に露出する下地配
線層の表面部の金属と金属ハロゲン化物ガスとの
反応により生ずるハロゲン化物の蒸気圧に比べて
低く設定したことを特徴とする半導体装置の製造
方法。 ２ 前記下地配線層の表面部が高融点金属または
その化合物である特許請求の範囲第１項記載の半
導体装置の製造方法。[Claims] 1. A step of forming an insulating film having connection holes on a semiconductor substrate on which one or more underlying wiring layers are formed, and selectively filling the connection holes with metal halide gas. A process of vapor phase growth of a metal film;
forming an upper wiring layer connected to an underlying wiring layer through the metal film, wherein at least a surface portion of the underlying wiring layer is made of a metal or a compound thereof, and the metal film is heated in a vapor phase. In the growth step, at least as an initial condition, the pressure in the reaction chamber is set to be lower than the vapor pressure of the halide produced by the reaction between the metal on the surface of the underlying wiring layer exposed to the connection hole and the metal halide gas. A method for manufacturing a semiconductor device, characterized by: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the surface portion of the underlying wiring layer is made of a high melting point metal or a compound thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22356683A JPS60115221A (en) | 1983-11-28 | 1983-11-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22356683A JPS60115221A (en) | 1983-11-28 | 1983-11-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60115221A JPS60115221A (en) | 1985-06-21 |
| JPH0228253B2 true JPH0228253B2 (en) | 1990-06-22 |
Family
ID=16800164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22356683A Granted JPS60115221A (en) | 1983-11-28 | 1983-11-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60115221A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6365643A (en) * | 1986-09-05 | 1988-03-24 | Nec Corp | Manufacture of semiconductor device |
| JP2512740B2 (en) * | 1987-03-17 | 1996-07-03 | 富士通株式会社 | Method for manufacturing semiconductor device |
| DE3818509A1 (en) * | 1987-06-01 | 1988-12-22 | Gen Electric | METHOD AND DEVICE FOR PRODUCING A LOW-RESISTANT CONTACT WITH ALUMINUM AND ITS ALLOYS THROUGH SELECTIVE DEPOSITION OF TUNGSTEN |
| JPH0638416B2 (en) * | 1987-10-15 | 1994-05-18 | 日本電気株式会社 | Semiconductor device |
| JPH01262644A (en) * | 1988-04-13 | 1989-10-19 | Fujitsu Ltd | Method for forming wiring |
| JPH0235753A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH03116932A (en) * | 1989-09-29 | 1991-05-17 | Sharp Corp | Formation of multilayer wiring |
| JPH04226054A (en) * | 1990-03-02 | 1992-08-14 | Toshiba Corp | Semiconductor device having multilayered interconnection structure and its manufacture |
| KR0124644B1 (en) * | 1994-05-10 | 1997-12-11 | 문정환 | Forming method of multi metal line for semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5828856A (en) * | 1981-08-13 | 1983-02-19 | Nec Corp | Manufacture of semiconductor device |
-
1983
- 1983-11-28 JP JP22356683A patent/JPS60115221A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5828856A (en) * | 1981-08-13 | 1983-02-19 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60115221A (en) | 1985-06-21 |
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