JPH065673B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a planarized gate electrode wiring and a planarized multilayer wiring mainly composed of refractory metal and a method of manufacturing the same. is there.

BACKGROUND ART Al is generally used as a wiring material of a semiconductor device, but the wiring current density increases as the semiconductor device is miniaturized, so that the reliability of wiring due to electromigration becomes a problem. There is. In order to solve this problem, it is possible to use a refractory metal such as Mo or W for the wiring, but the refractory metal has problems such as poor adhesion to the underlying oxide film and difficult processing.

In addition, as semiconductor devices have become finer and more dense, wirings have been multi-layered. When forming multilayer wiring,
A method of covering an interlayer insulating film such as a lower layer SiO ₂ film by a vapor phase growth method, providing an opening (through hole, contact hole, etc.) at a desired position of this interlayer insulating film, and then performing wiring of an upper layer. Normally used. However, in this case, there are problems that patterning of the upper layer wiring by a photo process becomes difficult due to the unevenness of the interlayer insulating film due to the lower layer wiring, and the upper layer wiring is likely to be broken at the step portion. . In order to solve this problem, various flattening wiring techniques for flattening the wiring layer, the interlayer insulating film, or the through holes themselves have been proposed.

Among them, the main technology is Al that utilizes the deposition direction of Al vapor deposition.
Lift-off method, SiO ₂ using deposition direction of the SiO ₂ film
Film lift-off method, reactive ion etching (RI
There are an etch back method utilizing E), a bias sputtering method utilizing the characteristics of film deposition by sputtering and etching. However, in both the Al lift-off method and the SiO ₂ film lift-off method, when the Al or SiO ₂ film is deposited on the photoresist, the film adheres to the side surface of the photoresist, which causes a problem such as difficulty in removing the photoresist. is there. In addition, the etchback method has difficulty in controllability and reproducibility, and the bias sputtering method has a problem such as adverse effect on the element due to plasma impact.

Further, as the wiring becomes multi-layered and has a higher density, the aspect ratio of the through hole increases, and it becomes difficult to deposit the wiring metal in the through hole. In order to solve this problem, a technique of selectively burying tungsten (W) on the underlying semiconductor or Al wiring has been proposed, but if W is deposited thickly, the selectivity deteriorates. It wasn't enough to completely fill the through hole.

Problems to be Solved by the Invention As described above, recent miniaturization of semiconductor devices
With the trend toward higher densities, it is necessary to improve the manufacturing process. Above all, the wiring of the semiconductor device after the addition of the function has become complicated in accordance with the above trend, and therefore the multilayer wiring technology has been developed. In this multilayer wiring technology, it is necessary to provide a contact hole, a via hole, etc. in the interlayer insulating film in order to secure electrical connection between the element and the wiring or the wiring, but a step is formed in the wiring portion based on the existence of these. However, since there is no film forming method having a good step coverage, disconnection or the like occurs, so that the reliability of the wiring is significantly impaired. Therefore, the flattening of wiring has become an important issue, and various flattening techniques have been proposed. Also, the problem of planarization is important for the gate electrode wiring. As described above, the conventional method still has a problem to be solved, and the emergence of a new technique capable of solving the above problem is awaited.

Further, since the wiring current density increases due to the miniaturization of the semiconductor device, electromigration may occur and the reliability of the wiring is impaired. Therefore, it is considered advantageous to use a refractory metal as a wiring material. However, there is a problem with the adhesiveness to the insulating layer and the workability, and the utilization technology was not sufficient.

Therefore, a first object of the present invention is to provide a semiconductor having a wiring structure mainly composed of a refractory metal, which solves the problems of electromigration and deterioration of wiring reliability due to poor adhesion between the wiring material and the underlying oxide film. An object is to provide a device and a manufacturing method thereof.

A second object of the present invention is to provide a fine and flat gate electrode wiring or multilayer wiring structure and a manufacturing method thereof, which solves the problems of various planarization techniques.

A third object of the present invention is to provide a fine and deep through-hole structure having a large aspect ratio, a semiconductor device having such a structure, and a manufacturing method thereof.

Means for Solving the Problems The present inventors have found that the above-described object of the present invention is to provide a groove or a hole in an insulating film on the surface of a conventional semiconductor substrate having a function, or a side surface of a hole provided in a conductive substance. The inventors have completed the present invention by finding that this can be achieved by providing a semiconductor or metal film on at least one of the side surface and the bottom surface of the provided insulator layer and burying a refractory metal in contact therewith.

That is, first, the semiconductor device of the present invention is provided with a groove or a hole whose side wall and bottom surface are made of an insulator, a conductor layer provided on at least one of the side surface and the bottom surface of the groove or hole, and a conductor layer in contact with the conductor layer. And a conductor structure including the high melting point metal layer.

The semiconductor device of the present invention can have a structure as shown in, for example, FIGS. 1 (a) to 1 (c).

Further, the semiconductor device of the present invention can be manufactured as follows. First, on a semiconductor substrate, for example, SiO ₂ , Si
Appropriately selected from known materials such as ₃ N ₄ , phosphorus glass (PSG), resins such as polyimide, and Al ₂ O ₃ according to the underlying (substrate) material, and the sputtering method, CVD method, plasma C
An insulating layer is formed by a VD method, an anodic oxidation method, or the like, and grooves or holes (hereinafter simply referred to as grooves for simplification) are formed in the insulating layer in a predetermined pattern by photoetching or the like. Using the resist pattern at this time as a mask to form a conductor layer (Si, Al, etc.) using various vapor deposition methods,
By removing the vapor-deposited layer other than the groove by lift-off, the conductor layer can be formed only on the bottom of the groove. In this case, it is advantageous to make the conductor layer thin.

When the conductor layer is formed only on the side surface of the groove, after forming the groove in the same manner as described above, the conductor film is formed by using a film forming method with good throwing power, for example, a vapor phase growth method. This can be achieved by forming the film so that it also adheres to the side surface and then etching the entire surface of the conductor film by a directional dry etching method.

Further, when forming a conductor film on both the side surface and the bottom surface of the groove, after forming the groove in the same manner, a conductor film is formed on the entire inner surface of the groove by a vapor deposition method such as a vacuum vapor deposition method or a vapor phase growth method. Then, apply a resist and remove the resist in the groove by etching back by plasma etching, reactive ion etching, etc., and remove the conductor layer other than the groove part by etching using the resist remaining in the groove as a mask. By removing the resist remaining in the groove, the conductor film can be formed on both the side surface and the bottom surface.

In this embodiment, it is advantageous to form the conductor layer thicker when using a vapor deposition method having poor throwing power. When the thickness is reduced, it is almost the same as the mode in which the conductor layer is formed only on the bottom. The thickness of the deposited layer at the bottom and that at the sidewall need not be the same.

Thus, the embedding of the refractory metal in the groove after covering at least one of the side surface and the bottom surface of the groove with the conductor film can be carried out by heating in a mixed atmosphere of a halide of each metal and H _2. . For example, when the refractory metal is W, the groove can be filled with W by heat-treating the semi-processed product obtained as described above in a mixed atmosphere of WF ₆ and H ₂ . The heating temperature is preferably about 400 ° C. or lower, and selective deposition can be expected within this range.

Further, according to still another aspect of the present invention, as shown in FIG. 5, a flat laminated structure similar to the above can be formed in the through hole portion having a high aspect ratio. This is done by first forming an insulator layer on the side surface of the hole by a thermal oxidation method or the like, then forming a conductor layer only on the side surface of the hole according to the method for forming a conductive layer only on the side surface of the groove, and then forming a high-conductivity layer as described above. A melting point metal layer can be selectively deposited on the conductor layer to obtain the final product. In this case, the refractory metal layer may fill the entire hole or may be hollow.

In order to achieve miniaturization in the multilayer wiring technique or gate electrode formation of a semiconductor device, it is necessary to use a wiring material that can withstand an increase in wiring current density, that is, a material that can prevent electromigration.

High melting point metals such as W and Mo are advantageous as materials that satisfy such requirements, but these have a problem in terms of adhesion to the base material. In this respect, according to the present invention, first, the conductive material (Al, Si) film, which is advantageous in both the adhesion to the base material (insulating film) and the adhesion to the refractory metal, is interposed. Problems such as can be solved.

Furthermore, another serious problem in multilayer wiring is planarization of the wiring structure. If the flattening is insufficient, there is a high possibility that the wiring layer will be fused or broken due to the electric field concentration at the step portion, and the reliability of the wiring will be significantly low. This flattening problem also occurs according to the present invention in the gate electrode wiring portion, the side surface of the groove corresponding to the through hole of the multilayer wiring portion,
This has been solved by forming a conductor film on at least one of the bottom surfaces and selectively filling the conductor film by heating in a mixed atmosphere of a halide of a refractory metal and H ₂ .

This is because the adhesion between the refractory metal used for embedding and the conductor layer such as Al is improved, and as a result, it becomes possible to selectively deposit the refractory metal only on the conductor film. It depends.

Therefore, according to the present invention, the aspect ratio of the through hole is large, and it is difficult to deposit the wiring metal in the through hole, which is difficult to deposit in the through hole by the conventional method. You can

Thus, in the semiconductor device of the present invention, based on the fact that the refractory metal layer is used as a wiring material, the risk of electromigration is extremely low, and sufficient improvement has been made in terms of planarization as well. In any case such as the case of the gate electrode wiring and the case of the multi-layer wiring structure, the reliability of the wiring is greatly improved, and the reliability of the semiconductor device itself is also greatly improved.

Further, according to the method of the present invention, a highly reliable semiconductor device can be advantageously manufactured, and miniaturization in recent semiconductor devices,
It can sufficiently cope with the trend of higher density.

Example An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing an embodiment of the present invention, in which a silicon substrate 1, a silicon oxide film 2, a groove 3 provided in the oxide film 2, and a polycrystalline silicon formed on the inner surface of the groove 3 are shown. Alternatively, it is composed of the aluminum layer 4 and the tungsten 5 buried in the groove 3. In FIG. 1 (a), the silicon oxide film 2
There is a polycrystalline silicon layer or aluminum layer 4 in contact with the bottom surface of the groove 3 provided in, and in (b) there is a polycrystalline silicon layer or aluminum layer 4 in contact with the sidewall of the groove 3,
In (c), a polycrystalline silicon layer or an aluminum layer 4 is provided in contact with the bottom surface and side wall of the groove 3. W is in contact with the polycrystalline silicon layer or aluminum layer 4 and the groove 3
It is embedded in. Gate electrode with such a structure
The method for constructing the wiring is shown below.

FIG. 2 is a process chart showing the first embodiment of the present invention,
The present invention relates to a method of forming a semiconductor or metal layer only on the bottom surface of the groove 3 and burying a refractory metal. As shown in FIG. 2 (a), a second silicon oxide film 2'is formed on the silicon substrate 1 covered with the silicon oxide film 2 of about 5000Å by about 5000Å.
Deposit. A photoresist film 6 is applied on the second silicon oxide film 2 ', a part of the photoresist is removed according to an electrode wiring pattern by a normal photolithography process, and then the second silicon is formed by a plasma etching method using the photoresist as a mask. A groove 3 is formed in the oxide film 2 '. Next, as shown in FIG. 2B, aluminum (Al) or silicon (Si) 4 is formed on the bottom of the groove 3 and the host resist 6 by vacuum evaporation while the host resist is applied.
Attach about 100Å. In this case, Al or S to be attached
Since i4 is thin, it hardly adheres to the side surface of the photoresist. Next, as shown in FIG. 3C, the photoresist 6 is removed with acetone, and at the same time, the photoresist 6 is removed.
The Al or Si 4 is lifted off to leave the Al or Si 4 only on the bottom of the groove 3 formed in the second silicon oxide film 2 ′.

FIG. 3 is a process chart showing a second embodiment of the present invention,
The present invention relates to a method of forming the semiconductor or metal layer 4 only on the side surface of the groove 3 and burying the refractory metal 5. Fig. 3
In (a), the Si film 6 is formed in the groove 5 formed in the silicon oxide film 2 by vapor phase growth so as to adhere to the side surface of the groove.
Next, as shown in FIG. 6B, Si 4 is etched over the entire surface by a directional dry etching method, and the Si film is left only on the side wall of the groove 3.

FIG. 4 is a process chart showing a third embodiment of the present invention,
A semiconductor or metal layer 4 is formed on both the bottom surface and the side surface of the groove 3.
As shown in FIG. 4 (a), which relates to a method of forming a metal and burying the high melting point metal 5, a groove 5 is formed in the silicon oxide film 2 on the silicon substrate 1 according to an electrode wiring pattern by a normal process. After that, by a vapor deposition method, Si film or Al
The film 4 is attached by several hundred Å. Next, as shown in FIG. 3B, a photoresist 6 is applied on the entire surface. In this case, since the photoresist 6 is also embedded in the groove 3, the photoresist 6 in the groove 3 is usually thicker than the photoresist other than the groove 3.
Next, as shown in FIG. 3C, the photoresist 6 is etched back by the plasma etching method to remove the photoresist 6 other than the groove 3. Next, as shown in FIG.
Using the photoresist 6 in the inside as a mask, Al or Si adhering to areas other than the groove 3 is removed by a normal etching method, and then the photoresist 6 in the groove 3 is removed to form a groove in the silicon oxide film 2. 3 on the bottom and sides of Si or
Leave Al4.

After depositing Si or Al only on the bottom or side surface of the groove 3 formed in the silicon oxide film by using any of the methods described above, FIG. 1 (a), (b), (c) As shown in
By heat treatment in a mixed atmosphere of F ₆ and H ₂ ,
W5 is buried in the groove 3 to form a buried wiring layer having a flat plane.

5A and 5B show another embodiment of the present invention,
This is an application of the second embodiment shown in FIG. First, after forming a hole penetrating the silicon substrate 11 in a desired region of the silicon substrate 11, the silicon oxide film 12 is formed by thermal oxidation. Next, polycrystalline silicon 13 is deposited, and according to the method described in the second embodiment, the polycrystalline silicon on the front and back surfaces of the silicon substrate 11 is removed by directional dry etching, and only the sidewalls of the holes are polycrystalline. A crystalline silicon layer 13 is formed. Then, by heat treatment in a mixed atmosphere of WF ₆ and H ₂ , W 14 and 14 ′ are embedded in the holes. When the depth is very large with respect to the diameter of the hole as in this embodiment, that is, when the aspect ratio is high, W14 is not necessarily obtained as shown in FIG.
It is not necessary to completely fill in the hole with W, as shown in Fig. 5 [B].
It is also possible to cover the side wall of the hole with 14 '.
Although the present embodiment is an example in which the silicon substrate 11 is penetrated, it goes without saying that it can be implemented with an insulator, and in that case, the silicon oxide film 12 is not necessary.

EFFECTS OF THE INVENTION As described above, in the present invention, since the wiring material is a refractory metal, it is possible to prevent deterioration of the reliability of the wiring due to electromigration, and Al or Si between the silicon oxide film and the refractory metal. Since there is a layer, the adhesion between the refractory metal and the silicon oxide film is good, Al or Si
The refractory metal must be processed because the refractory metal is selectively deposited only on the layer, and the refractory metal is formed by forming the Al or Si layer only on the bottom or side surface of the groove formed in the silicon oxide film. Embedded in the groove to form a buried wiring layer with a flat surface, and by forming a Si layer only on the side wall of a deep through hole with a large aspect ratio and depositing a refractory metal on the Si layer on the side wall, There is an advantage that a deep through hole in which is embedded can be formed. In this case, Al or
Although various methods of attaching Si can be considered, in any case, it is easy because the Al or Si layer may be thin.

Therefore, the semiconductor device of the present invention has high reliability in that electromigration does not occur even if the device is miniaturized and the density is increased, and there is no fear of disconnection.

[Brief description of drawings]

FIGS. 1 (a) to 1 (c) are cross-sectional configuration diagrams of three types of buried wirings, which are characteristic of the device of the present invention, and FIG. 2 is a process showing a first embodiment of the present invention. FIG. 3 is a diagram relating to a method of forming a semiconductor or metal layer only on the bottom surface of a groove, and FIG. 3 is a process diagram showing a second embodiment of the present invention,
The present invention relates to a method of forming a semiconductor or metal layer only on the side surface of a groove, and FIG. 4 is a process drawing showing a third embodiment of the present invention.
The present invention relates to a method for forming a semiconductor or metal layer on both the bottom and side surfaces of a groove, and FIG. 5 is a constitutional view of a deep through hole which is another embodiment of the present invention. (Main reference numbers) 1,11 ... Silicon substrate, 2, 2 ', 12 ... Silicon oxide film, 3 ... Groove, 4, 13 ... Al or Si layer, 6 ... Photoresist, 5, 14, 14 '... W

Claims (6)

[Claims] 1. A groove or hole whose side wall and bottom surface are made of an insulator, a conductor layer provided on at least one of the side surface and bottom surface of the groove or hole, and a high melting point provided in contact with the conductor layer. A semiconductor device comprising a conductor structure including a metal layer. 2. A groove or hole whose side wall and bottom surface are made of an insulator, a conductor layer provided on at least one of the side surface and bottom surface of the groove or hole, and a high melting point provided in contact with the conductor layer. In a method of manufacturing a semiconductor device having a conductor structure including a metal layer, a step of depositing a conductor material on at least one of a side surface and a bottom surface of the groove or hole, and a refractory metal on the conductor material layer. The method for manufacturing a semiconductor device as described above, comprising a step of selectively depositing. 3. A conductor layer is formed by a vapor deposition method using the resist pattern at the time of forming the groove or hole as a mask,
3. The method according to claim 2, wherein the conductor film is formed only on the bottom of the groove or hole by removing the deposited film on the portion other than the groove or hole by lift-off. 4. After forming the groove or hole, a conductor layer is formed by a vapor phase growth method, and then the entire conductor layer is removed by etching by a directional dry etching method to form the groove or hole. The method according to claim 2, wherein the conductor layer is formed only on the side surface. 5. After forming the groove or hole, a conductor film is formed on the entire side surface and bottom surface of the groove or hole by a vapor deposition method, and then a resist is applied and etched back to leave the inside of the groove or hole. 3. The conductive film is formed on both the bottom surface and the side surface of the groove or hole by removing a portion of the conductive layer other than the groove or hole by using the resist as a mask. the method of. 6. A sidewall of a hole is formed by forming an insulator film on a side surface of a hole provided in a conductive substrate, then depositing a conductive layer by vapor phase epitaxy, and etching by a directional dry etching method. The method according to claim 2, characterized in that the conductor layer is formed only on the substrate.