JP3254763B2 - Multi-layer wiring formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a multilayer wiring.

[0002]

2. Description of the Related Art FIG.
In a semiconductor integrated circuit device or the like, the first wiring 1 (the present invention)
The first wiring in the detailed description is a wiring such as a metal wiring.
In addition to designating the pattern, the electrode or wiring
Semiconductor substrate from which the lower wiring is derived)
A diffusion region or the like in a semiconductor layer is also referred to).
_TwoThe second wiring 3 is laminated via the interlayer insulating layer 2 by
Formed thereon, and an insulating layer 6 is further formed on the
A multilayer wiring structure with a high density is often employed.

In this multilayer wiring structure, for example, the connection between the second wiring 3 and the first wiring 1 is made by forming a connection hole 4 penetrating through the insulating layer 6 -the second wiring 3 -the lower interlayer insulating layer 2. And a conductor 5 is filled into the connection hole 4 so that the surface thereof is substantially flush with the surface of the upper interlayer insulating layer 2.
It is desired that the conductor 5 makes an electrical connection between the second wiring 3 and the first wiring 1.

That is, when such a configuration is adopted,
By flattening the surface, a third wiring is formed on the insulating layer 6 through an interlayer insulating layer (not shown), for example, and when the third wiring is connected to the second wiring, When a connection hole is formed in the interlayer insulating layer between the wirings and the connection is made, the position of the connection portion is determined by the first position.
Since it can be set at the connection position between the second wiring and the second wiring, that is, on the connection hole 4 or in the vicinity thereof, the integration degree can be further improved.

That is, now, for example, the first and second
When the connection between the wirings is made by inserting the second wiring 3 itself into the connection hole 4 of the interlayer insulating layer 2, a recess is formed on the surface of the connection. In addition, the connection between the second and third wirings cannot be provided directly above the connection due to a problem of reliability.

Therefore, the so-called plug-in vertical wiring for filling the connection hole 4 formed in the interlayer insulating layer 2 with the conductor 5 as described above has recently become important.

In the case of performing this plug-in vertical wiring, the above-mentioned conductor 5 is filled with, for example, tungsten W.
Is performed by selective CVD (chemical vapor deposition).
In practice, the growth of W is, for example, as shown in FIG.
Since the growth rate is different between the first wiring 1 made of Al and the second wiring 3 made of Al-Si or the like, cavities, that is, voids 7 are generated in the conductor 5 and the mechanical and electrical characteristics are reduced. May come.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a multi-layer wiring having a plug-in vertical wiring and having high reliability without generating voids or the like. .

[0009]

According to a first aspect of the present invention, as shown in FIG.
A second wiring 13 is formed thereon via an interlayer insulating layer 12, and a conductor 15 is filled in a connection hole 14 formed through the second wiring 13 and the interlayer insulating layer 12 thereunder. Then, in the multilayer wiring forming method in which the first wiring 12 and the second wiring 13 are electrically connected, after the formation of the connection hole 14 shown in FIG. 2C, as shown in FIG. The exposed surface of the second wiring 13 facing the inner peripheral surface of the connection hole 14 is oxidized.
After the formation of the edge film 18, the connection hole 14 is filled with the conductor 15.
Reduction is performed on the insulating film 18 on the way .

[0010]

[0011]

Here, the first wiring and the second wiring refer to a relatively lower wiring and an upper wiring formed thereon via an interlayer insulating layer, respectively. As described above, not only refers to a wiring pattern formed of, for example, metal wiring, but also refers to a semiconductor substrate or a diffusion region in a semiconductor layer from which wiring is derived.

[0013]

According to the present invention, in the filling of the conductor 15 into the connection hole 14 by, for example, selective CVD, at least at the initial stage of the growth, the conductor 1 is removed from the lower first wiring 11.
5 is formed, but an oxide insulating film 18 is formed from the exposed surface of the second wiring 13 of the upper wiring facing the connection hole 14.
To prevent the deposition film from being formed by the coating with the conductor 15, and then the removal is performed by reducing the oxide insulating film 18 so that the conductor 15 is in direct contact with the exposed surface of the second wiring 13 so that the filling is completed. To make it progress.

Therefore, according to this method, the conductor 15 is sequentially filled from the bottom of the connection hole 14, so that the structure shown in FIG.
Thus, it is possible to avoid the generation of voids as described in the above.

[0015]

EXAMPLES Examples of the method of the present invention will be described in detail.

In the present invention, as shown in FIG. 1, a second wiring 13 is formed on a first wiring 11 with an interlayer insulating layer 12 interposed therebetween, as shown in FIG. Wiring 13
A conductor 15 is filled in a connection hole 14 formed penetrating the first wiring 12 and the second
To form a multilayer wiring for making an electrical connection with the wiring 13.

An embodiment of the method of the present invention will be described with reference to FIGS. In this example, the first wiring 13 is, for example, a semiconductor substrate 21 having a semiconductor circuit element (not shown).
A substrate 21 is formed on an insulating layer (not shown) formed thereon.
The first wiring 11 and the second wiring 1 formed on the first wiring 11 via an interlayer insulating layer 12 are formed.
This is a case where the electrical connection with No. 3 is made by plug-in vertical wiring.

In this case, first, as shown in FIG. 2A, a first wiring 11, an interlayer insulating layer 12,
The second wiring 13 and the insulating layer 16 are sequentially formed.

The first wiring 11 is, for example, a Ti layer, a T layer
The iN layer, the Ti layer, the Al-Si layer, and the TiON layer were respectively formed by 30 nm, 70 nm, 30 nm, 300 nm, and 30 n.
m, for example, by sputtering continuously over the entire surface,
This laminated metal layer is formed into a required pattern by pattern etching by photolithography.

Here, Ti, TiN, and Ti are formed as barrier layers, and TiON is formed as an antireflection film for pattern exposure of a photoresist when pattern etching is performed by photolithography.

The interlayer insulating layer 12 and the insulating layer 16 are
It can be formed by SiO ₂ by VD.

The second wiring 13 is formed by forming a Ti layer and an Al-Si layer to a thickness of 60 nm and 90 nm, respectively, by continuous sputtering, and thereafter similarly forming a desired pattern by, for example, pattern etching by photolithography. Form.

First, as shown in FIG.
6, a photoresist (not shown) is entirely formed,
The connection portion between the first wiring 11 and the second wiring 13 is exposed to a pattern of connection holes 24 having a radius of, for example, 0.5 μm using a stepper, then developed and opened, and then dry-etched. For example, the condition of perpendicular anisotropy is used,
C ₄ F ₃ flow rate: 46 sccm, pressure: 2.0 Pa, high frequency (RF) output: 2.7 W / cm ² ,
An opening 24 is formed substantially perpendicular to the film surface.

Next, as shown in FIG. 2C, the second wiring 13 is similarly formed by dry etching using a magnetic field microwave etcher at a flow rate of BCl ₃ / Cl ₂ = 60.
/ 90 sccm, pressure: 2.0 Pa, microwave: 80
Anisotropic etching is performed under the conditions of 0 W and RF bias: 50 A. Further, the lower insulating layer 12 is etched under the same conditions as for the insulating layer 16 until the surface of the lower first wiring 11 is exposed, and a connection hole 14 is formed. Thereafter, the above-mentioned photoresist (not shown) is removed by a usual method.

Next, for example, as shown in FIG.
O ₂ flow rate: 50 sccm, pressure: 10 Pa, RF output 0.1 W / cm ² , thickness of about 10 n by plasma oxidation
An insulating film 18 of m oxide film is formed on the inner surface of the connection hole 14 and then the first wiring 1 is formed by vertical anisotropic etching.
Only the insulating film 18 on the first is removed.

Thereafter, the substrate 21 is placed in a selective W (tungsten) CVD apparatus, and NF ₃ / H ₂ = 10/50 s.
ccm, pressure: 6.7 Pa, RF output: 0.5 W / cm
^The pretreatment is performed under the condition of ² , and first, WF ₆ / SiH ₄ =
As shown in FIG. 3B, a portion of the conductor 15 is formed by selectively growing W under the second wiring 13 at 10/7 sccm and a pressure of 26.6 P ₃ at 260 ° C.

Next, WF ₆ / H ₂ = 10/1000 sc
cm, pressure: 26.6 Pa, conductor 15 at 400 ° C.
Is formed while reducing the oxide insulating layer 18 on the side wall.
The reduction in this case is effectively performed at this high temperature.

Thus, the first and second wirings 11 and 13 are connected by the conductor 15 shown in FIG.

FIG. 4 shows another embodiment of the present invention.
The same reference numerals are given to the portions corresponding to and the description thereof will not be repeated. In this case, first, as shown in FIG. 4A, the connection hole 14 is formed in the same manner as in the above-described embodiment, and
Is formed leaving the upper portion of the connection hole 14. afterwards,
Blanket tungsten with good coverage (hereinafter Bl
The connection holes 14 are buried by CVD (referred to as kW) to form the upper wiring 19. This utilizes the property that Blk-W grows over the entire surface. Also at this time, WF ₆ / H
_{In step 2} , Blk-W is grown at 450 ° C. or higher, and the oxide insulating film 18 is reduced.

Note that a barrier layer can be grown under Blk-W, and in this case also, the oxide film is reduced. At this time, the growth of Blk-W is performed in two stages, and the condition of the first stage is SiH ₄ / WF ₆ = 10/25 sccm, 1064
0 Pa, 450 ° C., the second stage is H ₂ / WF ₆ = 360 /
30 sccm, 10640 Pa, and 450 ° C.

In the above-described example, W is used as the conductor 15, but a metal such as molybdenum (Mo) or aluminum (Al) may be used.

Although the present embodiment has shown the two-layer wiring of the first wiring 11 and the second wiring 13, it can be applied to a three-layer or four-layer wiring.

The second wiring 13 is made of TiON and Al-
Although the example of Si is shown, it is needless to say that the present invention is not limited to this. For example, the lower wiring is W polycide,
The upper layer may have a configuration of Al-Si.

[0034]

As described above, according to the present invention, the connection hole 1
4 is filled with the conductor 15 by, for example, selective CVD, the conductor 15 is deposited and deposited from above the lower first wiring 11 at least at the initial stage of the growth, but the upper wiring facing the connection hole 14 is formed. from the exposed surface of the second wiring 13 it is one that does not cause its precipitation deposited by coating with oxide insulating film 18, then the acid
Its filled state in which the conductor 15 is in direct contact with the exposed surface of the second wiring 13 by removal by reduction of of the insulating film 18
As a result, the conductors 15 are sequentially filled from the bottom of the connection hole 14, so that the generation of voids as described with reference to FIG. 6 can be avoided.

Therefore, highly reliable interconnection between wirings,
A higher degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a main part of a multilayer wiring obtained by a method of the present invention.

FIG. 2 is a process chart (part 1) of an example of the method of the present invention.

FIG. 3 is a process diagram (part 2) of an example of the method of the present invention.

FIG. 4 is a process chart of another example of the method of the present invention.

FIG. 5 is a schematic sectional view of a main part of a multilayer wiring according to a conventional method.

FIG. 6 is a schematic sectional view of a main part showing a problem in a multilayer wiring according to a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 1st wiring 12 Interlayer insulating layer 13 2nd wiring 14 Connection hole 15 Conductor

Claims (1)

(57) [Claims] A first wiring provided on the first wiring via an interlayer insulating layer;
Is formed, and a connection hole formed through the second wiring and the interlayer insulating layer is filled with a conductor to make electrical connection between the first wiring and the second wiring. In the method for forming a multilayer wiring to be performed, an oxide insulating film is formed on an exposed surface of the second wiring facing the inner peripheral surface of the connection hole after the formation of the connection hole, and then the conductor is inserted into the connection hole. A method for forming a multilayer wiring, comprising reducing the oxide insulating film during filling.