JPH0590412A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and manufacturing method thereof which can form an antifuse in a via hole even if the via hole is miniaturized with regard to the structure and the manufacturing method of the antifuse formed in an integrated circuit. CONSTITUTION:This device is constituted so as to include the following parts. A first interconnection layer 8 is formed on a substrate 7. An interlayer insulating film 9 is formed by coating the first interconnection layer 8. A via hole 10 is formed in the interlayer insulating film on the first interconnection layer 8. An embedded conductor 11 containing high-melting-point metal is embedded in the via hole 10 in contact with the first interconnection layer 8 at the bottom part of the via hole 10. An amorphous semiconductor layer 12a is formed so as to cover the embedded conductor 11 in contact with the embedded layer conductor 11. A second interconnection layer 31 is formed on the amorphous semiconductor layer 12a.

Description

Detailed Description of the Invention

(Table of Contents) -Industrial field of application-Conventional technology (Fig. 7) -Problems to be solved by the invention-Means for solving the problems-Actions-Examples (1) First aspect of the present invention Embodiment (FIGS. 1 and 2) (2) Second embodiment of the present invention (FIG. 3) (3) Third embodiment of the present invention (FIGS. 4 to 6)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device structure and manufacturing method of an antifuse formed in an integrated circuit.

An antifuse that changes from a high resistance state to a low resistance state by a write operation is an FPGA (Field Programmable Grate Arra) having a scale of several thousand gates or more.
formed in an integrated circuit to form a logic cell of a user programmable logic device such as y) or a memory cell of a PROM.

In recent years, there is a strong demand for high integration and high speed for logic devices such as FPGAs.

[0005]

2. Description of the Related Art FIG. 7 shows an example of a semiconductor logic integrated circuit device including a conventional antifuse. In this example, an amorphous semiconductor layer as an antifuse is sandwiched between a first wiring layer and a second wiring layer on a semiconductor substrate.

In FIG. 7, 1 is a base insulating film on a semiconductor substrate (not shown), 24 is a first wiring layer on the base insulating film 1, a barrier conductive film 3 made of a TiW film is formed on the upper layer, and a lower layer is formed. A conductor layer 2 made of an alloy of Al and Si, Cu, Ti, or the like is formed on the surface of. Reference numeral 26 is an interlayer insulating film that covers the first wiring layer 24, 27 is a via hole formed in the interlayer insulating film 4 on the first wiring layer 24, 4 is a via hole 27, and the first hole at the bottom of the via hole 27. 1 is an amorphous silicon film selectively formed in contact with the wiring layer 24, 5 is a barrier conductive film made of a TiW film covering the amorphous silicon film 4, and 6 is formed on the barrier conductive film 5. , A conductor layer made of an Al alloy film containing Si, Cu, or Ti, and the barrier conductive film 5 and the conductor layer 6 constitute the second wiring layer 25.

[0007]

In the above example, the conductor layer 6 of the second wiring layer 25 is thin on the side wall of the via hole 27. That is, the film thickness a shown in the figure is
It is smaller than the film thickness b at the flat portion. If the width c of the via hole 27 is 1.0 μm, then a / b =
About 0.3, that is, the step coverage (coverage rate) is about 30%. Further, when the width c is 0.8 μm or less, the step coverage is further reduced, and the conductor layer 6 may be interrupted.

Thus, when the width c becomes less than about 1.0 μm, the second wiring layer 25 formed by the sputtering method.
Reliability is significantly reduced. Even if there is no discontinuity, the step coverage is small, resulting in a wiring having a small electromigration resistance. For this reason,
The conventional technique has a problem that the antifuse cannot be formed in the via hole 27 formed by the submicron rule.

The present invention has been made in view of the above problems, and provides a semiconductor device capable of forming an antifuse in a via hole even when the via hole is miniaturized, and a manufacturing method thereof. To aim.

[0010]

The first object of the present invention is to provide a first wiring layer formed on a substrate, an interlayer insulating film formed by covering the first wiring layer, and A via hole formed in the interlayer insulating film on the first wiring layer, an embedded conductor containing a refractory metal embedded in the via hole, in contact with the first wiring layer at the bottom of the via hole, and the embedded conductor. And a second wiring layer formed on the amorphous semiconductor layer and an amorphous semiconductor layer formed in contact with the buried conductor and covering the buried conductor, and a second wiring layer formed on the amorphous semiconductor layer. Secondly, the first wiring layer formed on the substrate, the interlayer insulating film formed by covering the first wiring layer, and the interlayer insulating film formed on the first wiring layer. The via hole and the first wiring layer at the bottom of the via hole,
An amorphous semiconductor layer formed by covering the first wiring layer, an embedded conductor containing a refractory metal in contact with the amorphous semiconductor layer and embedded in the via hole, and the embedded conductive layer. And a second wiring layer formed in contact with the body.
In the first wiring layer, the layer in contact with the buried conductor according to the first invention or the layer in contact with the amorphous semiconductor layer according to the second invention is a barrier conductive film containing a refractory metal. A fourth aspect of the invention is achieved by the semiconductor device according to the first or second invention, which is a body layer, and fourthly, the amorphous semiconductor according to the first invention, which is the second wiring layer. The layer in contact with the layer or the layer in contact with the embedded conductor according to the second invention is
This is achieved by the semiconductor device according to the first, second or third invention, which is a barrier conductor layer containing a refractory metal. Fifth, the amorphous semiconductor layer is enhanced by an electrical method. In a method of manufacturing a semiconductor device capable of changing from a resistance state to a low resistance state, a step of forming a first wiring layer on a substrate, and a step of forming an interlayer insulating film on the first wiring layer. A step of forming a via hole in the interlayer insulating film, and a step of forming a buried conductor containing a refractory metal in contact with the first wiring layer at the bottom of the via hole and covering the first wiring layer with the via hole. And a step of forming an amorphous semiconductor layer in contact with the embedded conductor and a step of forming a second wiring layer in contact with the amorphous semiconductor layer. Achieved by a method of manufacturing a semiconductor device And sixth, in a method of manufacturing a semiconductor device capable of transitioning an amorphous semiconductor layer from a high resistance state to a low resistance state by an electrical method, the step of forming a first wiring layer on a substrate, A step of forming an interlayer insulating film on the first wiring layer, a step of forming a via hole in the interlayer insulating film, a step of contacting the first wiring layer at the bottom of the via hole, and the first wiring A layer to form an amorphous semiconductor layer, a step of embedding a buried conductor containing a refractory metal in the via hole in contact with the amorphous semiconductor layer in the via hole, and the buried conductive layer. And a step of forming a second wiring layer in contact with the body.
In the fifth or sixth aspect, the embedded conductor is embedded in the via hole by selectively forming the embedded conductor on the first wiring layer at the bottom of the via hole. Eighth achieved by the method for manufacturing a semiconductor device according to the present invention. Eighth, a conductive film is formed on the entire surface by a chemical vapor deposition (CVD) method, and then etched back to remove the embedded conductor into the via hole. A fifth aspect of the present invention, which is achieved by the method of manufacturing a semiconductor device according to the fifth or sixth aspect of the present invention, characterized in that the step of annealing the amorphous semiconductor layer is performed. This is achieved by the method for manufacturing a semiconductor device according to the sixth, seventh or eighth invention.

[0011]

[Operation] According to the semiconductor device and the method for manufacturing a semiconductor device of the present invention, since the buried conductor is buried in the via hole for connecting the first and second wiring layers,
There is almost no step that must be covered by the wiring layer. Therefore, regardless of the size of the via hole opening width,
Since the coverage rate of the second wiring layer can always be kept at about 80% or more, the discontinuity or the like of the second wiring layer due to the conventional step does not occur. This makes it possible to form an amorphous semiconductor layer as an antifuse between the first and second wiring layers through the via hole formed in the submicron rule or the half micron rule or less.

Particularly, since the buried conductor is a conductor interposed between the first or second wiring layer and the amorphous semiconductor layer and containing a refractory metal, the first or second wiring layer is formed. Mutual diffusion between the amorphous semiconductor layer and the amorphous semiconductor layer can be prevented. Therefore, the antifuse can be stably formed in the manufacturing process.

Further, by annealing the amorphous semiconductor layer, it is possible to reduce the leakage current in the high resistance state between the first and second wirings.

[0014]

Embodiments (1) First Embodiment FIGS. 1A to 1C and 2D to 2F are sectional views for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. It is a figure.

First, S is sputtered on a substrate 7 consisting of a semiconductor substrate and a base insulating film on the semiconductor substrate.
After forming an Al alloy film containing i, Cu or Ti and having a film thickness of about 0.5 μm, patterning is performed to form the first wiring layer 8. Then, by a CVD method or the like, a P
After forming the interlayer insulating film 9 made of the SG film, a resist film (not shown) is patterned to form a resist pattern. Interlayer insulating film 9 using this resist pattern as a mask
Is etched to form a via hole 10 having an opening width of about 0.5 μm on the first wiring layer 8 (FIG. 1A).

Next, the via hole 1 is selectively formed on the first wiring layer 8 at the bottom of the via hole 10 by the CVD method using a reaction gas containing a halide of W such as WF _6.
An embedding member 11 is embedded in 0 (FIG. 1 (b)).

Next, an amorphous silicon layer (amorphous semiconductor layer) 12 having a film thickness of about 1000 Å is formed on the entire surface. by the way,
As the method, there are a CVD method and a sputtering method.
In the case of the CVD method, the amorphous silicon layer 12 is grown by a reduction reaction of SiH ₄ (silane) or Si ₂ H ₆ (disilane), and the growth temperature is preferably 400 to 500 ° C. In the case of the sputtering method, the amorphous silicon layer 12 is formed by sputtering a target made of silicon with Ar or the like.

Next, the amorphous silicon layer 12 is doped with an impurity of Group III or Group V conductivity type, such as boron, phosphorus, or arsenic, by ion implantation. At this time, the dose of ion implantation is about 10 ¹⁴ to 10 ¹⁶ cm ⁻² , and the implantation energy is such that ion species do not penetrate through the amorphous silicon layer 12 (FIG. 1C). It should be noted that activation annealing of ion species should not be performed after ion implantation. This is because if the heat treatment at about 600 ° C. or higher is applied, the amorphous silicon layer 12 is polycrystallized and the resistance is lowered. In some cases, the amorphous silicon layer 12 may not be doped with conductive impurities.

Next, the amorphous silicon layer 12 formed on the entire surface is patterned by using the photolithography method and the dry etching method, thereby completing the antifuse made of the amorphous silicon layer 12a (see FIG. Two
(D)).

Next, in order to form the second wiring layer 31, first, a TiN film or TiW having a film thickness of about 1000 to 2000Å is formed.
A barrier conductor layer 13 made of a film is deposited on the entire surface by a sputtering method (FIG. 2E). The barrier conductor layer 13 is formed to prevent the amorphous silicon layer 12a from eluting into the conductor layer 14 of the second wiring layer 31.

Next, an Al alloy film containing Si, Cu or Ti and having a film thickness of about 0.5 μm to be the conductor layer 14 is formed on the entire surface. Then, the conductor layer 14 and the barrier conductor layer 13 are simultaneously patterned by using the photolithography method and the etching method, and the second wiring layer 31 including the barrier conductor layer 13 and the conductor layer 14 is formed. Are formed (Fig. 2
(F)).

As described above, in the semiconductor device of the first embodiment of the present invention, the buried conductor 1 is embedded in the via hole 10.
Since 1 is buried, there is almost no step which the second wiring layer 31 has to cover. Therefore, regardless of the size of the opening width of the via hole 10, the second wiring layer 31
Since it is possible to always secure the coverage rate of about 80% or more, the discontinuity or the like of the second wiring layer 31 at the step like the conventional case does not occur. As a result, the first and second wiring layers 8 and 3 are formed through the via holes formed according to the submicron rule or the half micron rule or less.
It becomes possible to form the amorphous silicon layer 12a as an antifuse between the two.

In particular, the buried conductor 11 is the first wiring layer 8
Between the first wiring layer 8 and the amorphous silicon layer 12a, it is possible to prevent mutual diffusion between the first wiring layer 8 and the amorphous silicon layer 12a. .. Therefore, the antifuse can be stably formed in the manufacturing process.

Further, it has been experimentally confirmed that the resistance value in the low resistance state is lower than that in the case where the conductivity type impurity is not introduced, because the conductivity type impurity is introduced into the amorphous silicon layer 12a. Can be made smaller. Further, by annealing the amorphous silicon layer 12a, the leakage current in the high resistance state between the first and second wirings can be reduced. As described above, it is possible to comprehensively improve the electrical characteristics of the semiconductor device.

Next, a method of using the antifuse formed as described above will be described. In the initial state, the resistance value of the antifuse between the first wiring layer 8 and the second wiring layer 31 is as high as about 100 MΩ, which means that the antifuse is substantially open.

Next, in order to conduct the antifuse at a predetermined location, a pulse voltage of about 10 V is applied between the first wiring layer 8 and the second wiring layer 31 where the predetermined antifuse is present. do it. As a result, the crystalline state of the amorphous silicon layer 12a changes to become polysilicon,
The resistance value between the first wiring layer 8 and the second wiring layer 31 is
It becomes as small as 100Ω.

After the pulse voltage is once applied, the resistance value does not decrease and remains approximately 100Ω semipermanently. In other words, it means that the antifuse is written, and the first wiring layer 8 and the second wiring layer 3
1 becomes electrically conductive. In this way, the desired logic can be realized by bringing the antifuses between the wiring layers formed in large numbers in the integrated circuit into conduction.

The electrical characteristics of the antifuse can be controlled as follows, for example, by controlling the conditions for forming the antifuse. That is, if the thickness of the amorphous silicon layer 12a is increased, the writing voltage will be increased. For example, if the film thickness is 1000Å and 10V, 1
At 300Å, it becomes 12V.

If the amorphous silicon layer 12a is doped with impurities, the resistance value after writing becomes small. For example, in the case of undoped 120 Ω, if phosphorus is ion-implanted,
It becomes about 90Ω. The resistance value after writing can be controlled by changing the ion species for ion implantation and the dose amount.

Further, in order to reduce the leakage current in the initial state before writing, it is desirable to anneal at any time after forming the amorphous silicon layer 12a. That temperature is
The temperature is about 250 ° C. to 500 ° C., the time is about 15 to 40 powders, and the atmosphere is nitrogen or oxygen or hydrogen or a mixed atmosphere of nitrogen and hydrogen. By adjusting the annealing conditions, it is possible to reduce the leakage current by about 2 digits. Since the process of forming the integrated circuit usually includes the process of annealing the wafer under the above conditions, it is not necessary to add an additional annealing process.

(2) Second Embodiment FIG. 3 shows a second embodiment of the present invention. The difference from the first embodiment is the structure and material of the second wiring layer.
That is, in the second embodiment, tungsten (W) as a refractory metal is used as the material of the second wiring layer 23. Therefore, as the structure of the second wiring layer 23, the barrier conductor layer 13 of the first embodiment can be omitted. Because the amorphous silicon layer 12a is made of W, the second wiring layer 2
This is because there is no elution in 3.

When forming the second wiring layer 23, after the step of FIG. 2D of the first embodiment, it is formed on the entire surface by the CVD method or the sputtering method, and then the photolithography method and the etching method. Patterning by. Note that the other reference numerals in FIG. 3 are similar to those in FIGS.
2 (d) to 2 (f) are denoted by the same reference numerals as those in FIG. 1 (a).
2 (c) and 2 (d) to 2 (f).

Although W is used as the material of the second wiring layer 23 in the second embodiment, other refractory metal such as molybdenum (Mo) may be used. (3) Third Embodiment FIGS. 4A to 4C, 5D to 5F, and 6G.
[FIG. 6A] is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 6 (g) shows the semiconductor device after the antifuse is formed, but in the first and second embodiments,
While the buried conductor 11 is buried under the amorphous silicon layer 12a, the buried conductor 20 is buried in the third embodiment.
a is embedded on the amorphous silicon layer 19a. That is, in the anti-fuse, the amorphous silicon layer 19 a is formed on the conductor layer 15 on the conductor layer 15 forming the first wiring layer 32 and on the conductor layer 22 forming the second wiring layer 33. That is, the structure is sandwiched between the buried conductor 20a below the barrier conductor layer 21.

The barrier conductor layer 16 is an amorphous silicon layer.
It is necessary to prevent 19a from eluting into the conductor layer 15 made of an Al alloy that forms the first wiring layer 32. The barrier conductor layer 21 is made of an amorphous silicon layer 19a, and the conductor layer 2 is made of an Al alloy that constitutes the second wiring layer 33.
Required to prevent elution into 2.

Next, a manufacturing method for manufacturing the above semiconductor device will be described. First, an Al alloy film with a film thickness of about 0.5 μm and a TiN film with a film thickness of about 1000 ° C. to 2000 Å or T is formed on a base insulating film 7 on a semiconductor substrate (not shown).
An iW film is sequentially formed on the entire surface by a sputtering method, and then patterned by a photolithography method and etching to form a first wiring layer 32.

Next, a film thickness of about 1 μm is formed by the CVD method or the like.
After forming the inter-layer insulating film 17 on the entire surface, a via hole 18 is formed in the inter-layer insulating film 17 on the first wiring layer 32 by photolithography and etching (FIG. 4).
(A)).

Next, an amorphous silicon layer (amorphous semiconductor layer) 19 is formed on the entire surface, and the method follows the method shown in the first embodiment (FIG. 4B). Next, the tungsten (W) film 20 is grown on the entire surface by the CVD method. Here, a blanket growth method (a blanket growth method) by decomposition of WF ₆ is used (FIG. 4C).

Next, the amorphous silicon layer 19 and the W film 20 formed on the entire surface are etched back. That is,
By etching the amorphous silicon layer 19 and the W film 20 for an appropriate time, the amorphous silicon layer 19 and the W film 20 on the interlayer insulating film 17 are completely removed, and the first The amorphous silicon layer 19 and the W film 20 are left in the via hole 18 on the wiring layer 32. As a result, as shown in FIG.
A buried conductor 20a made of the film 20 is buried.

Next, in order to form the second wiring layer 33, first, a barrier conductor layer 21 made of a TiN film or a TiW film having a film thickness of about 1000 ° C. to 2000 Å is formed on the entire surface by a sputtering method. Then, the conductor layer 22
A semiconductor device is completed by forming an Al alloy film having a thickness of about 0.5 μm on the entire surface by sputtering and patterning.

The electrical characteristics of the antifuse thus formed are the same as those shown in the first embodiment. As described above, in the semiconductor device of the third embodiment of the present invention, since the embedded conductor 20a is embedded in the via hole 18, the second wiring layer is formed regardless of the opening width of the via hole 18. Since the coverage rate of 33 can always be maintained at about 80% or more, the disconnection of the second wiring layer 33 due to the step difference as in the conventional case does not occur. As a result, the via hole 1 formed by the sub-micron rule or the half-micron rule or less
It is possible to form the amorphous silicon layer 19a as an anti-fuse between the first and second wiring layers 32 and 33 via the intermediate layer 8.

In particular, since the buried conductor 20a interposed between the second wiring layer 33 and the amorphous silicon layer 19a is a refractory metal made of tungsten, the second wiring layer 33 and the amorphous silicon are not formed. Mutual diffusion with the layer 19a can be prevented. Therefore, the antifuse can be stably formed in the manufacturing process.

Further, by introducing a conductivity type impurity into the amorphous silicon layer 19a, the resistance value in the low resistance state can be reduced. Further, by annealing the amorphous silicon layer 19a, the first and second wiring layers 32 and 3 are formed.
It is possible to reduce the leakage current in the high resistance state between the three. As described above, it is possible to comprehensively improve the electrical characteristics of the semiconductor device.

[0044]

As described above, according to the semiconductor device and the method of manufacturing the semiconductor device of the present invention, the amorphous semiconductor layer and the buried conductor are combined to connect the first and second wiring layers. By forming the anti-fuse in the portion, the coverage ratio of the second wiring layer can be kept good regardless of the opening width of the via hole in the wiring connection portion. Therefore, even if the via hole is formed according to the half-micron rule or the half-micron rule or less, the antifuse can be incorporated therein.

In particular, since the buried conductor is a conductor which is interposed between the first or second wiring layer and the amorphous semiconductor layer and contains a refractory metal, the first or second wiring layer is formed. Mutual diffusion between the amorphous semiconductor layer and the amorphous semiconductor layer can be prevented. Therefore, the antifuse can be stably formed in the manufacturing process.

From the above, according to the present invention, it is possible to manufacture a user programmable logic device such as a highly integrated and high speed FPGA.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view explaining a second embodiment of the present invention.

FIG. 4 is a sectional view (No. 1) for explaining the third embodiment of the present invention.

FIG. 5 is a sectional view (No. 2) for explaining the third embodiment of the present invention.

FIG. 6 is a cross-sectional view (No. 3) explaining the third embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a conventional example.

[Explanation of symbols]

1, 7 substrate, 2, 6 conductor layer, 3, 5, 13, 16, 21 barrier conductor layer, 4 amorphous silicon layer, 8 conductor layer (first wiring layer), 9, 17, 26 Interlayer insulating film, 10, 18, 27 via hole, 11 buried conductor, 12, 12a, 19, 19a Amorphous silicon layer (amorphous semiconductor layer), 14, 15, 22 Conductor layer, 20 Tungsten film, 20a Buried layer, 23, 25, 31, 33 Second wiring layer, 24, 32 First wiring layer.

Claims (9)

[Claims] 1. A first wiring layer formed on a substrate, an interlayer insulating film formed by covering the first wiring layer, and an interlayer insulating film formed on the first wiring layer. A beer hole,
A buried conductor containing a refractory metal embedded in the via hole in contact with the first wiring layer at the bottom of the via hole; and a non-contact layer formed in contact with the buried conductor and covering the buried conductor. A semiconductor device comprising: a crystalline semiconductor film; and a second wiring layer formed on the amorphous semiconductor film. 2. A first wiring layer formed on a substrate, an interlayer insulating film formed to cover the first wiring layer, and an interlayer insulating film formed on the first wiring layer. A beer hole,
An amorphous semiconductor layer formed in contact with the first wiring layer at the bottom of the via hole and covering the first wiring layer, and in contact with the amorphous semiconductor layer and embedded in the via hole A semiconductor device comprising: an embedded conductor containing a refractory metal; and a second wiring layer formed in contact with the embedded conductor. 3. The barrier conductor containing the refractory metal, wherein the first wiring layer is in contact with the buried conductor according to claim 1 or the layer is in contact with the amorphous semiconductor layer according to claim 2. It is a layer, The semiconductor device of Claim 1 or Claim 2 characterized by the above-mentioned. 4. The barrier conductor which is the second wiring layer and which is in contact with the amorphous semiconductor layer according to claim 1 or is in contact with the buried conductor according to claim 2, It is a layer, The semiconductor device of Claim 1, Claim 2, or Claim 3 characterized by the above-mentioned. 5. A method of manufacturing a semiconductor device capable of changing an amorphous semiconductor layer from a high resistance state to a low resistance state by an electrical method, the method comprising: forming a first wiring layer on a substrate; Forming an interlayer insulating film on the first wiring layer; forming a via hole in the interlayer insulating film; contacting the first wiring layer at the bottom of the via hole, and forming the first wiring layer A step of burying a buried conductor containing a refractory metal in the via hole, a step of forming an amorphous semiconductor layer in contact with the buried conductor, and a step of contacting with the amorphous semiconductor layer. And a step of forming a second wiring layer. 6. A method of manufacturing a semiconductor device capable of transitioning an amorphous semiconductor layer from a high resistance state to a low resistance state by an electrical method, the method comprising: forming a first wiring layer on a substrate; Forming an interlayer insulating film on the first wiring layer, forming a via hole in the interlayer insulating film, contacting the first wiring layer at the bottom of the via hole, and forming the first wiring A step of covering the layer to form an amorphous semiconductor layer, a step of contacting the amorphous semiconductor layer in the via hole with an embedded conductor containing a refractory metal in the via hole, and the embedded conductive layer. And a step of forming a second wiring layer in contact with the body, the method for manufacturing a semiconductor device. 7. The embedded conductor is embedded in the via hole by selectively forming the embedded conductor on the first wiring layer at the bottom of the via hole. Alternatively, the method of manufacturing a semiconductor device according to claim 6. 8. The embedded conductor is embedded in the via hole by etching back after forming a conductive film on the entire surface by a chemical vapor deposition (CVD) method. The method for manufacturing a semiconductor device according to claim 6. 9. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of annealing the amorphous semiconductor layer.