JPH04133453A - Lead frame for semiconductor device use - Google Patents

Lead frame for semiconductor device use

Info

Publication number
JPH04133453A
JPH04133453A JP2255627A JP25562790A JPH04133453A JP H04133453 A JPH04133453 A JP H04133453A JP 2255627 A JP2255627 A JP 2255627A JP 25562790 A JP25562790 A JP 25562790A JP H04133453 A JPH04133453 A JP H04133453A
Authority
JP
Japan
Prior art keywords
lead
resin
outer frame
frame
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2255627A
Other languages
Japanese (ja)
Inventor
Kojiro Shibuya
渋谷 幸二郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2255627A priority Critical patent/JPH04133453A/en
Publication of JPH04133453A publication Critical patent/JPH04133453A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make it possible to perform a resin injection in upper and lower resin sealing parts at almost the same time and to make it possible to prevent the generation of an unfilled part by a method wherein an opening part is provided in a part, which is positioned in the vicinity of the resin injection hole of a metal mold, of the outer frame of a lead frame. CONSTITUTION:In a semiconductor lead frame having a die pad 3, inner leads 4, which are provided on the periphery of the pad 3 and are respectively coupled with outer leads by tie bars 5, the outer leads 6, each one end of which is connected to each inner lead 4 and the other ends of which are connected to an outer frame 1, and suspension leads 7, each one end of which is connected to each corner part of the pad 3 and the other ends of which are connected to the outer frame 1, a semiconductor pellet 11 is mounted on the pad 3 and thereafter, an opening part 10 is provided in a part, which is positioned in the vicinity of a resin injection hole of a metal mold, of the outer frame of the above lead frame, which is resin-sealed by the metal mold. For example, the above suspension leads 7 are respectively branched into a branch suspension lead 8 from their middles, the branch lead 8 is led out in parallel to the leads 6 from the vicinities of parts, which avoid a chamfering part 9, of a resin-sealing part 2 and is connected to an outer frame 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関し、特に樹脂
封止型半導体装置用のリードフレームに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and particularly to a lead frame for a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来この種のリードフレームにおいては、第4図に示す
ように、リードフレームのダイハツト3とインナーリー
ド4を含む領域に形成される樹脂封止部2の面取り部9
、いわゆる樹脂封止部2を形成する金型の樹脂注入口付
近のリードフレームの外枠1の内面部は、面取り部9か
られずか0.1mmから0.15mm離れたところに位
置し、ダイパッド3を支持する吊りビン18の1つがダ
イパッド3のコーナーから樹脂封止部2の面取り部9へ
突出し、樹脂注入口付近の外枠1に接続された構造とな
っていた。そのため従来のリードフレーム用の樹脂封止
用の金型においては、下型あるいは上型にのみ樹脂注入
用のランナーやゲート口が設けられ、樹脂封止部2内へ
の樹脂注入が下型あるいは上型からのみ行われる構造に
なっていた。
Conventionally, in this type of lead frame, as shown in FIG.
The inner surface of the outer frame 1 of the lead frame near the resin injection port of the mold forming the so-called resin sealing part 2 is located at a distance of 0.1 mm to 0.15 mm from the chamfered part 9, and the die pad One of the hanging bottles 18 supporting the die pad 3 protruded from the corner of the die pad 3 to the chamfered part 9 of the resin sealing part 2, and was connected to the outer frame 1 near the resin injection port. Therefore, in conventional molds for resin sealing lead frames, runners and gate ports for resin injection are provided only in the lower mold or the upper mold, and the resin injection into the resin sealing part 2 is performed only in the lower mold or the upper mold. The structure was such that it could only be done from the upper mold.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

半導体装置の動向として、多ピン化、小型化の傾向があ
る。限られたスペースに数多くのリードを設ける必要が
あるため、従来のインナーリートの幅やインナーリード
とインナーリードの間隔はさらに加工限界近くまで縮小
されてきている。このような多ビン対応の従来のリード
フレームでの樹脂封止においては、通常樹脂封止部2の
コーナー下部に設けられる金型の樹脂注入口から注入さ
れる溶融樹脂か、各インナーリード4間のすきまが小さ
いために、リードフレーム上部の樹脂封止部に注入され
に<<、樹脂封止部の下部と上部へ充填される時間に大
きな差がでて最終的には、上部あるいは下部の樹脂封止
部の表面に未充填部が発生するなど成形性を損なう欠点
があった。
The trend in semiconductor devices is toward increasing the number of pins and downsizing. Because it is necessary to provide a large number of leads in a limited space, the width of conventional inner leads and the spacing between inner leads have been further reduced to near processing limits. In resin sealing with conventional lead frames compatible with multiple bins, molten resin is usually injected from the resin injection port of the mold provided at the lower corner of the resin sealing part 2, or the molten resin is injected between each inner lead 4. Because the gap is small, the resin is injected into the resin sealing part at the top of the lead frame, and there is a large difference in the time it takes to fill the bottom and top of the resin sealing part. There were drawbacks such as the occurrence of unfilled areas on the surface of the resin-sealed portion, which impairs moldability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のリードフレームは、タイバ・ンドと、このダイ
パッドの周囲に設けられかつタイバーにより連結された
インナーリードと、一端がこのインナーリードに接続さ
れ他端が外枠に接続されたアウターリートと、一端が前
記ダイパッドのコーナー部に接続され他端が前記外枠に
接続それた吊りリードとを有する半導体装置用リードフ
レームにおいて、前記ダイパッドに半導体ペレ・ントを
搭載したのち金型により樹脂封止される前記リードフレ
ームの前記金型の樹脂注入口付近に位置する前記外枠に
開口部を設けたものである。
The lead frame of the present invention includes a tie bar, an inner lead provided around the die pad and connected by a tie bar, and an outer lead having one end connected to the inner lead and the other end connected to the outer frame. In a lead frame for a semiconductor device having a suspension lead having one end connected to a corner portion of the die pad and the other end connected to the outer frame, a semiconductor pellet is mounted on the die pad and then resin-sealed with a mold. An opening is provided in the outer frame located near the resin injection port of the mold of the lead frame.

〔実施例〕〔Example〕

次に本発明について図面を用いて詳細に説明する。 Next, the present invention will be explained in detail using the drawings.

第1図は本発明の第1の実施例を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.

第1図において、複数のインナーリード4はグイパッド
3周辺に配置され、樹脂封止部2の周囲でタイバー5で
各々連結されている。インナーリード4の延長上にある
アウターリード6とタイバー5は、リードフレーム外枠
1に延長接続されている。また、ダイパッド3の4つの
コーナーには吊りリード7の一端が接続され、その他端
は、途中から分岐リード8に分岐し、樹脂封止部2の面
取り部9を避けた近傍からアウターリード6に平行して
導出されリードフレームの外枠lに接続されている。
In FIG. 1, a plurality of inner leads 4 are arranged around the guide pad 3 and connected around the resin sealing part 2 with tie bars 5. Outer leads 6 and tie bars 5, which are on extensions of the inner leads 4, are extended and connected to the lead frame outer frame 1. Also, one end of the suspension lead 7 is connected to the four corners of the die pad 3, and the other end branches into a branch lead 8 from the middle, and connects to the outer lead 6 from the vicinity avoiding the chamfered part 9 of the resin sealing part 2. It is led out in parallel and connected to the outer frame l of the lead frame.

さらに、樹脂封止部2の面取り部9の近傍の外枠1には
開口部10が設けられている。通常、面取り部9には樹
脂封止のための金型の樹脂注入口が設けられるが、この
開口部10は樹脂注入口が設けられる部位の近傍に限定
して設けられる。
Furthermore, an opening 10 is provided in the outer frame 1 near the chamfered portion 9 of the resin sealing portion 2 . Usually, a resin injection port of a mold for resin sealing is provided in the chamfered portion 9, but this opening 10 is provided only in the vicinity of the portion where the resin injection port is provided.

開口部10の幅Aは、樹脂注入口の幅よりも約0.2m
l!l程度大きくした方がよい。本発明は開口部10の
形状や大きさに限定されるものではない。
The width A of the opening 10 is approximately 0.2 m wider than the width of the resin injection port.
l! It is better to make it larger by about l. The present invention is not limited to the shape or size of the opening 10.

次にこのように構成された本実施例を用い、ダイパッド
3に半導体ペレットを固定し、樹脂封止金型で樹脂封止
した半導体装置の断面図を第2図に示す。第2図におい
て、ダイパッド3に搭載された半導体ペレット11のホ
ンディングパッドとインナーリード4の先端はワイヤー
12で接続されている。
Next, FIG. 2 shows a cross-sectional view of a semiconductor device in which a semiconductor pellet is fixed to the die pad 3 and resin-sealed with a resin-sealing mold using this embodiment configured as described above. In FIG. 2, the bonding pad of the semiconductor pellet 11 mounted on the die pad 3 and the tip of the inner lead 4 are connected by a wire 12.

リードフレームの外枠lの下面の一部には、金型の下部
ランナー16が位置し下部ゲート口15を介して樹脂封
止部2と接続している。また開口部10の上部には金型
の上部ランナー14が位置し、上部ゲート口13を介し
て樹脂封止部2と接続している。つまり、下部ランナー
16と上部ランナー14は、開口部10が設けであるた
めに一体化されている。上部ランナー14及び上部ゲー
ト口13を図示していない樹脂封止金型の上型に形成す
ることは全く容易である。以上のことから、樹脂封入時
に下部ランナー16から注入されてきた溶融樹脂の一部
は、下部ゲート口15から、そして他の溶融樹脂は開口
部10を通り、上部ランナー14を経て上部ゲート口1
3から、樹脂封止部2へ樹脂注入が可能になる。従って
従来のように樹脂封止部2に未充填部が発生することは
なくなる。
A lower runner 16 of the mold is located on a part of the lower surface of the outer frame l of the lead frame, and is connected to the resin sealing part 2 via the lower gate opening 15. Further, an upper runner 14 of the mold is located above the opening 10 and is connected to the resin sealing part 2 via the upper gate opening 13. That is, the lower runner 16 and the upper runner 14 are integrated because the opening 10 is provided. It is quite easy to form the upper runner 14 and the upper gate opening 13 in the upper mold of a resin sealing mold (not shown). From the above, some of the molten resin injected from the lower runner 16 during resin sealing flows through the lower gate opening 15, and the other molten resin passes through the opening 10, passes through the upper runner 14, and passes through the upper gate opening 15.
3, resin can be injected into the resin sealing part 2. Therefore, unlike in the conventional case, unfilled portions do not occur in the resin sealing portion 2.

第3図は本発明の第2の実施例の平面図である。第3図
において開口部17は、金型の下部ランナーが位置する
部位に設けられ、リードフレームの外周に至っている。
FIG. 3 is a plan view of a second embodiment of the invention. In FIG. 3, the opening 17 is provided at a portion of the mold where the lower runner is located, and extends to the outer periphery of the lead frame.

この第2の実施例を用いた場合ては、リードフレームの
外枠1に位置する金型の下部ランナーと上部ランナーの
長さを同しにすることにより、樹脂封入時、樹脂注入口
付近での空気の巻き込みをなくすことができる。また、
上部、下部ランナーがリードフレームに接する面積が小
さくなるため、樹脂封止後、リードフレームから不要の
上部、下部ランナ一部の樹脂を除去しやすいという利点
がある。
When this second embodiment is used, by making the length of the lower runner and the upper runner of the mold located on the outer frame 1 of the lead frame the same, it is possible to air entrainment can be eliminated. Also,
Since the area in which the upper and lower runners contact the lead frame becomes smaller, there is an advantage that it is easier to remove unnecessary resin from parts of the upper and lower runners from the lead frame after resin sealing.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、樹脂封入時に用いる金型
の樹脂注入口が位置する付近の外枠に開口部を設けるこ
とにより、金型の上型にも上部ランナー及び上部ゲート
口を設けることができ、樹脂封止部へ上部ゲート口及び
下部ゲート口の両方から樹脂注入することが可能である
。そのため、超多ビンのように、インナーリード幅や各
インナーリード間の間隙が狭いリードフレーム、また低
熱抵抗対応の超大型アイランドを有するリードフレーム
においては、上部及び下部の樹脂封止部にほぼ同時に樹
脂注入ができ、従来問題であった未充填部の発生を防止
できる効果がある。また、樹脂封止部のゲート口方面に
向って吊りリードか途中で分岐し、面取り部つまりゲー
ト口を避けて位置し、ゲート幅が最大になるよう設けら
れるため、最適な樹脂注入速度を選定しやすいという効
果もある。
As explained above, the present invention provides an opening in the outer frame of the mold used for resin injection near where the resin injection port is located, and also provides an upper runner and an upper gate in the upper die of the mold. It is possible to inject resin into the resin sealing part from both the upper gate port and the lower gate port. Therefore, in lead frames with narrow inner lead widths and narrow gaps between inner leads, such as ultra-high-volume bins, and lead frames with ultra-large islands that support low thermal resistance, the upper and lower resin sealing parts are sealed almost simultaneously. It allows resin injection and has the effect of preventing the occurrence of unfilled areas, which has been a problem in the past. In addition, the hanging lead branches toward the gate opening of the resin sealing part and is positioned to avoid the chamfered part, that is, the gate opening, so that the gate width is maximized, so the optimal resin injection speed can be selected. It also has the effect of being easy to do.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の平面図、第2図は第1
の実施例を用いて樹脂封止した場合の断面図、第3図は
本発明の第2の実施例の平面図、第4図は従来の半導体
装置用リードフレームの平面図である、 1・・・外枠、2・・・樹脂封止部、3・・・ダイパッ
ド、4・・・インナーリード、5・・・タイバー、6・
・・アウターリード、7・・・吊りリード、8・・・分
岐吊りリード、9・・・面取り部、10・・・開口部、
11・・・半導体ペレット、12・・・ワイヤー、13
・・・上部ゲート口、14・・上部ランナー、15・・
・下部ゲート口、16・・・下部ランナー、17・・・
開口部。
FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is a plan view of the first embodiment of the present invention.
3 is a plan view of the second embodiment of the present invention, and FIG. 4 is a plan view of a conventional lead frame for a semiconductor device.1. ... Outer frame, 2... Resin sealing part, 3... Die pad, 4... Inner lead, 5... Tie bar, 6...
... Outer lead, 7... Hanging lead, 8... Branch hanging lead, 9... Chamfered part, 10... Opening part,
11... Semiconductor pellet, 12... Wire, 13
...Top gate opening, 14...Top runner, 15...
・Lower gate opening, 16...Lower runner, 17...
Aperture.

Claims (1)

【特許請求の範囲】 1、ダイパッドと、このダイパッドの周囲に設けられか
つタイバーにより連結されたインナーリードと、一端が
このインナーリードに接続され他端が外枠に接続された
アウターリードと、一端が前記ダイパッドのコーナー部
に接続され他端が前記外枠に接続された吊りリードとを
有する半導体装置用リードフレームにおいて、前記ダイ
パッドに半導体ペレットを搭載したのち金型により樹脂
封止される前記リードフレームの、前記金型の樹脂注入
口付近に位置する前記外枠に開口部を設けたことを特徴
とする半導体装置用リードフレーム。 2、ダイパッドを支持する吊りピンの一端が二股に分か
れ外枠に接続されている請求項1記載の半導体装置用リ
ードフレーム。
[Claims] 1. A die pad, an inner lead provided around the die pad and connected by a tie bar, an outer lead having one end connected to the inner lead and the other end connected to an outer frame; in a lead frame for a semiconductor device having a hanging lead connected to a corner portion of the die pad and the other end connected to the outer frame, the lead being sealed with resin by a mold after a semiconductor pellet is mounted on the die pad. A lead frame for a semiconductor device, characterized in that an opening is provided in the outer frame of the frame located near the resin injection port of the mold. 2. The lead frame for a semiconductor device according to claim 1, wherein one end of the hanging pin supporting the die pad is bifurcated and connected to the outer frame.
JP2255627A 1990-09-26 1990-09-26 Lead frame for semiconductor device use Pending JPH04133453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2255627A JPH04133453A (en) 1990-09-26 1990-09-26 Lead frame for semiconductor device use

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2255627A JPH04133453A (en) 1990-09-26 1990-09-26 Lead frame for semiconductor device use

Publications (1)

Publication Number Publication Date
JPH04133453A true JPH04133453A (en) 1992-05-07

Family

ID=17281380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2255627A Pending JPH04133453A (en) 1990-09-26 1990-09-26 Lead frame for semiconductor device use

Country Status (1)

Country Link
JP (1) JPH04133453A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232195A (en) * 1993-01-28 1994-08-19 Rohm Co Ltd Manufacture of semiconductor device and lead frame
JPH08227961A (en) * 1995-02-21 1996-09-03 Nec Kyushu Ltd Lead frame for semiconductor device and its manufacture
US7019388B2 (en) * 2002-12-26 2006-03-28 Renesas Technology Corp. Semiconductor device
CN102097734A (en) * 2009-12-14 2011-06-15 昆山均瑞电子科技有限公司 Method for manufacturing flat connector terminals
JP2013183054A (en) * 2012-03-02 2013-09-12 Renesas Electronics Corp Manufacturing method of semiconductor device and semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60121750A (en) * 1984-07-25 1985-06-29 Hitachi Ltd Lead frame
JPS60138949A (en) * 1983-12-26 1985-07-23 Toshiba Corp Lead frame for semiconductor device
JPS6113952B2 (en) * 1980-09-20 1986-04-16 Erunsuto Bintaa Unto Zoon

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113952B2 (en) * 1980-09-20 1986-04-16 Erunsuto Bintaa Unto Zoon
JPS60138949A (en) * 1983-12-26 1985-07-23 Toshiba Corp Lead frame for semiconductor device
JPS60121750A (en) * 1984-07-25 1985-06-29 Hitachi Ltd Lead frame

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232195A (en) * 1993-01-28 1994-08-19 Rohm Co Ltd Manufacture of semiconductor device and lead frame
JPH08227961A (en) * 1995-02-21 1996-09-03 Nec Kyushu Ltd Lead frame for semiconductor device and its manufacture
US7019388B2 (en) * 2002-12-26 2006-03-28 Renesas Technology Corp. Semiconductor device
CN102097734A (en) * 2009-12-14 2011-06-15 昆山均瑞电子科技有限公司 Method for manufacturing flat connector terminals
JP2013183054A (en) * 2012-03-02 2013-09-12 Renesas Electronics Corp Manufacturing method of semiconductor device and semiconductor device

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