JP2834990B2 - Structure of lead frame for quad type semiconductor device - Google Patents
Structure of lead frame for quad type semiconductor deviceInfo
- Publication number
- JP2834990B2 JP2834990B2 JP27411793A JP27411793A JP2834990B2 JP 2834990 B2 JP2834990 B2 JP 2834990B2 JP 27411793 A JP27411793 A JP 27411793A JP 27411793 A JP27411793 A JP 27411793A JP 2834990 B2 JP2834990 B2 JP 2834990B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead terminals
- semiconductor chip
- suspension
- suspension leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップに対する
多数本の外部リード端子を、前記半導体チップに対する
合成樹脂製のモールドパッケージ部における四つの側面
から突出するようにしたいわゆるクワッド型半導体装置
において、その製造に際して使用するリードフレームの
構造に関するものである。BACKGROUND OF THE INVENTION The present invention relates to a so-called quad type semiconductor device in which a large number of external lead terminals for a semiconductor chip are projected from four sides of a synthetic resin mold package portion for the semiconductor chip. The present invention relates to a structure of a lead frame used in the manufacture thereof.
【０００２】[0002]
【従来の技術】この種のクワッド型半導体装置に使用す
る従来におけるリードフレームは、例えば、特開昭６０
−１２１７４７号公報等に記載され、且つ、図３及び図
４に示すように構成している。すなわち、リードフレー
ム１に、その略中央部にアイランド部２を、当該アイラ
ンド部における四隅部から放射状に一体的に延びる四本
の吊りリード３ａ，３ｂ，３ｃ，３ｄを介して一体的に
連接した状態で形成すると共に、前記各吊りリード３
ａ，３ｂ，３ｃ，３ｄの間の部分に多数本のリード端子
４を、当該各リード端子４が前記アイランド部２に向か
って放射状に延びるように一体的に造形すると言う構造
にしている。2. Description of the Related Art A conventional lead frame used for this kind of quad type semiconductor device is disclosed in, for example,
It is described in, for example, Japanese Unexamined Patent Publication No. 121747, and is configured as shown in FIGS. That is, the island portion 2 is connected to the lead frame 1 at the substantially central portion thereof through four suspension leads 3a, 3b, 3c, 3d which extend radially and integrally from the four corners of the island portion. And each of the suspension leads 3
A large number of lead terminals 4 are formed integrally at portions between a, 3b, 3c, and 3d so that each of the lead terminals 4 extends radially toward the island portion 2.
【０００３】また、このリードフレーム１を使用して、
半導体装置を製造するに際しては、前記アイランド部２
に半導体チップ５をダイボンディングし、次いで、この
半導体チップ５における各電極と前記各リード端子４に
おける先端との相互間を、細い金属線６にてワイヤボン
ディングしたのち、前記半導体チップ５及び各リード端
子４の先端部を、合成樹脂製のモールドパッケージ部７
にてパッケージするようにしている。Also, using this lead frame 1,
When manufacturing a semiconductor device, the island 2
Then, a semiconductor chip 5 is die-bonded, and then each electrode of the semiconductor chip 5 and each of the lead terminals 4 are connected.
Between each other and tip definitive, after wire bonding with a thin metal wire 6, the semiconductor chip 5 and the tips of the lead terminals 4, made of synthetic resin mold package 7
It is packaged at.
【０００４】[0004]
【発明が解決しようとする課題】ところで、このリード
フレーム１において、各吊りリード３ａ，３ｂ，３ｃ，
３ｄの間に配設する各リード端子４の先端の相互間に
は、当該各リード端子４の形成及び金属線６によるワイ
ヤボンディングを可能とするために、所定以上のピッチ
間隔Ｐを確保することが必要であるから、前記各リード
端子４の先端を結ぶ線を、図示のように、前記半導体チ
ップ５における外周側面と略平行にした形態のままで、
前記吊りリード３ａ，３ｂ，３ｃ，３ｄの間に配設する
各リード端子４を多くするには、各リード端子４の先端
から半導体チップ５の電極までの距離Ｓ、換言すると、
各リード端子４の先端を半導体チップ５の電極から離す
距離Ｓを大きくしなければならないことにより、各リー
ド端子４の先端と半導体チップ５の電極とを接続する金
属線５のうち、前記各吊りリード３ａ，３ｂ，３ｃ，３
ｄの左右両側に隣接する付近のリード端子４に対する金
属線５における長さが大幅に長くなるのである。By the way, in this lead frame 1, each of the suspension leads 3a, 3b, 3c,
In order to enable the formation of each lead terminal 4 and the wire bonding with the metal wire 6, a pitch interval P equal to or greater than a predetermined value is secured between the tips of the respective lead terminals 4 disposed between 3d. Therefore, the line connecting the tips of the lead terminals 4 is substantially parallel to the outer peripheral side surface of the semiconductor chip 5 as shown in the drawing.
In order to increase the number of lead terminals 4 arranged between the suspension leads 3a, 3b, 3c, 3d, the distance S from the tip of each lead terminal 4 to the electrode of the semiconductor chip 5, in other words,
Since the distance S at which the tip of each lead terminal 4 is separated from the electrode of the semiconductor chip 5 must be increased, each of the metal wires 5 connecting the tip of each lead terminal 4 and the electrode of the semiconductor chip 5 has a corresponding one of the suspensions. Leads 3a, 3b, 3c, 3
The length of the metal wire 5 with respect to the adjacent lead terminals 4 on both the left and right sides of d is greatly increased.
【０００５】一方、前記半導体チップ５及び各リード端
子４の先端部をパッケージする合成樹脂製のモールドパ
ッケージ部７を成形するに際しては、当該モールドパッ
ケージ部７における一つの隅部に、溶融合成樹脂注入用
のゲート８を開口し、このゲート８から溶融合成樹脂
を、矢印Ａで示すように、高い圧力で注入することが一
般的に行われる。On the other hand, when molding the semiconductor chip 5 and the mold package 7 made of synthetic resin for packaging the leading end of each lead terminal 4, the corner portion of one of definitive to the molded package section 7, molten synthetic In general, a gate 8 for resin injection is opened, and molten synthetic resin is injected from the gate 8 at a high pressure as indicated by an arrow A.
【０００６】従って、従来のように、各リード端子４の
先端と半導体チップ５とを接続する金属線５のうち、前
記各吊りリード３ａ，３ｂ，３ｃ，３ｄの左右両側に隣
接する付近のリード端子４に対する金属線５における長
さが大幅に長くなると言う構成であると、前記各吊りリ
ード３ａ，３ｂ，３ｃ，３ｄのうち前記溶融合成樹脂の
注入方向Ａと直角方向に延びる左右両吊りリード３ｂ，
３ｄにおける左右両側に隣接する付近の金属線５が、当
該金属線の長さが前記のように長いことにより、ゲート
８から矢印Ａの方向に高い圧力で注入される溶融合成樹
脂の流れに押されて大きく湾曲変形して、これに隣接の
金属線５に対して接近又は接触することが多発するので
ある。Accordingly, as in the prior art, among the metal wires 5 for connecting the tip and the semiconductor chip 5 of the lead terminals 4, each suspension lead 3a, 3b, 3c, leads in the vicinity adjacent to the left and right sides of the 3d If the configuration is such that the length of the metal wire 5 with respect to the terminal 4 is greatly increased, both the left and right suspension leads 3a, 3b, 3c, 3d extend in the direction perpendicular to the injection direction A of the molten synthetic resin. 3b,
3d, the metal wires 5 adjacent to the left and right sides are pressed against the flow of the molten synthetic resin injected from the gate 8 at a high pressure in the direction of arrow A due to the long length of the metal wires as described above. As a result, the metal wire 5 is greatly bent and deformed, and often approaches or contacts the metal wire 5 adjacent thereto.
【０００７】つまり、従来におけるリードフレームの構
造では、モールドパッケージ部７を成形するに際して、
各金属線５の相互間に、当該金属線５の変形によってシ
ョートが多発することになるから、不良品の発生率が高
いと言う問題があった。本発明は、この問題の発生を確
実に低減できるようにしたリードフレームの構造を提供
することを技術的課題とするものである。That is, in the conventional lead frame structure, when molding the mold package portion 7,
A short circuit frequently occurs between the metal wires 5 due to the deformation of the metal wires 5, so that there is a problem that the incidence of defective products is high. An object of the present invention is to provide a lead frame structure capable of reliably reducing the occurrence of this problem.
【０００８】[0008]
【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「略中央部に半導体チップを搭載する
アイランド部を、当該アイランド部における四隅部又は
四隅部に近い部位から放射状に一体的に延びる四本の吊
りリードを介して一体的に連接した状態で形成すると共
に、前記各吊りリードの間の部分に多数本のリード端子
を、当該各リード端子が前記アイランド部に向かって放
射状に延びるように一体的に造形して成るリードフレー
ムにおいて、前記各吊りリード間に位置する各リード端
子における先端を結ぶ線を、当該各リード端子の先端か
ら前記半導体チップの電極までの距離が前記吊りリード
に隣接する箇所において最も小さく吊りリードから離れ
るにつれて次第に大きくなるように傾斜する。」と言う
構成にした。In order to achieve this technical object, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: "arranging an island portion on which a semiconductor chip is mounted at a substantially central portion from four corners or a portion near the four corners of the island portion; In addition to being formed in a state of being integrally connected via four suspension leads extending integrally, a large number of lead terminals are provided between the suspension leads, and each of the lead terminals is directed toward the island portion. In a lead frame integrally formed so as to extend radially, a line connecting the tips of the respective lead terminals located between the respective suspension leads is formed such that the distance from the tip of the respective lead terminal to the electrode of the semiconductor chip is reduced. was constituted say gradually increased so as to be inclined. "moves away from the smallest suspension leads at a location adjacent to the suspension lead.
【０００９】[0009]
【作 用】このように構成することにより、各吊りリ
ード間に位置する各リード端子の本数を多くした場合に
おいても、この各リード端子の先端の相互間に、各吊り
リード間に位置する各リード端子における先端を結ぶ線
を傾斜したことで、所定以上のピッチ間隔を確保するこ
とができる。[Operation] With this configuration, even when the number of lead terminals located between the suspension leads is increased, each of the lead terminals located between the suspension leads is located between the tips of the lead terminals. By inclining the lines connecting the tips of the lead terminals, it is possible to secure a predetermined pitch interval or more.
【００１０】これに加えて、前記各リード端子における
先端を結ぶ線を傾斜するに際して、当該各リード端子の
先端から前記半導体チップの電極までの距離を、前記吊
りリードに隣接する箇所において最も小さく吊りリード
から離れるにつれて次第に大きくなるように構成したこ
とにより、各リード端子の先端の相互間に、所定以上の
ピッチ間隔を確保した状態で、各吊りリードの左右両側
に隣接する付近のリード端子に対する金属線における長
さを大幅に短くすることができるのである。[0010] In addition, when tilting the line connecting the tips of the respective lead terminals, the distance from the tip of each of the lead terminals to the electrodes of said semiconductor chip, hanging minimum at locations adjacent to the suspension lead With a configuration in which the pitch gradually increases as the distance from the lead is increased , a predetermined pitch interval or more is secured between the tips of the lead terminals, and the metal for the nearby lead terminals adjacent to the left and right sides of each suspension lead is secured. The length of the line can be greatly reduced.
【００１１】[0011]
【発明の効果】従って、本発明によると、モールドパッ
ケージ部の成形に際して、当該モールドパッケージ部に
おける一つの隅角部から注入する溶融合成樹脂によっ
て、各吊りリードのうち前記溶融合成樹脂の注入方向と
直角方向に延びる左右両吊りリードにおける左右両側に
隣接する付近の金属線が湾曲変形することを、当該金属
線の長さが短いことで、僅少にとどめることができるか
ら、モールドパッケージ部の成形に際しての不良品の発
生率を大幅に低減できる効果を有する。Therefore, according to the present invention, when molding the mold package portion, the injection direction of the molten synthetic resin in each suspension lead is controlled by the molten synthetic resin injected from one corner of the mold package portion. Due to the short length of the metal wire, it is possible to minimize the bending deformation of the metal wires near the left and right both sides of the left and right suspension leads extending in the right-angle direction. Has the effect of greatly reducing the incidence of defective products.
【００１２】[0012]
【実施例】以下、本発明の実施例を、図１及び図２の図
面について説明する。この図において符号１１は、薄い
金属板製のリードフレームを示す、このリードフレーム
１１には、その略中央部にアイランド部１２が、当該ア
イランド部１２における四隅部又は四隅部に近い部位か
ら放射状に一体的に延びる四本の吊りリード１３ａ，１
３ｂ，１３ｃ，１３ｄを介して一体的に連接した状態で
形成されていると共に、前記各吊りリード１３ａ，１３
ｂ，１３ｃ，１３ｄの間の部分に多数本のリード端子１
４が、当該各リード端子１４が前記アイランド部１２に
向かって放射状に延びるように一体的に造形されてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In this figure, reference numeral 11 denotes a lead frame made of a thin metal plate. In this lead frame 11, an island portion 12 is provided at a substantially central portion thereof in a radial manner from four corners of the island portion 12 or a portion near the four corners. Four suspension leads 13a, 1 extending integrally
3b, 13c, and 13d, and are integrally connected to each other.
b, 13c, 13d, a large number of lead terminals 1
4 are integrally formed such that the respective lead terminals 14 extend radially toward the island portion 12.
【００１３】なお、前記アイランド部１２には、半導体
チップ１５をダイボンディングし、次いで、この半導体
チップ１５における各電極と、前記各リード端子１４の
先端との間の各々を、金属線１６にてワイヤボンディン
グしたのち、これらの全体を、合成樹脂製のモールドパ
ッケージ部１７にてパッケージするのであり、このモー
ルドパッケージ部１７の成形に際しては、当該モールド
パッケージ部１７における一つの隅部に設けたゲート１
８から溶融合成樹脂を矢印Ａで示す方向に注入すること
によって行うのである。A semiconductor chip 15 is die-bonded to the island portion 12, and then each of the electrodes of the semiconductor chip 15 and the tip of each of the lead terminals 14 are connected by a metal wire 16. After wire bonding, the whole is packaged in a synthetic resin mold package portion 17. When molding the mold package portion 17, the gate 1 provided at one corner of the mold package portion 17 is provided.
This is carried out by injecting the molten synthetic resin in the direction indicated by arrow A from 8.
【００１４】そして、前記各吊りリード１３ａ，１３
ｂ，１３ｃ，１３ｄの間に位置する各リード端子１４に
おける先端を結ぶ線１９を、当該各リード端子１４の先
端から前記半導体チップにおける電極までの距離を各吊
りリード１３ａ，１３ｂ，１３ｃ，１３ｄに隣接するリ
ード端子１４においては最も小さい距離Ｓ１にする一
方、各吊りリード１３ａ，１３ｂ，１３ｃ，１３ｄの間
の中央に位置するリード端子１４において最も大きい距
離Ｓ２にすると言うように、前記各吊りリード１３ａ，
１３ｂ，１３ｃ，１３ｄに隣接する箇所において最も小
さく各吊りリード１３ａ，１３ｂ，１３ｃ，１３ｄから
離れるにつれて次第に大きくするように傾斜するのであ
る。The suspension leads 13a, 13
b, 13c, and 13d, a wire 19 connecting the tip of each lead terminal 14 is connected to each of the suspension leads 13a, 13b, 13c, and 13d by changing the distance from the tip of each lead terminal 14 to the electrode of the semiconductor chip. The adjacent lead terminals 14 have the shortest distance S1, while the lead terminals 14 located at the center between the suspension leads 13a, 13b, 13c and 13d have the largest distance S2. 13a,
At the portion adjacent to 13b, 13c, 13d, the inclination is made so as to gradually increase as the distance from each of the suspension leads 13a, 13b, 13c, 13d becomes smallest .
【００１５】このように構成することにより、各吊りリ
ード１３ａ，１３ｂ，１３ｃ，１３ｄの間に位置する各
リード端子１４の本数を多くした場合においても、この
各リード端子１４の先端の相互間に、各吊りリード１３
ａ，１３ｂ，１３ｃ，１３ｄの間に位置する各リード端
子１４における先端を結ぶ線１９を傾斜したことで、所
定以上のピッチ間隔Ｐを確保することができる一方、各
吊りリード１３ａ，１３ｂ，１３ｃ，１３ｄの左右両側
に隣接する付近のリード端子１４に対する金属線１６に
おける長さを大幅に短くすることができるのである。With this configuration, even when the number of lead terminals 14 located between the suspension leads 13a, 13b, 13c, and 13d is increased, the distance between the tips of the lead terminals 14 is increased. , Each hanging lead 13
The pitches P that are equal to or greater than a predetermined pitch can be ensured by inclining the lines 19 connecting the tips of the lead terminals 14 located between a, 13b, 13c, and 13d, while each of the suspension leads 13a, 13b, and 13c. , 13d can be greatly shortened in the metal wire 16 with respect to the lead terminals 14 near the left and right sides adjacent to each other.
【００１６】従って、モールドパッケージ部１７の成形
に際して、当該モールドパッケージ部１７における一つ
の隅角部のゲート１８から矢印Ａの方向に注入する溶融
合成樹脂によって、各吊りリード１３ａ，１３ｂ，１３
ｃ，１３ｄのうち前記溶融合成樹脂の注入方向Ａと直角
方向に延びる左右両吊りリード１３ｂ，１３ｄにおける
左右両側に隣接する付近の金属線１６が湾曲変形するこ
とを、当該金属線１６の長さが短いことで、僅少にとど
めることができるのである。Accordingly, when the mold package portion 17 is formed, each of the suspension leads 13a, 13b, 13 is formed by the molten synthetic resin injected from the gate 18 at one corner of the mold package portion 17 in the direction of arrow A.
The length of the metal wire 16 adjacent to the right and left suspension leads 13b and 13d adjacent to the left and right sides of the left and right suspension leads 13b and 13d extending in the direction perpendicular to the injection direction A of the molten synthetic resin is determined by the length of the metal wire 16. Is short, so it can be kept small.
【図１】本発明の実施例によるリードフレームの平面図
である。FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention.
【図２】図１の要部拡大図である。FIG. 2 is an enlarged view of a main part of FIG.
【図３】従来におけるリードフレームの平面図である。FIG. 3 is a plan view of a conventional lead frame.
【図４】図３の要部拡大図である。FIG. 4 is an enlarged view of a main part of FIG. 3;
１１ リードフレーム １２ アイランド部 １３ａ，１３ｂ，１３ｃ，１３ｄ 吊りリード １４ リード端子 １５ 半導体チップ １６ 金属線 １７ モールドパッケージ部 １８ ゲート １９ リード端子の先端を結ぶ線 DESCRIPTION OF SYMBOLS 11 Lead frame 12 Island part 13a, 13b, 13c, 13d Suspended lead 14 Lead terminal 15 Semiconductor chip 16 Metal wire 17 Mold package part 18 Gate 19 Wire which connects the tip of a lead terminal
Claims (1)
ンド部を、当該アイランド部における四隅部又は四隅部
に近い部位から放射状に一体的に延びる四本の吊りリー
ドを介して一体的に連接した状態で形成すると共に、前
記各吊りリードの間の部分に多数本のリード端子を、当
該各リード端子が前記アイランド部に向かって放射状に
延びるように一体的に造形して成るリードフレームにお
いて、 前記各吊りリード間に位置する各リード端子における先
端を結ぶ線を、当該各リード端子の先端から前記半導体
チップの電極までの距離が前記吊りリードに隣接する箇
所において最も小さく吊りリードから離れるにつれて次
第に大きくなるように傾斜したことを特徴とするクワッ
ド型半導体装置用リードフレームの構造。1. An island portion on which a semiconductor chip is mounted at a substantially central portion is integrally connected via four suspension leads which extend radially and integrally from four corners or a portion near the four corners of the island portion. In a lead frame formed in a state, a large number of lead terminals are integrally formed so that each of the lead terminals radially extends toward the island portion, at a portion between the suspension leads. next as a line connecting the tip of each lead terminal located between the suspension leads away from the smallest suspension lead at the point where the distance from the tip of each of the lead terminals to the electrodes of said semiconductor chip adjacent to the suspension lead
Secondly, a structure of a lead frame for a quad-type semiconductor device, characterized in that the structure is inclined to be larger .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27411793A JP2834990B2 (en) | 1993-11-02 | 1993-11-02 | Structure of lead frame for quad type semiconductor device |
| US08/327,835 US5466968A (en) | 1993-11-02 | 1994-11-01 | Leadframe for making semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27411793A JP2834990B2 (en) | 1993-11-02 | 1993-11-02 | Structure of lead frame for quad type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07130940A JPH07130940A (en) | 1995-05-19 |
| JP2834990B2 true JP2834990B2 (en) | 1998-12-14 |
Family
ID=17537258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27411793A Expired - Fee Related JP2834990B2 (en) | 1993-11-02 | 1993-11-02 | Structure of lead frame for quad type semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5466968A (en) |
| JP (1) | JP2834990B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2765542B2 (en) * | 1995-12-20 | 1998-06-18 | 日本電気株式会社 | Resin-sealed semiconductor device |
| DE19652395A1 (en) * | 1996-06-13 | 1997-12-18 | Samsung Electronics Co Ltd | Integrated circuit module |
| US5939775A (en) * | 1996-11-05 | 1999-08-17 | Gcb Technologies, Llc | Leadframe structure and process for packaging intergrated circuits |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60121747A (en) * | 1984-07-25 | 1985-06-29 | Hitachi Ltd | Semiconductor device |
| JPH02246126A (en) * | 1989-03-20 | 1990-10-01 | Seiko Epson Corp | Semiconductor device |
| JPH04164357A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Lead frame for semiconductor device |
| JPH04333276A (en) * | 1991-05-08 | 1992-11-20 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US5245214A (en) * | 1991-06-06 | 1993-09-14 | Northern Telecom Limited | Method of designing a leadframe and a leadframe created thereby |
-
1993
- 1993-11-02 JP JP27411793A patent/JP2834990B2/en not_active Expired - Fee Related
-
1994
- 1994-11-01 US US08/327,835 patent/US5466968A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5466968A (en) | 1995-11-14 |
| JPH07130940A (en) | 1995-05-19 |
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