JPH04132257A - Preparation of semiconductor laminated substrate - Google Patents
Preparation of semiconductor laminated substrateInfo
- Publication number
- JPH04132257A JPH04132257A JP25345490A JP25345490A JPH04132257A JP H04132257 A JPH04132257 A JP H04132257A JP 25345490 A JP25345490 A JP 25345490A JP 25345490 A JP25345490 A JP 25345490A JP H04132257 A JPH04132257 A JP H04132257A
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- film
- silicon substrate
- sio2
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 47
- 229910052710 silicon Inorganic materials 0.000 abstract description 47
- 239000010703 silicon Substances 0.000 abstract description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 229910052681 coesite Inorganic materials 0.000 abstract description 11
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 229910052682 stishovite Inorganic materials 0.000 abstract description 11
- 229910052905 tridymite Inorganic materials 0.000 abstract description 11
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241001463014 Chazara briseis Species 0.000 description 1
- 229910004283 SiO 4 Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体積層基板の製造方法に関し、特に、貼り
合わせ法を用いたSol基板の製造方法に適用して好適
なものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor multilayer substrate, and is particularly suitable for application to a method for manufacturing a Sol substrate using a bonding method.
貼り合わせ法を用いたS OI (Silicon O
n In5ulator)基板の製造方法は、従来、次
のようにして行われていた。SOI (Silicon O
Conventionally, a method for manufacturing a substrate (In5lator) has been carried out as follows.
まず、第2図(a)に示すように、第1のシリコン基板
lの主面に熱酸化法により5iOzl12を形成する。First, as shown in FIG. 2(a), 5iOzl12 is formed on the main surface of a first silicon substrate l by thermal oxidation.
次に、第2図(b)に示すように、この第1のシリコン
基板1の主面に第2のシリコン基板3の主面を貼り合わ
せ、熱処理することによりシリコン基板同士を互いに接
着する。Next, as shown in FIG. 2(b), the main surface of the second silicon substrate 3 is bonded to the main surface of the first silicon substrate 1, and the silicon substrates are bonded to each other by heat treatment.
次に、第2図(C)に示すように、第2のシリコン基板
3をその裏面側から研磨していき、Sing膜2上に能
動領域として薄いシリコン膜3を残して、Sol基板を
形成する。Next, as shown in FIG. 2(C), the second silicon substrate 3 is polished from the back side, leaving a thin silicon film 3 as an active region on the Sing film 2 to form a Sol substrate. do.
しかしながら、この方法では、最後の研磨工程において
研磨量をモニターすることが難しく、このため、残存さ
せるシリコン膜3の膜厚を精密にコントロールすること
が困難であった。However, with this method, it is difficult to monitor the amount of polishing in the final polishing step, and therefore it is difficult to accurately control the thickness of the silicon film 3 to remain.
この問題を解決するために、次のような方法がとられて
いる。In order to solve this problem, the following methods have been taken.
まず、第3図(a)に示すように、第1のシリコン基板
1の主面全面に熱酸化法によりSiO□膜2を形成する
。一方、第2のシリコン基板3の主面の一部を熱酸化し
て、局部的にSiO□4を形成する。First, as shown in FIG. 3(a), a SiO□ film 2 is formed on the entire main surface of a first silicon substrate 1 by thermal oxidation. On the other hand, a part of the main surface of the second silicon substrate 3 is thermally oxidized to locally form SiO□4.
このStow 4の表面は、シリコン基板3の主面の表
面から凸状に突出しており、また、SiO□4とシリコ
ン基板3との境界面は、シリコン基板3の主面の表面よ
りも深いところにある。The surface of this Stow 4 protrudes convexly from the main surface of the silicon substrate 3, and the interface between the SiO□4 and the silicon substrate 3 is deeper than the main surface of the silicon substrate 3. It is in.
次いで、第3図(b)に示すように、第1のシリコン基
板lと第2のシリコン基板3との主面同士を互いに貼り
合わせ、熱処理により接着する。Next, as shown in FIG. 3(b), the main surfaces of the first silicon substrate 1 and the second silicon substrate 3 are bonded to each other and bonded by heat treatment.
次いで、第3図(C)に示すように、第2のシリコン基
板3の裏面側から研磨する。この時、研磨速度はシリコ
ンよりもSiO2の方がかなり小さいため、シリコン基
板3に形成したSiO□4がストッパーとして働き、S
ing膜2上に能動領域として残存させるシリコン膜3
の膜厚を一定にすることができる。Next, as shown in FIG. 3(C), the second silicon substrate 3 is polished from the back side. At this time, since the polishing rate of SiO2 is much lower than that of silicon, the SiO□4 formed on the silicon substrate 3 acts as a stopper, and the S
a silicon film 3 left on the ing film 2 as an active region;
The film thickness can be kept constant.
しかしながら、第3図に示した方法では、第2のシリコ
ン基板3の主面上に5i(h4の突起が存在するため、
第3図(b)に示すように基板同士を貼り合わせた時に
、突起の周囲に空隙が生じて接着性が悪くなったり、突
起の周辺のシリコン基板3の主面が平面を保てずに撓ん
でシリコンの結晶性が悪くなる等の問題があった。However, in the method shown in FIG. 3, since there are protrusions 5i (h4) on the main surface of the second silicon substrate 3,
As shown in FIG. 3(b), when the substrates are bonded together, voids may occur around the protrusions, resulting in poor adhesion, or the main surface of the silicon substrate 3 around the protrusions may not be able to maintain a flat surface. There were problems such as deterioration of silicon crystallinity due to bending.
本発明は上述の問題点に鑑みてなされたものであって、
能動領域となるシリコン膜の膜厚を一定にコントロール
することができ、且つ、結晶性や接着性を損なうことな
くSOI基板を製造することができる方法を提供しよう
とするものである。The present invention has been made in view of the above-mentioned problems, and includes:
The present invention aims to provide a method in which the thickness of a silicon film serving as an active region can be controlled to be constant, and an SOI substrate can be manufactured without impairing crystallinity or adhesiveness.
上記課題を解決するために、本発明の半導体積層基板の
製造方法は、
第1の半導体基板の主面に酸化膜を形成する工程と、
上記酸化膜表面に凹部を形成する工程と、第2の半導体
基板の主面の上記第1の半導体基板の凹部と対応する位
置に、酸化膜により凸部を形成する工程と、
上記第2の半導体基板の凸部が上記第1の半導体基板の
凹部に嵌合するように、上記第1及び第2の半導体基板
の主面同士を貼り合わせて、熱処理により互いに接着す
る工程と、
酸化膜が露出するまで上記第2の半導体基板をその裏面
側から研磨する工程とを有するものである。In order to solve the above problems, the method for manufacturing a semiconductor multilayer substrate of the present invention includes the steps of: forming an oxide film on the main surface of a first semiconductor substrate; forming a recess on the surface of the oxide film; forming a convex part using an oxide film at a position corresponding to the concave part of the first semiconductor substrate on the principal surface of the semiconductor substrate; a step of bonding the main surfaces of the first and second semiconductor substrates to each other and bonding them to each other by heat treatment so that they fit together; and a step of attaching the second semiconductor substrate from the back side until the oxide film is exposed. It has a step of polishing.
本発明においては、第2の半導体基板の主面に存在する
突起に対応する第1の半導体基板の主面の位置に凹部を
形成しているので、第1及び第2の半導体基板を互いに
貼り合わせた時に、各々の主平面隠士が充分に密着する
。従って、突起近傍の空隙や、第2のシリコン基板の主
面の撓みは生じない。In the present invention, since the recess is formed at the position of the main surface of the first semiconductor substrate corresponding to the protrusion existing on the main surface of the second semiconductor substrate, the first and second semiconductor substrates can be attached to each other. When put together, each main plane hermit will be in close contact with each other. Therefore, no voids are formed near the protrusions, and no deflection of the main surface of the second silicon substrate occurs.
以下、本発明の実施例を第1図を参照して説明する。 Embodiments of the present invention will be described below with reference to FIG.
まず、第1図(a)に示すように、シリコン基板1の主
面に熱酸化法により2pm厚の5ift膜2を形成する
。First, as shown in FIG. 1(a), a 5ift film 2 having a thickness of 2 pm is formed on the main surface of a silicon substrate 1 by thermal oxidation.
次いで、5iOz膜2上にフォトレジストパターンを形
成し、これをマスクとして、Sing膜2をバッファ弗
酸溶液中で5000人の深さだけ選択エツチングし、そ
の後、フォトレジストを除去して、第1図(b)に示す
ように、SiO□膜2に凹部6を複数個形成する。Next, a photoresist pattern is formed on the 5iOz film 2, and using this as a mask, the Sing film 2 is selectively etched to a depth of 5000 mm in a buffered hydrofluoric acid solution.Then, the photoresist is removed and the first As shown in Figure (b), a plurality of recesses 6 are formed in the SiO□ film 2.
一方、第1図(c)に示すように、第2のシリコン基板
3の主面に熱酸化法により200人厚O5ing膜7を
形成する。On the other hand, as shown in FIG. 1(c), a 200-layer thick O5ing film 7 is formed on the main surface of the second silicon substrate 3 by thermal oxidation.
次いで、第1図(d)に示すように、このSiO□膜7
上にCVD法により1500人厚(7)SiJ4膜8を
形成した後、周知の方法でこの5i2N、膜8をバター
ニングする。ここで、Si3N4膜8に形成する開口の
位置は、第1と第2のシリコン基板l及び3の主面同士
を貼り合わせた時に、第1のシリコン基板1上のSin
、膜2に形成した凹部6の位置に対応する。Next, as shown in FIG. 1(d), this SiO□ film 7
After forming a SiJ4 film 8 with a thickness of 1500 mm (7) on top by the CVD method, this 5i2N film 8 is patterned by a well-known method. Here, the position of the opening formed in the Si3N4 film 8 is determined by the position of the opening formed in the Si3N4 film 8 when the main surfaces of the first and second silicon substrates l and 3 are bonded together.
, corresponds to the position of the recess 6 formed in the membrane 2.
次に、第1図(e)に示すように、熱酸化法によりSi
、N4膜8の開口部分にのみSiO□4をlamの厚さ
で形成する。Next, as shown in FIG. 1(e), Si was heated by thermal oxidation.
, SiO□4 is formed to a thickness of lam only in the opening portion of the N4 film 8.
次いで、プラズマエツチング法により5iJa膜8を、
更に、バッファ弗酸によりSiO2膜7を夫々除去する
。これにより、第1図(f)に示すように、第2のシリ
コン基板3の主面に突起状のSi0g4が形成される。Next, the 5iJa film 8 is formed by plasma etching.
Further, each SiO2 film 7 is removed using buffered hydrofluoric acid. As a result, protruding Si0g4 is formed on the main surface of the second silicon substrate 3, as shown in FIG. 1(f).
この時、突起状の5i(h 4の頂部は、第2のシリコ
ン基板3の主面のシリコン表面から約4500人盛り上
がっている。At this time, the top of the protrusion 5i (h4) rises by about 4,500 degrees from the silicon surface of the main surface of the second silicon substrate 3.
次いで、第1図(g)に示すように、第1のシリコン基
板1と第2のシリコン基板3との主面同士を貼り合わせ
、熱処理を行うことにより、両者を接着する。この時、
第2のシリコン基板3の突起状のSiO,4は、第1の
シリコン基板1上のSiO2膜2の凹部6内に収まるた
め、第1のシリコン基板1の凹部6を除く平面部と第2
のシリコン基板3の突起部を除く平面部同士は充分に密
着する。Next, as shown in FIG. 1(g), the main surfaces of the first silicon substrate 1 and the second silicon substrate 3 are bonded together and heat treated to bond them together. At this time,
The protruding SiO 4 of the second silicon substrate 3 fits within the recess 6 of the SiO2 film 2 on the first silicon substrate 1.
The planar portions of the silicon substrate 3 other than the protruding portions are in sufficient contact with each other.
また、第2のシリコン基板3が撓んだりすることがなく
、従って、その結晶性を損なうこともない。Further, the second silicon substrate 3 is not bent, and therefore its crystallinity is not impaired.
次いで、第1図(h)に示すように、5iOz4の一部
が露出するまで第2のシリコン基板3をその裏面側から
研磨することにより、550z膜2上に能動領域として
約4500人盛のシリコン膜3が形成される。Next, as shown in FIG. 1(h), by polishing the second silicon substrate 3 from the back side until a part of the 5iOz4 is exposed, about 4,500 layers of active area are formed on the 550z film 2. A silicon film 3 is formed.
以上説明したように、本発明によれば、貼り合わせ法に
よって半導体積層基板を製造する際に、第1の半導体基
板の上に形成された酸化膜と、その上に貼り合わされる
第2の半導体基板との間の接着性が高く、また、能動領
域としての第2の半導体基板の結晶性を損なうことがな
い。As explained above, according to the present invention, when manufacturing a semiconductor multilayer substrate by a bonding method, an oxide film formed on a first semiconductor substrate and a second semiconductor bonded thereon are bonded together. It has high adhesion to the substrate, and does not impair the crystallinity of the second semiconductor substrate as an active region.
第1図(a)〜(h)は本発明の一実施例による半導体
積層基板の製造方法を工程順に示す断面図、第2図(a
)〜(c)は従来の半導体積層基板の製造方法を工程順
に示す断面図、第3図(a)〜(C)は従来の別の半導
体積層基板の製造方法を工程順に示す断面図である。
なお、図面に用いた符号において、
l ・・・・・・・・・ 第1のシリコン基板2 ・・
・・・・・・・ SiO□膜
3 ・・・・・・・・・ 第2のシリコン基板4 ・・
・・・・・・・ SiO□
6 ・・・・・・・・・ 凹部
7 ・・・・・・・・・ SiO□膜
8 ・・・・・・・・・ 5i3N41!である。1(a) to 1(h) are cross-sectional views showing the manufacturing method of a semiconductor multilayer substrate according to an embodiment of the present invention in the order of steps, and FIG. 2(a)
) to (c) are cross-sectional views showing a conventional method for manufacturing a semiconductor multilayer substrate in order of steps, and FIGS. 3(a) to (C) are cross-sectional views showing another conventional method for manufacturing a semiconductor multilayer substrate in order of steps. . In addition, in the symbols used in the drawings, l...... First silicon substrate 2...
...... SiO□ film 3 ...... Second silicon substrate 4 ...
・・・・・・・・・ SiO□ 6 ・・・・・・・・・ Concavity 7 ・・・・・・・・・ SiO□ film 8 ・・・・・・・・・ 5i3N41! It is.
Claims (1)
と対応する位置に、酸化膜により凸部を形成する工程と
、 上記第2の半導体基板の凸部が上記第1の半導体基板の
凹部に嵌合するように、上記第1及び第2の半導体基板
の主面同士を貼り合わせて、熱処理により互いに接着す
る工程と、酸化膜が露出するまで上記第2の半導体基板
をその裏面側から研磨する工程とを有する半導体積層基
板の製造方法。[Claims] A step of forming an oxide film on the main surface of a first semiconductor substrate; a step of forming a recess on the surface of the oxide film; and a step of forming a recess on the main surface of the second semiconductor substrate. forming a convex portion using an oxide film at a position corresponding to the concave portion of the second semiconductor substrate; A method for manufacturing a semiconductor multilayer substrate, comprising the steps of: bonding the main surfaces of the second semiconductor substrates together and bonding them to each other by heat treatment; and polishing the second semiconductor substrate from the back side until the oxide film is exposed.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2253454A JP2813921B2 (en) | 1990-09-21 | 1990-09-21 | Manufacturing method of semiconductor laminated substrate |
US07/763,302 US5238865A (en) | 1990-09-21 | 1991-09-20 | Process for producing laminated semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2253454A JP2813921B2 (en) | 1990-09-21 | 1990-09-21 | Manufacturing method of semiconductor laminated substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04132257A true JPH04132257A (en) | 1992-05-06 |
JP2813921B2 JP2813921B2 (en) | 1998-10-22 |
Family
ID=17251622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2253454A Expired - Fee Related JP2813921B2 (en) | 1990-09-21 | 1990-09-21 | Manufacturing method of semiconductor laminated substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2813921B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0410568A (en) * | 1990-04-27 | 1992-01-14 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1990
- 1990-09-21 JP JP2253454A patent/JP2813921B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0410568A (en) * | 1990-04-27 | 1992-01-14 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2813921B2 (en) | 1998-10-22 |
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