JPH04127241A - Parity generation/check circuit - Google Patents

Abstract

PURPOSE:To check the normal operations of a parity memory and a parity generation/check circuit by setting a parity generation rule used when the data are written in a data memory and a parity check rule used when the data are read out of the data memory so that both rules are different from each other. CONSTITUTION:An RS flip-flop 305 and an EX-OR circuit 306 are provided so that the switch is attained between the even and odd parities. The circuit 306 gives directly the SIGMA0 output of a check circuit 301 to a parity error state holding circuit 302 and a gate circuit 304 when a parity inverting signal 101 is kept at 'L'. Then the circuit 306 inverts the output 303 when the signal 101 is kept at 'H'. Then a parity generation rule used when the data are written in a data memory and a parity check rule used when the data are read out of the data memory are set so that both rules are different from each other. Thus the operations of a parity memory and a parity generation/check circuit can be confirmed with higher reliability.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a parity generation/check circuit for a microcomputer system, and particularly to a parity generation/check circuit that can check the operation of the parity generation/check circuit itself and the parity memory. This concerns a check circuit.

[Prior Art] Generally, in microcomputer systems, data errors are detected by parity checking.

FIG. 4 shows an example of the configuration of a conventional microcomputer system in which such error detection is performed.

This system uses a microcomputer (
(hereinafter abbreviated as microcomputer) 201, a readable and writable data memory 202 that stores data for arithmetic processing by the microcomputer 201, an address decoder 203 that generates a memory selection signal 207, and parity data 209.
a readable and writable parity memory 204 that stores parity data 209 and a parity generation/check circuit 205 that generates parity data 209 and performs a parity check.
It mainly consists of.

First, the procedure when the microcomputer 201 writes data to the data memory 202 in the above system will be explained.

■The microcomputer 201 sets the write destination address to
Output to bus 206.

(2) The address decoder 203 generates a memory selection signal 207 from the signal on the address bus 206 and supplies it to the data memory 202 and the parity memory 204.

(2) The microcomputer 201 outputs data to be written to the data memory 202 to the data bus 208.

■Parity generation/check circuit 205 is data bus 2
Parity data 209 is generated from the signal on 08 and provided to parity memory 204.

■The microcomputer 201 has a memory write signal book 210 (*
indicates a negative logic signal line. ), writes data to the data memory 202 and writes parity data 209 to the parity memory 204 in accordance with the memory selection signal 207.

Next, a description will be given of procedure 1 when the microcomputer 201 reads data from the data memory 202 in this system.

(2) The microcomputer 201 outputs the address from which data is to be read to the address bus 206.

(2) The address decoder 203 generates a memory selection signal 207 from the signal on the address bus 206 and supplies it to the data memory 202 and the parity memory 204.

■The microcomputer 201 outputs a memory read signal 211 and selects the data memory 202 according to the memory selection signal 207.
The parity data 209 is read from the parity memory 204.

■Parity generation/check circuit 205 is data bus 2
A parity check is performed using the data on 08 and parity data 209, and when an abnormality occurs, a parity error detection signal 212 is given to the microcomputer 201.

This signal line is normally connected to an interrupt input terminal of the microcomputer 201.

FIG. 5 shows an example of the internal configuration of the parity generation/check circuit 205 when an 8-bit microcomputer is used. This circuit mainly includes a check circuit 301 that generates parity bits and performs parity checks, and a parity error state holding circuit 302.

In the test circuit 301, the ΣO ratio output 01 becomes "L" when the number of "H"s at the A-I input is an even number, and the ΣO ratio output 01 becomes "L" when the number of "H"s at the A-1 input is an odd number. A-1, inputs A to H are 8-bit data.
from bus 208. The remaining one input is given from an AND circuit 300 which receives the memory write signal zero 210 and the parity data 209 as inputs.

The parity error state holding circuit 302 receives the read signal 2
11 is input, the ΣO output 301 of the inspection circuit 301
This is a D-type flip-flop circuit that holds the parity error detection signal 212 as a parity error detection signal 212 until the next memory read signal 211 is input.

The gate circuit 304 closes when the read signal 211 is input, and prevents the Σ0 output 301 of the test circuit 301 from being applied as the parity data 209 to the parity memory 204 (Figure 4).

Conversely, when the memory read signal 211 is not input, it is opened and the ΣO output 303 is provided as the parity data 209 to the parity memory 204 and the AND circuit 300.

Now, with reference to FIGS. 6 and 7, the write/read operations for checking the operation of the data memory 02 by the parity generation/check circuit will be described.

When the microcomputer 201 writes data to the data memory 202, the write data is input manually to the A-H inputs of the test circuit 301, and since the memory write signal 210 becomes "L" at the time of writing, the I input is Therefore, as shown in FIG. 6, when the number of "H" in A-H manual power is an even number, the ΣO output 303 becomes "L",
“0” is written to the specified address of the parity memory 2040 as the parity data 209. On the other hand, when the number of Hjt at the A-H input is an odd number, Σ0
The output 303 becomes “6H” and the parity data 204
``1'' is written to the corresponding address.

In contrast, the microcomputer 201 uses the data memory 202
When reading data from A-) of the inspection circuit 301
(Read data is input to the input, and the memory write signal zero 210 is “H91” at the time of reading, so
The parity data 209 read from the parity memory 204 is input as is to the I input of the test circuit 301 .

At this time, if the data memory 202 is normal and the number of "H??" in the A-H input is an even number as shown in the upper column of FIG. 7, the parity data 209 is "O", that is, "L". On the contrary, if the number is odd, the parity data 209 is "l", that is, jjH, so Σ0
In either case, the output 303 becomes "L tt", and as a result, the parity error detection signal 212, which is the output of the parity error state holding circuit 302, also becomes "L".

Suppose that an abnormality occurs in the data memory 202 and the data
When reading data at an address where an odd number of bit values have changed, as shown in the bottom column of Figure 7, if the A-H input has an even number of normal values, it will be an odd number; If so, the number is even, so the Σ0 output 303 becomes "H" in any case. As a result, the rise of the memory read signal 211 causes the parity error detection signal 212 to also become "H", and the parity error is detected by the microcomputer 2.
01 will be notified.

[Problems to be Solved by the Invention] By the way, in order to check whether the parity memory and the parity generation/check circuit themselves are operating normally using the conventional parity generation/check circuit method, it is necessary to check whether the parity memory and the parity generation/check circuit themselves are operating normally. An indirect check method was used in which data was written to an arbitrary address and data was read from the same address to confirm that no parity errors had occurred.

However, with this method, when a parity error occurs, it is possible to know that either the data memory, the parity memory, or the parity generation/check circuit is abnormal, but the parity generation/check circuit itself It is impossible to know whether the parity is operating normally or whether the correct parity data is written in the parity memory. This is because although it is possible to check the circuit output with respect to a constant input direction, it is not only impossible to check the circuit output change with respect to the input change, but also the output direction change with respect to the input change of the parity memory cannot be checked.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a parity generation/check circuit capable of checking whether a parity memory and a parity generation/check circuit are operating normally.

[Means for solving the problem] The gist of the first invention is that when generating and checking parity,
The reason lies in the addition of a circuit that allows selection of even parity and odd parity. Here, even parity means that when the number of °°H'' in the data is even, the parity data becomes 12', and odd parity means that when the number of H'' in the data is odd, the parity data becomes 12'. ''.

That is, the parity generation/check circuit of the first invention generates parity and writes it to the parity memory when writing data from the microcomputer to the data memory, and compares the read data and parity when reading data from the data memory. In the parity generation/check circuit that performs a parity check to check the operation of the data memory, the parity generation rule when writing data to the data memory and the parity check rule when reading data are set to be different from each other. It is configurable.

The gist of the second invention lies in the addition of a selection circuit for writing data only into the data memory and not writing data into the parity memory.

That is, the parity generation/check circuit of the second invention generates parity and writes it to the parity memory when writing data from the microcomputer to the data memory, and compares the read data and parity when reading data from the data memory. , q) In a parity generation/check circuit that performs a parity check to check the operation of the data memory, it is possible to prohibit writing of parity to the parity memory when writing data to the data memory. .

[Operation] In the first invention, for example, when checking the operation of the data memory, the parity generation rule when writing data to the data memory and the parity check rule when reading data are set to be the same. do. In this case, when the data memory is normal, the parity
Assume that a certain output result indicating that no error is detected is obtained, and the normal operation of the data memory is confirmed.

Next, consider the case where, after confirming the normal operation of the data memory, the operation of the parity memory and parity generation/check circuit is further checked.

In this case, the parity generation rules when writing data to data memory and the parity generation rules when reading data are
Set the check rules to be different from each other.

Then, if the parity memory and the parity generation/check circuit are normal, an output result opposite to that obtained when checking the operation of the data memory will be obtained. Therefore, it is possible to confirm the normal operation of the parity memory and the parity generation/check circuit.

On the other hand, if the parity memory and the parity generation/check circuit are abnormal, the same output result as when checking the operation of the data memory will be obtained. Therefore, abnormalities in the parity memory and parity generation/check circuit can be confirmed.

In the second invention, for example, when checking the operation of the data memory, first the parity memory is set to a state where parity is written. Write data to any address in the data memory and write parity to the parity memory at the same time.

Read data from the same address in data memory.

At this time, since no parity error is detected, normal operation of the data memory is confirmed.

Next, the parity memory is set to write parity. Data such that the number of "H" bits in the data is an even number is written to an arbitrary address in the data memory. At this time, "0" is written to the address of the parity memory. Set the state to prohibit writing of parity to the parity memory.

Thereafter, data such that the number of 'H'' bits in the data is an odd number is written again to the same address in the data memory. However, parity is not written to the parity memory. When data is read from the same address in the data memory, the number of "Hl+" in the data memory is an odd number, but since "'0pa" is written in the parity memory, both the parity memory and parity If the generation/check circuit is normal, a parity error will occur.

On the other hand, if the parity memory and the parity generation/check circuit are abnormal, no parity error will occur. Therefore, abnormalities in the parity memory and parity generation/check circuit can be confirmed. Note that the same result can be obtained even if the number of "H" bits in the data is an odd number during the first write and an even number when the data is written again.

[Example 7] Examples of the present invention will be described below with reference to FIGS. 1 to 4 and 8 to 9.

First Embodiment FIG. 1 shows a parity generation/check circuit according to a first embodiment. The difference from the conventional circuit system is that an RS flip-flop 30δ and an EX-OR circuit 306 are added to enable switching between even parity and odd parity.

The EX-OR circuit 306 connects the inspection circuit 301 and parity.
It is inserted between the error state holding circuit 302, and when the parity inversion signal 101, which is one human input, is L II, the Σ0 output 303 of the inspection circuit 301 is given as it is to the parity/error state holding circuit 302 and the gate circuit 304. , conversely, when the parity inversion signal 101 is “H”, the ΣO output 30
Invert 3.

The RS flip-flop 305 outputs a parity inversion signal 101 to be applied to the EX-OR circuit 3060, is set when the parity inversion request signal 102 is "L jl", and outputs a parity inversion signal 101 of "H11".
When the parity inversion release signal 103 is "°L", it is reset and outputs the parity inversion signal 101 of "H". The parity inversion request signal *102 and the parity inversion release signal 103 are generated by accessing an appropriate address within the address space of the data memory 202 or the parity memory 204 from the microcomputer 201.

Now, the operation of this circuit configured as described above will be explained.

Immediately after this system starts up, the parity inversion signal 101 is "L", and at this time, it operates in the same way as the conventional circuit. That is, the operation of the data memory 202 is checked as described above.

Next, when confirming the operation of the parity memory 204 and the parity generation/check circuit 205, the following procedure is performed.

First, the microcomputer 201 uses the data memory 2
When writing data to 02, the parity inversion request signal 102 is generated and the parity inversion signal 101 is set to #L.
99 to "Htt. Then, EX-OR circuit 30
3 inverts the Σ0 output 303 of the test circuit 301, so as shown in FIG. ), “1” is written in the parity data 209. On the other hand, when there is an odd number of HIIs, l01' is written in the parity data 209.In other words, as will become clearer when comparing FIG. 2 with FIG.
It can be seen that even though the input conditions are the same, the values of the parity data 209 are reversed.

Next, a parity inversion release signal *103 is generated to set the parity inversion signal 101 to "j L +".

In this state, the data memory 20 into which the data was written earlier
When the contents of the address 2 are read out, assuming that the inspection circuit 30 and the parity memory 204 are normal, the A-H inputs of the inspection circuit 301 and
The total number of "H" inputs is an odd number, regardless of whether the number of "H'' in the A-H inputs is even or odd.
The ΣO output 303 becomes 4E". Therefore, the read signal 2
11 rises, the parity error detection signal 21
2 also becomes “H” and an interrupt is generated to the microcomputer 201.

By receiving an interrupt, the microcomputer 201 can confirm that the parity generation/check circuit 205 operates normally.

If an abnormality occurs in the parity memory 204 and an address where the value of the parity data 209 is inverted is read, the parity error detection signal 212 becomes "L".
Since no interrupts are sent to the microcomputer 201, it can be confirmed that an abnormality has occurred in the parity memory 204.

Further, even if an abnormality occurs in the test circuit 301 itself, the parity error detection signal 212 becomes "L" and no interrupt is generated in the microcomputer 201, so that the abnormality can be confirmed.

In this way, the operation of the parity memory 204 and the inspection circuit 30 itself can be checked on the premise that the data memory is checked when the parity is not inverted (when the parity inversion signal is "L"). This is because when checking the operation of the memory and test circuit, the parity inversion signal is set to "H" to invert the parity when checking the data memory.

In the embodiment shown in FIG. 1, the parity inversion signal can be output at any time, so it is possible to switch the parity both when writing and reading data to the data memory. It is also possible to fix the parity (or odd parity) and switch to odd parity (or even parity) when reading. Alternatively, it is also possible to make the parity switchable when writing and fix the parity when reading.

Second Embodiment FIG. 8 shows a parity generation/check circuit according to a second embodiment. The difference from the conventional circuit system is that an RS flip-flop 80 is used to inhibit writing of parity data 209 to parity memory 204 (FIG. 4).
5 and an OR circuit 806 are added to the memory write signal zero system.

Also, the difference from the first embodiment is that the conventional parity generation/check circuit shown in FIG. 5 remains unchanged;
The point is that changes are made to signals outside the parity generation/check circuit system.

The OR circuit 806 is placed between the microcomputer 2o1 (FIG. 4) and the parity memory 204, and when the parity write inhibit signal 801 is "L jj", the OR circuit 806 directly uses the memory write signal *21o of the microcomputer 201 for parity. memory·
It is given to the parity memory 204 as a write signal 81o, and conversely, when the parity write inhibit signal 801 is "H", the memory write signal zero 210 of the microcomputer 201 is not given to the parity memory 204.

The RS flip-flop 805 is connected to the above OR circuit 806.
It outputs a parity write inhibit signal 801 to be given to one input of the
When the parity write prohibition release signal *803 is L'', it is reset and outputs the parity write prohibition signal 801 of "LP+".

The parity write inhibit request signal zero 802 and the parity write inhibit release signal zero 803 are generated by the microcomputer 201 accessing appropriate addresses within the address space.

Now, the operation of this circuit configured as described above will be explained below.

First, the microcomputer system shown in FIG. 4 is started up. Immediately after the system is started up, the parity write inhibit signal 801 shown in FIG. 2
04, so it operates in the same way as a conventional circuit.

Next, data is written to an arbitrary address in the data memory 202 (FIG. 4). At this time, data is written in which the number of "H" bits in the data is an odd number. Then, "'l" is written into the corresponding address of the parity memory 204 (upper column of FIG. 9).

Next, the microcomputer 201 generates a parity write inhibit request signal *802, and changes the parity write inhibit signal 801 from "LT9" to "'H".

Then, even if the microcomputer 201 changes the memory write signal 210 to "L++", the parity memory write signal *810 to the parity memory 204 remains "H", so the parity memory 204 is changed to "L++". The parity data 209 cannot be written.Next, write data in which the number of "H" bits in the data is an even number to the same address where the data was written earlier. The value of “l” remains unchanged.
It remains as ``'' (lower column of Figure 9).

After that, the microcomputer 201 reads data from the same address. At this time, since "1" has been written in the parity memory 204, the output of the AND circuit 300 (FIG. 8) becomes "H". Then, “
Since the number of H” is an even number, the ΣO output 303 is H
”.As a result, the rise of the memory read signal 211 causes the parity error detection signal 212 to also become “H”.
Then, the parity error is notified to the microcomputer 201 (see the upper column of FIG. 3). As a result, an interrupt is manually input to the microcomputer 201, and the microcomputer 201 can confirm that the parity generation/check circuit 205 operates normally.

If an abnormality occurs in the parity memory 204 and an address where the value of the parity data 209 is inverted is read, the parity error detection signal 212 becomes "L".
Since no interrupts are sent to the microcomputer 201, it can be confirmed that an abnormality has occurred in the parity memory 204.

Further, even if an abnormality occurs in the test circuit 301 itself, the parity error becomes 'L' and no interrupt is generated in the microcomputer 201, so that the abnormality can be detected.

The reason why it is possible to check the operation of the parity memory and the parity generation/check circuit itself in this way is because writing to the parity memory can be controlled to set the contents of the parity memory so that a parity error occurs.

[Effects of invention According to the present invention, the following effects are achieved.

(1) According to the parity generation/check circuit according to claim 1, the parity generation rule when writing data to the data memory and the parity check rule when reading data can be set to be different from each other. Therefore, the operation of the parity memory and the parity generation/check circuit can be confirmed more reliably.

(2) According to the parity generation/check circuit according to claim 2, since the writing of parity to the parity memory can be controlled, the operation of the parity memory and the parity generation/check circuit can be confirmed more reliably. can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of the parity generation/check circuit according to the first embodiment, and FIG. 2 is an explanatory diagram showing the parity memory and parity generation/check circuit operation check of the first embodiment at the time of writing. FIG. 3 is an explanatory diagram also showing the reading operation, FIG. 4 is a block diagram showing an example of the internal configuration of a microcomputer system common to this embodiment and the conventional example, and FIG. 5 is a parity generation/check circuit according to the conventional example. FIG. 6 is an explanatory diagram showing the writing time of data memory operation check in the conventional example, FIG. 7 is an explanatory diagram also showing the reading time, and FIG. 8 is a parity diagram according to the second embodiment. FIG. 9 is a block diagram showing the internal configuration of the generation/check circuit. FIG. 9 is an explanatory diagram showing the operation check of the parity memory and the parity generation/check circuit of the second embodiment at the time of writing. 101... Parity inversion signal, 102... Parity inversion request signal zero, 103... Parity inversion release signal *
, 201... Microcomputer, 202... Data memory, 203... Address decoder, 20
4...Memory for parity, 205...Parity generation/check circuit, 206...Address bus, 207
is a memory selection signal, 208...data bus, 209
...Parity data, 210...Write signal zero,
211... Read signal, 301... Parity generation/
Inspection circuit for checking, 302... Parity/error state holding circuit, 303... ΣO ratio output 3 of inspection circuit
05...RS flip-flop, 306...EX
-OR circuit, 801...Parity write inhibit signal, 80
2... Parity write inhibit request signal zero, 803... Parity write inhibit release signal zero, 805... RS flip-flop, 806... OR circuit, 810... Memory write signal for parity It is zero. FIG. 1 Internal structure of the parity generation circuit according to the first embodiment. FIG. Example of the internal configuration of the microphone α controller t"z-tan stem common to this embodiment and the conventional example. FIG. Figure 9 When writing the operation check of the memory for the property and the property generation circuit 11

Claims (2)

[Claims] (1) When writing data from the microcomputer to the data memory, parity is generated and written to the parity memory, and when reading data from the data memory, a parity check is performed between the read data and the parity. In a parity generation/check circuit that performs an operation check, a parity generation rule when writing data to a data memory and a parity check rule when reading data can be set to be different from each other. Generation/check circuit. (2) When writing data from the microcomputer to the data memory, parity is generated and written to the parity memory, and when reading data from the data memory, a parity check is performed between the read data and the parity. What is claimed is: 1. A parity generation/check circuit for checking the operation of a parity generation/check circuit, wherein writing of parity to the parity memory can be prohibited when writing data to the data memory.