JPH04125892A - Chip enable signal control circuit in dual port memory element - Google Patents

Abstract

PURPOSE: To increase a data transmitting margin and to prevent malfunctions by inputting a clock signal assigning the output signal from a switching means and the completion of data transmission and providing with a latch means outputting a clock signal being a master clock inside a tip. CONSTITUTION: When a first clock signal CLK1 is in a H state, since a signal in a L state is outputted with a fourth NOR gate NO4 , a second clock signal CLK2 outputted from a third NOR gate NO3 becomes inverted signal to the output signal of a second inverter 12 and becomes L state. Next, when the signal CLK1 is transited to the L state, the signal in the H state is outputted with the gate NO4 . In this case, since the signal CLK2 is maintained in the L state regardless of the state of a signal RAS, the active state of the signal CLK2 becomes longer than the signal RAS. By this way, a data transmitting time between dual ports is compensated, the transmitting margin becomes large, and also the data transmission is correctly executed in a prescribed time.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a chip enable signal control circuit in a dual-port memory device, and particularly relates to a chip enable signal control circuit in a dual-port memory device, and particularly to a chip enable signal control circuit in a dual-port memory device.
The present invention relates to a chip enable signal control circuit in a dual port memory device that controls signals for operating the chip during data transmission between a serial access memory (access memory) port and a SAM (serial access memory).

(Prior Art) Generally, a dual port memory device is a memory device developed for use as a VRAM (video RAM) for displaying graphics. Initially, 64Kx
A 256-VRAM was developed with 4 RAM ports and 256 x 4 SAM ports. Since this time, 6
VRAM has been standardized with the addition of a write-per-bit (WRB) function that improves the functionality of 4KX4 VRAM, and a function that performs real-time data transmission (RTDT) from memory to serial data.

Currently, there are 256 IN1-bit VRAMs.
There are types such as KX4 and 128Kx8.

On the other hand, when using an in-film RAM, when transmitting information from a processor to a peripheral device, the information is first transmitted to a memory, which is a DRAM, and then the peripheral device accesses the transmitted information.

In this case, the processor cannot transmit information to the memory while the peripheral device is accessing the memory. However, in a VRAM, it is possible to transfer information to the VRAM memory through its first port while simultaneously accessing the memory from a peripheral device through a second port. The first port and the second port
Each port consists of a RAM port or a SAM boat, and since SAM boats have fast access times,
VRAM is widely used for high resolution or high speed image display.

As the data transmission cycle at the above SAM port,
There are read transmission cycles, write transmission cycles, and real-time write transmission cycles. In the read transmission cycle, the data written in the RAM boat is transmitted to the SAM port, and the data in the SAM port is set to a readable mode. In a write transfer cycle, data written from a peripheral device to a SAM port is transferred to a RAM port.

FIG. 3 shows a diagram of a chip enable signal control circuit in a conventional dual port memory device.

The chip enable signal control circuit includes a first NOR gate NOI which inputs a chip enable signal RAS applied from the outside to a negative input terminal, and a first NOR gate NO1.
A first inverter 11 inputs the output of the first inverter 11, a second inverter 2 receives the output of the first inverter 1, and inputs the output of the second inverter I2 to the negative input terminal to output the clock signal CLK. and a second NOR gate NO2.

Here, the other input terminals of the first NOR gate NO1 and the second NOR gate NO2 are always grounded.

In the data transmission mode, the first NOR gate N01 inputs the chip enable signal RAS and outputs an inverted signal with respect to the chip enable signal RAS. This signal is inverted by each of the first and second inverters and delayed by a predetermined time, and then input to the second NOR gate (NO2). The second NOR gate NO2 receives a clock signal C which is inverted with respect to the signal input to the gate.
Output LK.

FIG. 4 shows an operational waveform diagram of the chip enable signal control circuit in the data transmission mode.

As shown in FIG. 4, the clock signal CLK is a signal delayed by a predetermined time with respect to the chip enable signal RAS.

The clock signal CLK serves as a mask clock inside the chip and controls data transmission between the physical ports (between the SAM port and the RAM port).

Data transmission between the dual ports is performed only when the clock signal CLK is in the active state, that is, the chip enable signal RAS is in the active state.

(Problem to be solved by the invention) However, in conventional dual-port memory devices, the data transmission time between dual ports is limited within the active state of the chip enable signal RAS, so the data transmission margin is small. There was a problem.

Furthermore, if the data transmission time extends to the inactive state of the chip enable signal RAS, the chip will enter the precharge state before the data transmission is completed.
There were some problems that caused malfunctions.

Therefore, the present invention solves the above-mentioned problems of the prior art.The purpose of the present invention is to compensate for the data transmission time when transmitting data between physical ports, increase the data transmission margin, and prevent malfunctions. An object of the present invention is to provide a chip enable signal control circuit in a dual port memory device.

[Structure of the Invention (Means for Solving the Problems) The present invention for solving the above problems includes a switching means for performing a switching operation by inputting a chip enable signal, and an output signal and data from the switching means. The device is characterized by comprising a latch means for inputting a first clock signal specifying the time of completion of transmission and outputting a second clock signal serving as a master clock inside the chip.

Preferably, the first clock signal has a first edge during an active state of the chip enable signal, and a second edge at the time of completion of subsequent data transmission.

Further preferably, the second edge of the first clock signal occurs during an inactive state after the end of the active state of the chip enable signal, and the second edge of the first clock signal occurs during an inactive state after the end of the active state of the chip enable signal; After transitioning to the active state in synchronization with the transition, the transition to the inactive state is performed in synchronization with the second edge of the first clock signal, and the transition is made from the active state of the second clock signal or the active state of the chip enable signal. It is also characterized by being extended.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a chip enable signal control circuit diagram in a dual port memory device according to an embodiment of the present invention.

The chip enable signal control circuit of this embodiment is different from the second NOR gate NO2 of the conventional chip enable signal control circuit.
However, this is replaced with a latch section 10.

The first NOR gate NO1 performs a switching operation to invert the chip enable signal RAS as in the prior art.

Further, the latch section 10 includes a third NOR gate NO3 and a fourth NOR gate NO3.
NOR gate NO4. 3rd NOR gate NO
3 inputs the output signal of the second inverter 2 to one input terminal, inputs the output signal of the fourth NOR gate NO4 to the other input terminal, and outputs the second clock signal CLK2.

Further, the fourth NOR gate NO4 is connected to the third NOR gate NO4.
The output signal CLK2 of No. 3 is input to one input terminal, and the first clock signal CLKI is input to the other input terminal.

Here, the first clock signal CLKI is a signal indicating completion of data transmission. In other words, the first clock signal CLKI
has a first edge during the active state of the chip enable signal RAS, and a second edge indicates completion of data transmission. For example, if the first clock signal CLKI is considered to be active when it is in the L state, its first edge is a falling edge and its second edge is a rising edge.

The second clock signal C output by the third NOR gate NO3
LK2 becomes the master clock inside the chip.

In the above configuration, the operation of the chip enable signal control circuit of this embodiment will be explained using the operational waveform diagram of the chip enable signal control circuit of this embodiment in the data transmission mode shown in FIG.

In the data transmission mode, the first NOR gate N
An inverted signal delayed by a predetermined time with respect to the chip enable signal RAS input to O1 is input to the third NOR gate NO3. Also, the first clock signal CLKI is input to the fourth NOR gate NO4.

wherein a first edge of the first clock signal CLKI occurs during an active state of the chip enable signal RAS;
When the second edge occurs during the inactive state of the signal RAS, the fourth NOR gate N04 always outputs a signal in the L state when the first clock signal CLKI is in the H state, so that it is output from the third NOR gate NO3. The second clock signal CLK2 is an inverted signal with respect to the output signal of the second inverter 12. That is, since the chip enable signal RAS is in the active state, that is, in the L state, the output signal of the second inverter I2 is in the H state, and the output signal of the third inverter I2 is in the H state.
Second clock signal C output from NOR gate NO3
LK2 goes to L state, then the first clock signal CLK
When I transitions to the L state at its first edge, the fourth
The NOR gate NO4 outputs an H-state signal. In this case, the second clock signal CLK2 output from the third NOR gate NO3 is the chip enable signal RA.
The state will be maintained regardless of the state of S. In other words, even when the chip enable signal RAS transitions to an H state (inactive), the second clock signal CLK2
outputs an L-state signal, so the second clock signal CL
The active state (L state) of K2 is longer than the active state of chip enable signal RAS. In other words, the active state of the chip enable signal RAS is substantially extended.

Then, when the first clock signal CLKI transitions to the H state at its second edge, the fourth NOR gate NO4 outputs an L state signal. Also, since the chip enable signal RAS has transitioned to the H state, the 3rd NO.
The signal input to one input terminal of R gate NO3 is in the L state. Therefore, the second clock signal CLK2 output from the third NOR gate NO3 becomes H state. This means that the active state of the second clock signal CLK2 ends in synchronization with the second edge of the first clock signal CLKI and becomes inactive.

Note that when the second edge of the first clock signal CLKI occurs during the active state of the chip enable signal RAS, the second clock signal CLK2 is not synchronized with the second edge and maintains the state, and the chip enable signal RAS remains in the active state. It must be noted that the transition to the H state occurs synchronously when the active state of the signal RAS ends, that is, when the chip enable signal RAS transitions to the inactive state.

Therefore, the first clock signal CL indicates the completion of data transmission.
Since the active state of the mask clock inside the chip is extended by KI, the data transmission time between the real ports is compensated and the transmission margin is increased.

Further, since the chip is not precharged even if the data transmission time reaches the inactive state of the chip enable signal RAS, data transmission can be performed accurately within a predetermined time.

In other words, the data transmission time is compensated between the real ports, the transmission margin is increased, and stable data transmission operation can be performed.

The present invention is not limited to the above-described embodiments, but can be implemented in any appropriate manner by making appropriate design changes.

[Effects of the Invention] As explained above, according to the present invention, there is provided a switching means that performs a switching operation by manually inputting a chip enable signal, and a first switch that specifies the output signal from the switching means and the completion time of data transmission. Since it is equipped with a latch means that inputs a clock signal and outputs a second clock signal that becomes a mask clock inside the chip, it compensates for the data transmission time and increases the data transmission margin when transmitting data between the dual ports. Malfunctions are prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a chip enable signal control circuit in a dual port memory device according to an embodiment of the present invention, and FIG. 2 is an operational waveform of the chip enable signal control circuit shown in FIG. 1 in data transmission mode. 3 is a diagram of a chip enable signal control circuit in a conventional dual port memory device, and FIG. 4 is an operational waveform diagram of the chip enable signal control circuit shown in FIG. 3 in a data transmission mode. NOI...First NOR gate NO3...Third NOR gate NO4...Fourth NOR gate 11...First inverter ■2...Second inverter RAS...Chip enable signal CLKI...First clock Signal CLK2...Second clock signal 10...Latch section FIG, 4

Claims (3)

[Claims] (1) A switching means that inputs a chip enable signal to perform a switching operation, and an output signal from the switching means and a first clock signal that specifies when data transmission is completed and becomes the master clock inside the chip. A chip enable signal control circuit in a dual port memory device, comprising: latch means for outputting a second clock signal. (2) The first clock signal has a first edge during the active state of the chip enable signal, and a second edge coincident with the completion of subsequent data transmission. Enable signal control circuit. (3) the second edge of the first clock signal occurs during the inactive state after the end of the active state of the chip enable signal, and the second clock signal is synchronous with the transition of the chip enable signal to the active state; After transitioning to an active state, transitioning to an inactive state in synchronization with a second edge of the first clock signal, and the active state of the second clock signal is longer than the active state of the chip enable signal. A chip enable signal control circuit in a dual port memory device characterized by: