JPH02139792A - Dynamic type memory and dynamic type memory system - Google Patents

Abstract

PURPOSE:To rapidly and accurately execute circuit operation based upon each, the inverse of RAS timing by shifting an internal, the inverse of RAS to a precharge period to extend restoring time. CONSTITUTION:An output from an external, the inverse of RAS input buffer 1 is inputted to respective set input terminals of flip flops FF1, FF2 obtained by cross-connecting 2-input NAND gates in a row system internal, the inverse of RAS generating circuit 2 and a column system internal, the inverse of RAS generating circuit 3. The output RTM of the 1st timer circuit 4 and the output KRTM of the 2nd timer circuit 5 are correspondingly inputted to respective reset input terminals. Thus, the inverse of RAS row address strobe is divided into the row system and the column system, the row system, the inverse of RAS executes the restoring operation of the sufficient number of bit line pairs and the column system, the inverse of RAS executes the normal operation of reading/writing. Even when, the inverse of RAS is precharged by a tRASmin, the potential difference of the bit line pair can be sufficiently amplified and various timing regulated from a chip or the outside of the system can be rapidly and accurately set up.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory, and in particular to a dynamic memory and a dynamic memory that realize a RAS timeout function or an equivalent function from outside the chip. Regarding the system.

(Prior art) Recently, dynamic random access memory (hereinafter referred to as
(abbreviated as DRAM) row address capture signal R
AS (low address strobe) has a timeout function. This is originally the user (DRAM
(controlling side) must input RAS from the outside at the timing shown in Figure 11.
As shown in Figure 3, if you keep the RAS input active (low level here) for a certain period of time, then the RAS
This is a function in which the internal 'F7v'T (r-ding-ding-ding) generated within the DRAM chip automatically remains active for a required period of time, regardless of the input state.

This function eliminates the need for the user to worry about the timing to precharge RAS to a high level, making it easier to use DRAM. It is designed to prevent data from being destroyed.

The conventional RAS timeout function has the following problems as DRAM speeds increase. That is, D
As shown in FIG. 14, the input signal timing of the RAM includes a RAS active period tRAS and a RAS precharge period tRP. If the transition time required to switch the RAS signal from low level to high level or vice versa is expressed as tT, then the DRAM cycle time tRC is t.
RC-t RAS 10t RP+2 t T...
(1). At each of these timings, for example, as shown in the following table, the respective minimum value t RCmin
.

tRAsm,in, tRPminS tTmin is clearly defined. In other words, one of the advantages of the RAS timeout function, which must operate normally even if the timing is shortened to this minimum value, is that it practically eliminates the above-mentioned tRASmin specification.

According to the table above, the RAS input must be kept at a low level for 80 ns, but with the introduction of the RAS timeout function, it can be made to a high level earlier, so from the user's perspective, this is a critical timing. is reduced by one, making it easier to use.

Instead, internal RAS (YTK
A timer must be provided to keep the low level for the above 80 ns.

Next, FIG. 12 shows the relationship between the RAS signal and the operations of the bit line and word line inside the DRAM in a conventional DRAM in which no RAS timeout function has been introduced. After a while after RAS goes low, the potential of the word line rises and the data in the memory cell is output to the bit line.

When a potential difference occurs between the bit line pair, a sense amplifier is activated to sense and amplify the potential difference between the bit line pair. R.A.
When S goes high, the potential of the word line drops, storing data in the memory cell.

When the word line is completely closed, it is short-circuited to the bit line pair and equalized to vcc/2 potential (Vcc is electric potential).

By the way, as DRAMs are becoming more highly integrated and faster, it is becoming more and more time consuming to sense and amplify the potential difference between a pair of bit lines, making the bit line storage time more difficult. It becomes. for example,
When RAS access time is 80ns (4M DR
In AM, it is required from the first generation) tRA
Smin is 80ns. Traditional processes, e.g.
In the 3-layer polysilicon + 1-layer aluminum (metal layer) process, the time remaining in the storage after the P-channel sense amplifier is activated is Vccs-4V.

V t n-1-OV s V t p m-1, CI
Only 2On under the worst condition of V s T c ==85℃
s, and it is impossible to restore it to a sufficient level.

Here, Vtn represents the threshold voltage of the N-channel transistor, and Vtp represents the threshold voltage of the P-channel transistor.

The problem of the longer time it takes to sense and amplify the potential difference between bit line pairs can be avoided by using lower resistance materials, but this also increases the complexity of the process.
Cost increases. For this reason, the tRAS
If RAS is precharged according to the minimum value, the word line closes before the potential difference between the bit line pair has been sufficiently amplified, resulting in an insufficient amount of signal being stored in the memory cell. Error This is not desirable as it will lead to deterioration of Bose characteristics.

To avoid the above problem, use the RAS timeout function to set the internal T'T'T (ff) to the above tRASmin.
It is conceivable to set the timer to keep the level low for longer than (80 ns). In this way, if the time required for closing the word line and equalizing the bit line pair is sufficient for the tRPmin, the tR
It becomes possible to sufficiently amplify the potential difference between the bit line pairs while ASmin remains at the specified value.

(Problem to be Solved by the Invention) However, if this is done, a problem arises in that another timing defined after the RAS is put into the precharge state cannot satisfy the minimum value.

For example, when the previous cycle is a cycle in which data should not be output, RAS is precharged and then CAS is
Regarding the time tRPC until the column address strobe becomes active (low level), there is a rule that data must not be output even at the minimum value Ons. Of course, even in the case of t RASmin (80 ns), the minimum value tRPcmin of the tRPC must be Ons. However, if the low level period of the internal τττ(r) is longer than tRASmin (80ns), naturally,
The above conditions cannot be met.

As described above, the conventional RAS timeout function becomes insufficient for DRAMs that are becoming more highly integrated and faster. In other words, the conventional RAS timeout function can contribute to reducing the critical timing for precharging RAS to a high level and improving the noise resistance of memory cell data. However, as the integration becomes higher and the speed becomes higher, the time required to amplify the potential difference between the bit line pairs tends to become longer.
The minimum value specification for the timing of S tends to become shorter. In response to these contradictory trends, the conventional RAS timeout function
If you try to deal with this by reducing tRP by the amount that RAS exceeds the regulation and keeping the overall tRC unchanged, another timing such as the above tRPc will be changed to tRAS.
min, the minimum value regulation cannot be met.

This kind of problem has been solved by conventional methods, which have only one type of timer.
This is due to the fact that when the external tRAS is short in this timer, the internal tRAS is generated within the tRAS specifications, and the output of the above-mentioned timer is used to control all the circuits in the DRAM.

Therefore, the present invention makes it possible to sufficiently amplify the potential difference between the bit line pairs even if RAS is precharged at tRASmin.
Another object of the present invention is to provide a dynamic memory and a dynamic memory system that can make various timings defined from outside the chip or system faster and more accurate.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention is configured to activate a word line, amplify the potential difference between a pair of bit lines, and activate the word line, which is formed from a row address strobe signal (RAS). It is formed from the input terminal of the row system RAS, which is a signal for precharging the bit line pair by making it inactive, and the RAS, and when set to the precharge level, prohibits the operation of at least a part of the column system control circuit. column-based RAS, which is a signal for
This dynamic memory is characterized in that it has input terminals on the same chip.

The present invention also provides a row address strobe signal (RAS).
and a row system RAS which is a signal for activating the word line to amplify the potential difference between the bit line pair and inactivating the word line to precharge the bit line pair. and the column system RAS, which is a signal for inhibiting at least a part of the operation of the column system control circuit, when set to the precharge level.
This dynamic memory is characterized by having a means for importing and forming a RAS from the outside within a chip. Further, the present invention provides a row address strobe signal (RA
S), which is a signal for activating the word line to amplify the potential difference between the bit line pair and inactivating the word line to precharge the bit line pair; a circuit that outputs a column system RAS which is a signal for inhibiting at least a part of the operation of the column system control circuit when the input terminal of the row system RAS is formed and the column system RAS is set to a precharge level; This is a dynamic memory system characterized by comprising: a dynamic memory having an input terminal of a dynamic memory on the same chip;

That is, in the present invention, when the RAS input becomes active, the DRA
If the RAS input is active for a certain period of time after M starts working, normal read or write operations will be performed inside the chip regardless of the level of the RAS input, and the memory cell data will be replayed without being destroyed. Dynamic memory or its system that performs a RAS timeout function such as writing or an equivalent function from outside the chip1, and divides the RAS that performs the above function into a row system and a column system. , the row system RAS performs a sufficient bit line pair restore operation, and the column system RAS performs the restore operation regardless of the row system RAS.
It enables normal read/write operations, solves problems arising in signal timing of column-related control circuits, and is also compatible with recent trends in higher integration and speed.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) and (b) show a part of the dynamic memory of the present invention. In FIG. 1(a), l is the external RAS signal, and the cover buffer is the first internal RAS signal R.
First internal RAS that generates INT (low system RAS)
3 is a second internal RAS generating circuit that generates a second internal RAS (column system RAS) signal KRINT;
4 is a first timer circuit, and 5 is a second timer circuit.

It consists of an external RAS buffer and two stages of inverters 6 and 7. The first internal RAS generation circuit 2 and the second internal RAS generation circuit 3 respectively correspond to set-reset type flip-flops FFI and FF2 formed by cross-connecting two-input NAND gates, and each set output terminal of each flip-flop. The output of each inverter 8.9 corresponds to the first
and a second internal RAS signal KRINT.

The external RAS buffer output is input to each set input terminal of each flip-flop FFI, FF2, and the output RTM of the first timer circuit 4 and the output RTM of the first timer circuit 4 are respectively input to each reset input terminal of flip-flops FFI, FF2. The output KRTM of the second timer circuit 5 is input.

The first timer circuit 4 receives a signal WDR that drives the word line.
A two-input NAND gate 10 with V as one input, a first delay circuit 11 that delays the signal WDRV by a delay time τl, and the output of this delay circuit 11 is inverted and used as the other input of the two-input NAND gate 10. an inverter 12 and an inverter 13 that inverts the output of the two-input NAND gate 10
The output of this inverter 13 is RTM.

The second timer circuit 5 receives a signal WDR that drives the word line.
A two-input NAND gate 14 whose one input is V, a second delay circuit 15 to which the signal WDRV is input and which delays it by a delay time τ2, and a second delay circuit 15 which inverts the output of this delay circuit 15 and outputs the signal WDRV to the two-input NAND gate 14. It consists of an inverter 16 which serves as the other input, and an inverter 17 which inverts the output of the two-input NAND gate 14, and the output of this inverter 17 is KRTM.

In FIG. 1(b), 21 is a row address buffer control circuit, 22 is a word line drive circuit, 23 is a row address buffer circuit, 24 is a row decoder, 25 and 26 are delay circuits, and these row-related The control circuit system is controlled by the output RINT of the first internal RAS generation circuit 2. Note that the output SEN of the delay circuit 25 is an N-channel sense amplifier activation signal, and the output SEP of the delay circuit 26 is
is a P channel sense amplifier activation signal.

Further, 27 is a column address buffer control circuit, 28 is a column address buffer circuit, 29 is a column system activation circuit, 30 is a column decoder, 31 is an address transition detection circuit, 32 is an output control circuit, and 33 is a write control circuit. , these column system control circuits are connected to the second internal ball-13.
- dominated by the output KRI NT of the generating circuit 3;

Next, the operation of the circuit shown in FIGS. 1(a) and 1(b) will be explained. The word line drive signal WDRV is initially at a low level, and when the word line drive signal WDRV rises from a low level to a high level and starts driving the word line WL, the output RTM of the first timer circuit 4 becomes a low level. rise to a high level.

Then, the flip-flop of the first internal RAS generation circuit 2, Rozzo FFI, is set, and its output RINT is output from the external RAS.
It is clamped to a low level without being affected by the S input. (RAS timeouts start to occur). After a while, the sense amplifier starts to be activated, but the signal W
When DRV goes high, the output RTM of the first timer circuit 4 falls to a low level after a delay time τ1 caused by the first delay circuit 11. At this point, the RAS timeout is canceled, and the output RINT of the first internal RAS generation circuit 2 begins to operate under the influence of the external RAS input again. The delay time τl by this first delay circuit 11 is the time required for the sense amplifier to become activated, the high level side of the bit line pair is helisdoored to the VCC potential side, and the time required for the low level side to reach a sufficient level, or the time required for the low level side to reach the Vss potential. The time taken to reach a sufficient level is set as the greater of the side helis doors. Therefore, it is possible to independently set the minimum value of the low level period of RAS by the movement of the bit line without being affected by the regulation of the minimum value of the low level period of RAS.

On the other hand, when the word line drive signal WDRV rises from a low level to a high level and starts driving the word line WL, the second
The output KRTM of the timer circuit 5 rises from low level to high level. Then, the flip-flop FF2 of the second internal RAS generation circuit 3 is set, and its output KRI
NT is clamped to a low level without being affected by external RAS input. (RAS timeouts start to occur). Then, the delay time τ due to the second delay circuit 15
After 2, the output KRTM of the second timer circuit 5 falls to a low level. At this point, RAS timeout is canceled and
[Second internal ball] The output KRINT of the v3- generation circuit 3 comes to operate under the influence of the external RAS input again.

The delay time .tau.2 by the second delay circuit 15 may be set to meet the tRASmin specification or to be a little shorter with some margin, regardless of the bit line storage state. In other words, even if a short RAS low level period is input to this DRAM from the outside (of course,
(must be longer than the period from the falling edge of RAS to the rising edge of signal WDRV), the internal RAS low level period is set to a specified minimum value, - generally, rl > tRASmin≧ The relationship τ2 holds true.

According to the DRAM of the above embodiment, even if the DRAM is operated at tRASmin specified in the specifications, the internal R
By shifting the AS, the restoration time can be extended to about 4Qns, so high speed can be achieved without deteriorating soft errors or pause characteristics due to insufficient bit line storage. In addition, since the column system circuit is controlled by the timer 15 having the relationship rl<τ2, the operation of the column system control circuit can be inhibited by setting the column RAS (second internal RAS) to the precharge level at an early point. This eliminates erroneous writes and reads, ensures normal write/read operations, and contributes to reducing critical timing, which is one of the purposes of the RAS timeout function.

FIG. 2(a) is a RAS timeout circuit diagram with three timers according to another embodiment of the present invention, and three output signals R
INTI, RINT2 and RINT3 are divided and input to each circuit block of the DRAM as shown in FIG. 2(b). Here, the same reference numerals are used for parts corresponding to those in the previous embodiment, and appropriate subscripts are added. Timer 4 of this circuit.
The signal RINTI obtained by is the row system RAS, and the signals ff and m- obtained by timers 4□ and 43 are the column system ■τ
It is I.

That is, first timer 4. starts operating after the word line drive signal WDRV rises, and is turned off after the time τ1 until the bit line is sufficiently restored. During this period, RINTI continues to maintain a low level regardless of the voltage value of external signal RAS.

As shown in FIG. 2(b), RINTI is input to the row address buffer control circuit 21 and the word line drive circuit 22, and even if tRAS (the period during which RAS is at low level) is shortened, the level of the word line remains unchanged. Time to rise (WDRV)
If it is longer than the time when the bit line rises, the word line is closed after waiting until the bit line is sufficiently restored, and then the bit line is equalized (made to have the same potential). Equalization of the bi-soto lines is performed by the output signal of the row address buffer 23. On the other hand, the output signal RINT2 controlled by the second timer 4° is input to the column address bar sofa control circuit 27 and the column system control circuit 29, as shown in FIG. 2(b). This signal is RINT
Similarly to I, when the external signal m is set to low level, it becomes low level, and when the word line drive signal WDRV rises, the second timer 4□ starts operating, so it does not depend on the voltage value of the external signal RAS. Continue to maintain low level.

Then, when a time constant τ2 shorter than the time constant τl of the first timer 41 has elapsed, the timer 42 is cut off, and RINT2 becomes synchronized with the external RAS.

The time when this timer 4□ expires is tRASm of DRAM.
It matches the specification value of in, or is set somewhat short with some margin. In other words, the second timer 42 guarantees that DRAM can be read/written normally even if tRAS is controlled to be short.
This contributes to reducing critical timing, which is one of the purposes of the AS timeout function.

A further feature of this embodiment is that it incorporates another third timer 43. In this embodiment, a third timer 4. The time constant τ3 of is set to τ2<τ3<τ1. This timer 4. The output signal RIN is dominated by
T3 is input to the column decoder 30 as shown in FIG. 2(b), and when tRAS is input briefly, the internal RAS signal RI NT2 input to the column address buffer control circuit 27 and column control circuit 29 is first input. is reset to high level, but for a while from this point on, the internal RAS signal R input to the column decoder
In order to keep INT3 low level, the column select line (C
SL) remains selected. However, it is set to be reset earlier than the internal RAS signal RINT1 input to the row address buffer control circuit 21 and the word line drive circuit 22 (τ3<τ1).

The reason for this is that the column select line CSL is
If it is reset at the same time as reset of 2, tRASmi
When inputting RAS with n, CSL is reset before the write operation is completed, the write operation becomes incomplete, and writing may become impossible. Conversely, if the column select line C3L is reset at the same time as RINTI is reset, there is not enough time between the bit line floating on the "0" side and the word line closing, and the signal to be rewritten to the cell will not be available. The quantity may decrease and lead to defects. The above floating bit line on the "0" side means that the DQ line (C8L is connected to the bit line when C8L is at a high level) is connected to the bit line in order to protect the memory cell data against multiple selections of the column select line SCL. A P-channel type load transistor is attached to the DQ line,
This means that the "0" level on both bit lines floats around 1 volt. However, if RAS is set to the precharge level with tRAS appropriately large, the bit line storage is already progressing, so even if the word line is closed and the floating on the "0" side is not completely settled, the signal level will still be high. Since a sufficient amount of can be secured, it will not become defective.

According to the above embodiment, the following advantages can be obtained. That is, as DRAMs become highly integrated and require high-speed operation, when the DRAM is controlled using the minimum value of tRAS, bit line restoration may be insufficient, resulting in failure. In this embodiment, since there is a margin in the RAS precharge time tRP, the timer 41 in the chip extends tRAS while keeping the RAS cycle time tRC defined by equation (1) above at a constant value. By making this possible, it is possible to realize a high-speed DRAM in which bit line restoration can be performed satisfactorily. In addition, in order to ensure that tRASmin also satisfies the timing spec defined from the rise of RAS (prohibiting column-related operations), RINT2, which is controlled by a timer 42 that expires earlier than tRASmin, is installed in the column-related circuit. input.

However, if the column selection line falls at this timing, there is a risk that the write operation will be insufficient and a write failure will occur. On the other hand, if C8L is pulled down (reset) at the same time as RINTI rises, there is a risk that the "0" side of the bit line will be insufficiently stored and a failure will occur. Therefore, C.S.L.
The RINT3 signal that causes RINT3 to fall is set to reset earlier than RINTI and later than RINT2,
The amount of signal restored within the cell can be increased while ensuring normal operation.

FIG. 3 shows another embodiment of the present invention, and FIG. 3(a) shows an internal RA
The S generating circuit, shown in FIG. 3(b), is the circuit portion that receives the signal. Here, parts corresponding to the embodiment shown in FIG. 1 are given the same reference numerals.

The purpose of this circuit is to set the time constant τ of RAS timeout timer 4 longer than the specification of tRASmin, so that even if the DRAM is operated at tRASmin, sufficient bit line storage can be performed. tRP
(RAS precharge time) has a margin, so even if internal tRAS is longer than tRASmin and creeps toward tRP, the specification of tRC (RAS cycle time) can be met. However, if this continues, the timing specifications defined from the time of RAS precharge will not be satisfied by tRASmin, so the column address buffer control circuit 27, which is not related to bit line restoration,
The column system control circuit 29 is not controlled by the timer 4, and is configured to directly receive control of the external rXI from the buffer 1.

This embodiment will be explained along with FIG. 3(a) and FIG. 3(b). As shown in FIG. 3(a), the external RAS of the DRAM is received by the buffer 1, and the internal RAS word line drive signal WDR is
When V rises, this signal no longer accepts the control of the external RAS, continues to maintain a low level state, and after the time τ has elapsed until the bit line is sufficiently restored, it becomes controlled by the external RAS again. This RINT-1
As shown in FIG. 3(b), is input only to the row address buffer control circuit 21 and the word line drive circuit 22, and even if the DRAM is operated at tRASmin, it will wait for enough time to perform bit line restoration. After that, the word line is closed, and then the bit line is equalized. (Bit line equalization is performed by the output signal of the row address buffer 23.) On the other hand, KRINT-1
It is completely synchronized with E-, as shown in Fig. 3(b).
It is input to a column address buffer control circuit 27 and a column system control circuit 29. As a result, the timing spec specified from the time of RAS precharge is changed to tR.
We are trying to satisfy even ASmin. In other words, the above τ
Despite its size, KRINT-1 can independently control the operation of column system control circuits. A typical example of the above timing is tRPC (RAS), as shown in Figure 4.
to CAS Prcharge Time
) and tRRH (ReadCommand Ho
1d Time Reference to
RAS). tRPC is defined as the time from when RAS is placed in a precharge state until when CAS is placed in an actup state. Therefore, even if tRPcmin-0 at the end of a cycle other than read (for example, at the end of RAS only refresh),
There is a regulation that data DOUT must not be output via the output buffer 34. Of course, tRASmin must also comply with this regulation. This regulation must be observed in the area 41 within the broken line in the graph of FIG. In other words, in this region 41, DOUT must be in an oven state (no output). If the column address buffer 27 and column system control circuit 29 also
The above RINT- with a longer timer than RASmin
1, the result will be a shmoo as shown in FIG. 6, and there will be a region 42 where some specifications cannot be met. This is because RINT-1 rises slowly,
This is a pass where the fail area 43 increases. According to this embodiment (FIG. 3(b)), the shmoo as shown in FIG. 7 is obtained, and KRINT-1 is no longer involved in RINT-1,
Since the fail area can be formed as 43', the specifications can be met. tRRH is defined as the time from precharging RAS to activating write enable signal WE. This timing is also t
Similar to RPC, it is specified that even if tRRHmin=0, a write operation must not be entered by mistake. In this case, the column address buffer 28 and column system control circuit 29 are also connected to the RI.
If controlled by NT-1, tRASmin will not be able to satisfy this specification, but in Fig. 3(b), KRI
Since it is controlled by NT-1, the write operation specifications can also be satisfied.

That is, the above embodiment has the following advantages.

As mentioned above, the bit line restore time is longer than that of conventional DRA.
In M, it is within the minimum value of tRAS (RAS pulse width), and the RAS timeout function ■ Eliminates the critical timing of RAS precharge, making it easier for users to use ■ Preventing data from being destroyed by noise received by RAS It had only the passive function of preventing.

However, DRAM is gradually being required to become faster.
The minimum value of tRAS is also required to be as short as 80 ns or 60 ns. At the same time, as the capacity of DRAM increases, the time required for bit line storage generally tends to increase.

Under such circumstances, it becomes necessary to give RAS timeout another positive meaning. In other words, even if the user controls the DRAM with the minimum value of tRAS, it is necessary to have a long timer inside the chip and restore the bit lines sufficiently. Regarding tRP (RAS precharge time), the actual value has a margin compared to the minimum value of the specifications, so
Even if such a long timer is provided, the RA of equation (1)
The cycle time tRC of S can be kept unchanged. In other words, the degree of freedom in dividing tRC into tRAS and tRP has increased.

However, in such a RAM, if column circuits other than bit lines and word lines are also under the control of this long timer, various timing specifications (tRPC, tRRH, etc.) defined from the rise of RAS will be changed to tRAS.
becomes difficult to satisfy at the minimum value of . Therefore, this problem can be solved by directly inputting a signal synchronized with an external RAS to these column systems. Therefore, the effect of this embodiment is that by perfecting the bit line restoration of high-speed, high-density DRAM, it is possible to restore the soft error rate and pause characteristics, which deteriorate due to a decrease in data amount, to normal values. That's true.

FIG. 8 shows each of the above embodiments in a simplified manner.

That is, FIG. 8(a) shows a simplified version of the embodiment shown in FIGS. 1(a) and (b), in which the external RAS is taken into the chip 51, and the low system RAS is A signal RINT is obtained, and a column system RAS signal KRINT is obtained using a timer 5 within the chip 51.

FIG. 8(b) shows a simplified version of the embodiment shown in FIGS. 2(a) and 2(b), in which the external RAS is taken into the chip 52, and the low system RAS signal is sent using the timer 41 within the chip. R
I am getting INTI.

FIG. 8(c) is a simplified version of the embodiment of FIGS. 3(a) and (bo), in which a column system using the timer 42 in the chip 52 is used. Low system ■τT signal 'FrF using timer 4 in the chip
'r-1, and also directly imports the external RAS into the chip 53 and converts it into the column system RAS signal KRI NT-.
It is used as 1.

Figure 9 shows a dynamic memory system.
In FIG. 9(a), the low system RAS signal RI of FIG. 8(a)
NT is obtained by the timer 4 of the chip 61 outside the chip 51 and introduced into the input terminal 65 of the chip 51, and the column system RAS signal KRINT is obtained by the timer 5 of the chip 61 and introduced into the input terminal of the chip 51. It is introduced into the terminal 64 and used in the same manner as described above. In this case the signal RINT,
KRINT may be obtained from a circuit other than the chip 61.

In FIG. 9(b), the signals RINTI, R of FIG. 8(b)
INT2 and RINT3 are connected to the timers 41 and 4 of the chip 62.
,4. and input terminals 66, 67 . of chip 52, respectively.
68 and is being used in the same way. In this case as well, it may be obtained from another circuit.

In FIG. 9(c), the signal RI NT-1 of FIG. 8(c)
, KRI NT-1 are obtained on chip 63, and are introduced into input terminals 69 and 70 of chip 53, respectively, and used in the same manner. In this case as well, the signal RI NT-1
, KRINT-1 may be obtained from a circuit other than the chip 63.

FIG. 10 shows another embodiment of the timer circuit for obtaining the row-related RAS signal RINT, and FIG. 10(a) corresponds to that in FIG. 1(a). FIG. 10(b) is a modification of FIG. 10(a), in which both the external RAS and the internal RAS generating circuit 2 and the timer circuit 4 are modified. Figure 10 (C
) is the one in which the flip-flop part of the internal RAS generation circuit 2 in FIG. 10(a) is replaced with a Nant gate 71,
FIG. 10(d) is similar to FIG. 10(b) in which the flip-flop portion is replaced with a NOR gate 72.

FIG. 10(e) is the same as in FIG. 10(a) with the addition of a circuit 81 that prevents the low system from being reset during the write period, and m is at a low level (“0”) during the write period. signal,
FIG. 10(f) shows a modification of the timer circuit 4 and reset prevention circuit 81 shown in FIG. 10(e). The same thing as shown in FIG. 10 can be said when obtaining a column-based RAS signal.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can of course be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As explained above, the present invention provides a dynamic memory and a memory having advantages such as being able to improve the problem of bit line data storage and making the circuit operation based on each RAS timing faster and more accurate. This system can be provided.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figures 2 and 3 are circuit diagrams showing one embodiment of the present invention.
The figures are circuit diagrams showing different embodiments of the present invention, Fig. 4 is a timing chart of the same, Figs. Fig. 10 is a diagram showing the configuration as shown in Figure 10. Fig. 14 is a timing chart in the dynamic memory.
S generation circuit, 3.3.3□... Column system RAS generation circuit, 4.4□, 4□, 43... Timer circuit, 5...
Timer circuit, 6 to 9... Inverter, 11... Delay circuit, 15.151, 15□... Delay circuit, FFI,
FF2...Set-reset type flip-flop, 21
. . . row address buffer control circuit, 22 . . . word line drive circuit, 23 . . . row address buffer circuit,
24... Row decoder, 25.26... Delay circuit,
27... Column address buffer control circuit, 28...
- Column address buffer circuit, 29... Column system activation circuit, 30... Column decoder, 31... Address transition detection circuit, 32... Output control circuit, 33...
-Write control circuit, 51-53.62-63...chip, 64-70...input terminal. Applicant's agent Patent attorney Takehiko Suzue (a) Figure 10 (a) (b) (C) Figure (a) (b) Figure 10

Claims (13)

[Claims] (1) A signal formed from a row address strobe signal (RAS) that activates a word line to amplify the potential difference between the bit line pair and deactivates the word line to precharge the bit line pair. Low type R
An input terminal of the AS and an input terminal of the column system RAS, which is formed from the RAS and is a signal for inhibiting at least a part of the operation of the column system control circuit when set to a precharge level, are provided on the same chip. Dynamic memory is characterized by: (2) A signal formed from a row address strobe signal (RAS) that activates a word line to amplify the potential difference between the bit line pair and deactivates the word line to precharge the bit line pair. Low type R
AS and a column system RAS, which is formed from the RAS and is a signal for inhibiting at least a part of the operation of the column system control circuit when set to a precharge level, are taken in from the outside within one chip. A dynamic memory characterized by comprising means for forming. (3) The dynamic memory according to claim 2, wherein the row system RAS is controlled by a first timer having a time constant necessary for amplifying the potential difference between the bit line pair. . (4) The row system RAS is controlled by a first timer having a time constant τ1 necessary for amplifying the potential difference between the bit line pairs, and the column system RAS is controlled by a minimum value tRASmin of the RAS active period. , or with a slightly shorter time constant τ2 (<τ1)
3. The dynamic memory according to claim 2, wherein the dynamic memory is controlled by a timer. (5) External row address strobe signal (RAS)
) There are two types of timers that start working when the input is active for a certain period of time, and forcibly set the internal RAS generated inside the memory chip to remain active without accepting the RKAS input for another certain period. Of these two types of timers, the first timer has a long time constant τ1 that waits for the amplification of the potential difference between the bit line pair, and the second timer has a long time constant τ1 that waits for the amplification of the potential difference between the bit line pairs. The row system RAS output from the first timer has a short time constant τ2 (<τ1) that is set somewhat short by taking . The column-related RAS, which controls at least a part of it and outputs it from the second timer, controls at least part of the column-related control circuit system including a column-related activation circuit, an address transition detection circuit, an output control circuit, and a write control circuit. What is claimed is: 1. A dynamic memory that controls a column-related control circuit and inhibits operation of the controlled column-related control circuit when a column-related RAS reaches a precharge level. (6) External row address strobe signal (RAS)
) is activated for a certain period or more, and there is a first timer that forcibly sets the internal RAS generated inside the memory chip to be active without accepting the RAS input for another certain period, This timer has a time constant τ1 that waits for the amplification of the potential difference between the bit line pair, and the output signal from the first timer is transmitted to at least one of the row control circuits including the row address buffer control circuit and the word line drive circuit. At least a part of the column system control circuit, including the column system activation circuit, address transition detection circuit, output control circuit, and write control circuit, has a minimum value of the RAS active period that is smaller than τ1. tRASm
A signal controlled by a second timer having a short time constant τ2 that meets the specifications of in or is set somewhat short with some margin is input, and the column decoder or the circuit that controls it is supplied with the signal controlled by the second timer. A dynamic memory characterized in that a signal controlled by a third timer having a time constant τ3 shorter than τ1 but longer than τ2 is input. (7) External row address strobe signal (RAS)
) is activated for a certain period of time, and there is a timer that forcibly sets the internal RAS generated inside the memory chip to be active without accepting the above RAS input for another certain period of time. The output signal from the timer has a time constant to wait for the amplification of the potential difference between the bit line pair, and is input to the row control circuit system including the row address buffer control circuit and word line drive circuit, and is input to the column system activation circuit and the column system activation circuit. It is not input to the column control circuit system including the address transition detection circuit, output control circuit, and write control circuit, and instead, the external RA is input to the column control circuit system.
A dynamic memory characterized in that a signal synchronized with S is directly input. (8) A signal formed from a row address strobe signal (RAS) for activating a word line to amplify the potential difference between the bit line pair and inactivating the word line to precharge the bit line pair. Low type R
AS, and a circuit that is formed from the RAS and outputs a column system RAS which is a signal for inhibiting at least a part of the operation of the column system control circuit when set to a precharge level; an input of the row system RAS; terminal and the column system RA
1. A dynamic memory system comprising: a dynamic memory having an S input terminal on the same chip. (9) The dynamic memory according to claim 8, wherein the row system RAS is controlled by a first timer having a time constant necessary for amplifying a potential difference between a pair of bit lines. system. (10) The row system RAS is controlled by a first timer having a time constant τ1 necessary for amplifying the potential difference between the bit line pair, and the column system RAS is controlled by a minimum value tRASmin of the RAS active period. 9. The dynamic memory system according to claim 8, wherein the dynamic memory system is controlled by a second timer having a time constant τ2 (<τ1) that matches or is somewhat short with a margin. (11) The dynamic memory starts working when the row address strobe signal (RAS) input becomes active for a certain period or more, and forces the internal RAS to remain active without accepting the RAS input for another certain period. There are two types of timers to be set outside one chip. Of these two types of timers, the first timer has a long time constant τ1 that waits for the potential difference between the bit line pair to be amplified, and the second timer has a long time constant τ1 that waits for the amplification of the potential difference between the bit line pair. The row system RAS output from the first timer has a short time constant τ2 (<τ1) that meets the minimum value tRASmin regulation or is set somewhat short with some margin, and the row system RAS output from the first timer is connected to the row address buffer control circuit and the word The column system RAS that controls at least a part of the row system control circuit system including the line drive circuit and outputs from the second timer is a column system activation circuit, an address transition detection circuit, an output control circuit, and a write control circuit. controlling at least a part of a column system control circuit system including a column system RAS, and inhibiting the operation of the column system control circuit being controlled when the column system RAS reaches a precharge level. 9. The dynamic memory system according to claim 8. (12) The dynamic memory starts working when the row address strobe signal (RAS) becomes active for a certain period of time, and forcibly sets the internal RAS to remain active without accepting the RAS input for another certain period. A first timer is provided outside the chip, the first timer has a time constant τ1 for waiting for amplification of the potential difference between the bit line pair, and the row system RAS which is the output from the first timer is
is input to the row control circuit system including the row address buffer control circuit and word line drive circuit, and is input to the column system control circuit system including the column activation circuit, address transition detection circuit, output control circuit, and write control circuit. In the system, the above τ1
smaller than the minimum value of the RAS active period tRAS
The first column system R is a signal controlled by the second timer outside the chip, which has a short time constant τ2 that meets the min specifications or is set somewhat short with some margin.
AS is input to the column decoder or the circuit that controls it, and a second signal controlled by a third timer outside the chip having a time constant τ3 shorter than τ1 but longer than τ2 is input. 9. The dynamic memory system according to claim 8, wherein the column-based RAS is inputted. (13) The dynamic memory starts working when the row address strobe signal (RAS) becomes active for a certain period or more, and forcibly sets the internal RAS to remain active without accepting the RAS input for another certain period. There is a timer outside the chip, and the timer has a time constant that waits for the amplification of the potential difference between the bit line pair.The row system RAS, which is the output from the timer, is used for the row system including the row address buffer control circuit and the word line drive circuit. It is not input to the column system control circuit system including the column system activation circuit, address transition detection circuit, output control circuit, and write control circuit, but instead is input to the column system control circuit system. The column system RA is a signal that synchronizes with the external RAS.
Claim 8 characterized in that S is directly input.
Dynamic memory system described in .