JPS634485A - Memory access system - Google Patents

Abstract

PURPOSE:To use a comparatively low speed memory as an external memory of a high-speed processor by applying memory access to a memory device using an address signal stored in one address latch circuit and an operation supplying an address signal for the next memory cycle to the other address latch circuit in parallel. CONSTITUTION:An address signal RA1 outputted from a processor ACRT synchronously with the low level of the inverse of an address strobe signal AS in a memory cycle K is fetched in address latch circuits A1H, A1L by the low level of an address strobe signal AS1. The following operations are executed in parallel in the next memory cycle (K+1); that is, an address signal WA1 outputted from the processor ACRTC synchronously with an address strobe signal AS2 is fetched in address latch circuits A2H, A2L by the low level of the address strobe signal AS2. The address signal RA1 fetched already in the preceding memory cycle K is used for the access of a memory device DRAM in the memory cycle K+1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory access method, and includes, for example, an information processing device such as a graphic processor, and a dynamic RAM (random access memory). The present invention relates to a technique effective for use in an image processing device including a frame memory.

[Conventional technology]

In processors that transmit address signals and data signals in a time-sharing manner, such as graphics processors that generate graphic signals for drawing graphics on the screen of a CRT (cathode ray tube), memory is An address signal is supplied to the device, and in the second half, the reading signal is taken in or the write data is supplied. Regarding such graphic processors, for example, ``8/16-bit Microcomputer Peripheral LSIJ'' published by Hitachi, Ltd. in September 1985 is available.

[Problem that the invention seeks to solve]

In the above-mentioned processor, the processor itself requires a minimum output delay time for the address signal and a set-up time for read data. Therefore, within one memory cycle, the time available for accessing the memory device is the time obtained by subtracting the above time. Therefore, if the system clock frequency is increased to increase processing speed, the memory cycle will be shortened.
The time allowed for accessing the memory device has become shorter (as a result, general-purpose low-cost memory devices such as dynamic RAM require relatively long access times, so the above-mentioned It cannot be used as a memory device for high-speed processors.

An object of the present invention is to provide a memory access method that makes it possible to use a memory device with a relatively slow operating speed as an external memory for a high-speed processor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by providing first and second address latch circuits that capture address signals supplied from the information processing device through the address bus at different timings, it is possible to capture address signals already during one memory cycle. Memory access to the memory device using the address signal held in one of the address latch circuits and the operation of supplying the address signal for the next memory cycle to the other address latch circuit are performed in parallel. It is.

[For production]

According to the above-described means, since the output delay time of the address signal in the information processing device can be substantially ignored, this time can be used as the memory access time.

This makes it possible to use a relatively low-speed memory device as an external memory for an information processing device that operates at high speed.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention. The processor ACRTC is a graphics processor such as, but not limited to, 'HD63484J. This processor ACRTC outputs an address signal AD and sends/receives data DA to/from a bus BUS in a time division manner.The memory device DRAM is a dynamic type RAM and constitutes a frame memory of the processor ACRTC.

The above-mentioned processor ACRTC performs a high-speed operation in response to a clock signal CLK set to a high frequency such as 8MH2.
In order to perform this for AM, the following memory access circuit is provided.

The first address latch circuits AIH and AIL are connected to the bus BU
The upper address signal and lower address signal supplied to S,
In other words, it corresponds to the row (X) address signal and column (Y) address signal for the dynamic RAM. Second address latch circuits A2H and A2L
Also takes in the address signal from the bus BUS in the same manner as above.

Although not particularly limited, processor A CRT Cit,
It is sent out as an address signal supplied to the bus BUS in synchronization with two address strobe signals SAI and SA2. These address strobe signals SAI and SA2 are
It is output corresponding to the first and second address latch circuits AIH, AIL and A2H, A2L. That is, when address strobe signal ASI is set to low level,
The control signal supplied to the gate terminal G of the first address latch circuit AIH, AIL through the inverter circuit N1 becomes high level, and the address signal AD output to the bus BUS is taken into the first address latch circuit AIH, ALL. It will be done. Further, when the address strobe signal AS2 is set to low level, the second
The control signals supplied to the gate terminals G of the address latch circuits A2H and A2L become high level, and the address signal AD output to the bus BUS becomes the second address latch circuit A2)'1. It is taken into A2L.

The memory control circuit CON↑ is connected to the above processor ACRTC.
The address strobe signal AS1. AS2
, read/write signal R/W, memory cycle signal MC
In response to the above clock signal CLK, the memory device DR
Control signal for AM and the address latch circuit AI
H, AIL and A2H, A2L output timing signals are formed.

The memory control circuit C0NT outputs the address strobe signals AS1. A.S.
2 and the memory cycle signal MC, the memory device DRAM
The address signal for access is determined and control signals OC1, QC2 and H/L are formed. Control signal OCI
and OC2 are output control signals of the address latch circuits AIH, ALL and address latch circuits A2H, A2L. The control I signal H/L is the address latch circuit A.
The output of either the upper address signal or the lower address signal from IH to A2L is taken as fAm+ signal. That is, the control signal OCI is supplied to one input terminal of the OR gate circuits G1 and G2. A control signal H/L is supplied to the other input of the OR gate circuit G1 via an inverter circuit N3. The above OR gate circuit G2
The control signal H/L is supplied as is to the other input. The output signals of the above OR gate circuits G1 and G2 are:
It is supplied to the output control terminals OC of the first address latch circuits AIH and AIL. Similarly, control signal OC2 is supplied to one input terminal of OR gate circuits G3 and G4. A control signal H/L is supplied to the other input of the OR gate circuit G3 via an inverter circuit N4. The other input of the OR gate circuit G4 is connected to the control signal H.
/L is supplied as is. The above OR gate circuit.

The output signals of G3 and 05 are sent to the second address latch circuit A.
It is supplied to the output control terminals OC of 2H and A2L.

As a result, in a certain memory cycle, the address signals held in the first address latch circuits AIH and AIL are chronologically connected to the common address terminal AD of the memory device DRAM according to the low level/high level of the control signal H/L. Supplied via address bus. Then, in the next memory cycle, the second address latch circuit A2H,
The address signal held in A2L is supplied in time series to the address terminal AD of the memory device gDRAM via the common address bus in accordance with the control signal H/L as described above.

The switching timing of the above-mentioned [i signal H/L between low level and high level corresponds to the row address strobe signal RAS and column address strobe signal CAS supplied from the beam memory control circuit C0NT to the memory device DRAM.

The memory control device Ic0NT receives read/write signals R/
In response to W, a write enable signal WE is generated to be supplied to the memory device DRAM in accordance with the timing of actual memory access.

A data terminal DA of the memory device DRAM is coupled to one input/output terminal of a bidirectional data bus driver DBD via a data bus. This data bus driver DB
The other input/output terminal of D is the bus BU on the processor side.
It is connected to S. The data transmission direction of the data bus driver DBD is controlled in accordance with a signal supplied from the memory control circuit C0NT to the control@child DIR.

Next, a memory access method of the memory device DRAM by the processor ACRTC will be described with reference to the timing diagram shown in FIG.

In a certain memory cycle K, the address strobe (
In synchronization with the low level of word SA1, processor ACRT
Address signal RA1 output from C is taken into address latch circuits AIH and AIL by the low level of address strobe signal ASI.

At the next memory cycle +1, the following operations are performed in parallel. In other words, address strobe buoy No. 8A
The address signal WAI output from the processor ACRTC in synchronization with S2 is the address strobe signal AS.
Address latch circuit A2H, A2 due to the low level of
It is taken into L. The address signal RAI already captured in the previous memory cycle K is used to access the memory device fiDRAM in this memory cycle +1. The memory control circuit C0NT sets an output control signal OC1 (not shown) to a low level. At this time, due to the high level of the control signal H/L (not shown), the output signal of the OR gate circuit G2 becomes high level, and the output of the first launch circuit ALL is brought into a high impedance state, and due to the high level of the control signal OC2. Since the output signals of the OR gate circuits G3 and G4 become high level and the outputs of the second address latch circuits A2)1 and A2L are brought into a high impedance state, the upper The address signal (row address signal X) of the memory device DRAM
is supplied to the address terminal AD of. Above control signal H/L
is set at high level, and the switching from high level to low level is synchronized with the timing at which column address strobe signal CAS is changed from high level to low level. By switching the 1iOf1m signal H/L to the low level, the output of the first address latch circuit AIH is brought into a high impedance state, and the address latch circuit AIL is brought into operation.
The lower address signal (column address signal Y) taken into the address latch circuit AIL is transferred to the memory device DR.
It is supplied to the address terminal AD of AM.

Such addressing for the memory device DRAM is performed immediately from the beginning of +1 in this memory cycle since the address signal RAI has already been taken into the address latch circuits AIH and AIL as described above. Such a memory access operation enables memory access that substantially ignores the output delay time of the address signal from the processor ACRTC. In other words, at +1 to this memory cycle,
Memory access can be performed with substantially zero address output delay time from the processor ACRTC. As a result, for example, a read/write signal R/W instructing a read operation is generated 7J after the output of the address signal RAI.
is sent out, the memory control circuit C0NT stores it and sets the write enable signal WE to high level read mode. Therefore, the read signal RDI sent from the data terminal DA is sent to the processor via the data bus driver. Sent to ACRTC. Processor ACR
The TC can take in the read signal RDI in synchronization with the falling edge of the clock signal CLK in the second half of +1 in the memory cycle.

At the next memory cycle +2, the following operations are performed in parallel. That is, the address strobe signal AS
The address signal RA2 output from the processor ACRTC in synchronization with the address strobe signal ASI
address latch circuits AIH, AIL due to the low level of
be taken in. The address signal WAI, already taken in at +1 in the previous memory cycle, is used for accessing the memory device DRAM at +2 in this memory cycle. The memory control circuit C0NT sets an output control signal OC2 (not shown) to a low level. At this time, tJl? The high level of the control signal OCI causes the output signal of the OR gate circuit G4 to go high and the output of the second latch circuit A2L to be in a high impedance state, and the high level of the control signal OCI causes the output signal of the OR gate circuit G1 to go high. and G2 output signals become high level, and the first address latch circuits AIH and A2
1 is brought into a high impedance state, the upper address signal (row address signal X) taken into the second address latch circuit A2H is supplied to the address terminal AD of the memory device DRAM. Similarly to the above, the control signal H/L is set to high level, and switching from high level to low level is synchronized with the timing at which column address strobe signal CAs is changed from high level to low level. By switching the control signal H/L to the low level, the output of the second address latch circuit A2H is brought into a high impedance state,
Since the address latch circuit A2L is activated, the lower address signal (column address signal Y) taken into the address latch circuit ALL is transferred to the memory device D.
It is supplied to the address terminal AD of the RAM.

Addressing the memory device DRAM as described above is performed immediately from the beginning of +2 in this memory cycle as described above. If W is sent out, the memory control circuit C0NT stores it and sets the write enable signal WE to low level write mode, so the processor ACRT
The write signal WDI sent from C is sent to the data terminal DA of the memory device DRAM via the data bus driver DBD, thereby performing a write operation to the memory device DRAM.

Hereinafter, by similar operation, in memory cycles after +3, etc., the processor ACRTC sends an address signal to one address latch circuit, and the other address latch circuit sends out an address signal to the other address latch circuit. Access operations are performed in parallel.

In such a memory access method, since the address output delay time from the processor side can be reduced to virtually zero, the time used for memory access operations during one memory cycle can be lengthened (because it is possible to It is possible to use a memory device that requires a relatively long memory access time, such as a dynamic RAM, or in other words, a low speed memory device, as an external memory device for the high speed processor.

The effects obtained from the above examples are as follows.

(1) First and second address latch circuits are provided to capture address signals supplied from a high-speed processor through a bus at different timings, and the address signal is already captured during one memory cycle. By parallelly performing memory access to a memory device using an address signal held in one address latch circuit and supplying an address signal for the next memory cycle to the other address latch circuit. , it is possible to substantially reduce the output delay time of the address signal in the processor to zero. This allows the output delay time of the address signal on the processor side to be used as the memory access time, resulting in the effect that relatively low-speed access to the memory device can be achieved.

(2) According to (1) above, it is possible to use a general-purpose low-speed memory device as an external memory device for a high-speed processor without sacrificing its processing speed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, when a processor does not have two address strobe signals, a frequency divider circuit or a counting circuit that receives the address strobe signal is provided on the memory control circuit C0NT side to generate the address strobe signals that are alternately generated as described above. In addition, when the memory device has independent X and Y address terminals like a static type RAM, the output control of the address latch circuit is performed using the above control signal H/L.
is considered unnecessary. The above-mentioned processor outputs address signals and sends and receives data signals in a time-series manner using a common bus as in the above embodiment, and also outputs and sends and receives respective signals using an address bus and a data bus. It may be.

Furthermore, the names of the respective signal terminals and control signals for the processor and memory device may be those having substantially the same functions as those described above.

The present invention can be widely used as a memory access method in an information processing system that includes a processor that performs various information processing operations and its external memory device.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by providing first and second address latch circuits that respectively take in address signals supplied from a high-speed processor through a bus, one of the address latch circuits that has already taken in an address signal during a certain memory cycle By performing in parallel the memory access to the memory device using the address signal held in the address latch circuit and the operation of supplying the address signal for the next memory cycle to the other address latch circuit,
The output delay time of the address signal in the processor circuit can be substantially reduced to zero. This allows relatively slow access to the memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining an example of its operation. ACRTC...processor, DRAM...memory device,
C0NT...Memory control circuit, AIH. AIL, A2B, A2L...address latch circuit, DB
D...Bidirectional data puff driver, N1-N4...Inverter circuit, Gl-G4...Nant gate circuit °n

Claims (1)

[Scope of Claims] 1. First and second address latch circuits each receiving address signals supplied from an information processing device through an address bus at different timings, and receiving control signals supplied from the information processing device. , a control circuit that forms a control signal for the memory device, the first and second address latch circuits, and a control signal for the bidirectional data bus driver, and the address signal is already taken in during one memory cycle. A memory access to a memory device using an address signal held in one of the address latch circuits and an operation of supplying an address signal for the next memory cycle to the other address latch circuit are performed in parallel. Characteristic memory access method. 2. Claim 1, wherein the information processing device is a graphic processor that uses a common bus for time-sharing address signals and data signals, and the memory device is a dynamic RAM. Memory access method described.