JPH04121753U - Plug-in type semiconductor device storage package - Google Patents
Plug-in type semiconductor device storage packageInfo
- Publication number
- JPH04121753U JPH04121753U JP1991026930U JP2693091U JPH04121753U JP H04121753 U JPH04121753 U JP H04121753U JP 1991026930 U JP1991026930 U JP 1991026930U JP 2693091 U JP2693091 U JP 2693091U JP H04121753 U JPH04121753 U JP H04121753U
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead pin
- external
- plug
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000003860 storage Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 24
- 239000002184 metal Substances 0.000 abstract description 24
- 238000009713 electroplating Methods 0.000 abstract description 10
- 239000002245 particle Substances 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000002023 wood Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ODINCKMPIJJUCX-UHFFFAOYSA-N Calcium oxide Chemical compound [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】外部リードピンの外表面に電解メッキ方法によ
りメッキ金属層を層着させたとしても外部リードピンの
全体径を略均一となし、外部電気回路との接続を容易、
且つ確実となすことのできるプラグイン型半導体素子収
納用パッケージを提供することにある。
【構成】絶縁基体１の一主面に周列状に取着した外部リ
ードピン7 のうち最外周角部に位置する外部リードピン
7 の外側にダミーの外部リードピン7aを取着した。ダミ
ーの外部リードピン7aによって電解メッキの際の荷電粒
子が各外部リードピン7 の先端に集中するのが有効に防
止され、その結果、各外部リードピン7 には略同一厚み
のメッキ金属層が層着される。
(57) [Summary] [Purpose] Even if a plated metal layer is deposited on the outer surface of the external lead pin by electrolytic plating, the overall diameter of the external lead pin can be made approximately uniform, facilitating connection with an external electric circuit.
Another object of the present invention is to provide a plug-in type semiconductor element storage package that can be manufactured reliably. [Structure] External lead pin located at the outermost corner of the external lead pins 7 attached in a circumferential row on one main surface of the insulating base 1
A dummy external lead pin 7a was attached to the outside of 7. The dummy external lead pins 7a effectively prevent charged particles during electrolytic plating from concentrating on the tips of each external lead pin 7, and as a result, each external lead pin 7 is coated with a plating metal layer of approximately the same thickness. Ru.
Description
【０００１】0001
本考案は半導体素子を収容するための半導体素子収納用パッケージの改良に関 するものである。 This invention relates to the improvement of a semiconductor device storage package for accommodating semiconductor devices. It is something to do.
【０００２】0002
従来、半導体素子、例えば多数の電極を有するゲートアレイ型半導体素子を収 容するプラグイン型半導体素子収納用パッケージは、アルミナセラミックス等の 電気絶縁性材料から成り、内部に半導体素子を収容するための空所を有する絶縁 基体と蓋体及び内部に収容する半導体素子を外部電気回路に電気的に接続するた めに前記絶縁基体の一主面に周列状に取着された多数の外部リードピンとにより 構成されており、絶縁基体の空所内に半導体素子を収容し、半導体素子の各電極 を外部リードピンに接続した後、絶縁基体と蓋体とをガラス、樹脂等の封止材に より接合させ、絶縁基体と蓋体とから成る容器内部に半導体素子を気密に封止す ることによって最終製品として半導体装置となる。 Conventionally, semiconductor devices, such as gate array type semiconductor devices having a large number of electrodes, have been housed. The plug-in type semiconductor device storage package is made of alumina ceramics, etc. An insulator made of electrically insulating material and having a cavity inside to accommodate a semiconductor element For electrically connecting the base body, lid body, and semiconductor element housed inside to an external electric circuit. In order to The semiconductor element is housed in a cavity of an insulating base, and each electrode of the semiconductor element is After connecting to the external lead pin, the insulating base and lid are sealed with a sealing material such as glass or resin. The semiconductor element is hermetically sealed inside a container consisting of an insulating base and a lid. By doing so, the final product becomes a semiconductor device.
【０００３】 尚、この従来のプラグイン型半導体素子収納用パッケージでは、外部リードピ ンと外部電気回路との電気的接続を良好となすために、また外部リードピンが酸 化腐食するのを防止するために通常、前記外部リードピンの外表面にはニッケル 、金等の良導電性で、且つ耐蝕性に優れた金属が電解メッキ方法により層着され ている。0003 In addition, in this conventional plug-in type semiconductor device storage package, external lead pins are In order to make a good electrical connection between the lead pin and the external electrical circuit, the external lead pin should be To prevent corrosion, the outer surface of the external lead pin is usually coated with nickel. , metals with good conductivity and excellent corrosion resistance, such as gold, are layered by electrolytic plating. ing.
【０００４】0004
しかしながら、この従来のプラグイン型半導体素子収納用パッケージは、絶縁 基体の一主面で周列状に取着された外部リードピンの露出外表面に電解メッキ方 法によりニッケル、金等を層着させた場合、電解メッキの際の荷電粒子は被メッ キ物のエッジ部に集中するという性質を有していることから各外部リードピンの 先端、特に最外周角部に位置する外部リードピンの先端に荷電粒子が集中して電 流密度が大きくなり、その結果、最外周角部に位置する外部リードピンはその先 端に多量のメッキ金属層が析出層着されて先端径が極めて大きなものとなってし まい、外部リードピンを外部電気回路に設けたソケット等に挿入し、内部に収容 する半導体素子の各電極を外部電気回路に接続する場合、外部リードピンのソケ ット等内への挿入が極めて困難となって半導体素子を外部電気回路に電気的に接 続することが不可となる欠点を有していた。 However, this conventional plug-in type semiconductor device storage package is Electrolytic plating is applied to the exposed outer surface of the external lead pins attached in a circumferential row on one main surface of the base. When a layer of nickel, gold, etc. is deposited using a method, charged particles during electrolytic plating can be Because each external lead pin has the property of concentrating on the edge of the material, Charged particles concentrate at the tip, especially at the tip of the external lead pin located at the outermost corner, causing an electric charge. The flow density increases, and as a result, the external lead pin located at the outermost corner A large amount of plated metal layer is deposited on the end, resulting in an extremely large tip diameter. Insert the external lead pin into a socket etc. provided in the external electrical circuit and store it inside. When connecting each electrode of a semiconductor device to an external electrical circuit, use the external lead pin socket. This makes it extremely difficult to insert the semiconductor device into an external electrical circuit. It had a drawback that made it impossible to continue.
【０００５】[0005]
本考案は絶縁基体の一主面に多数の外部リードピンが周列状に取着されて成る プラグイン型半導体素子収納用パッケージにおいて、前記周列状に取着された外 部リードピンのうち最外周角部に位置する外部リードピンの外側にダミーの外部 リードピンが取着されていることを特徴とするものである。 This invention consists of a large number of external lead pins attached in a circumferential row on one main surface of an insulating base. In the plug-in type semiconductor device storage package, the outer A dummy external It is characterized in that a lead pin is attached.
【０００６】[0006]
次に本考案を添付図面に基づき詳細に説明する。 Next, the present invention will be explained in detail based on the accompanying drawings.
【０００７】 図1 乃至図3 は本考案にかかるプラグイン型半導体素子収納用パッケージの一 実施例を示し、1 は絶縁基体、2 は蓋体である。この絶縁基体1 と蓋体2 とで半 導体素子3 を収容するための絶縁容器4 が構成される。[0007] Figures 1 to 3 show one of the plug-in type semiconductor device storage packages according to the present invention. An example is shown, where 1 is an insulating base and 2 is a lid. This insulating base 1 and lid 2 form a half An insulating container 4 for accommodating the conductor element 3 is constructed.
【０００８】 前記絶縁基体1 はアルミナ、ムライト、窒化アルミニウム、炭化珪素等のセラ ミックスから成り、その上面中央部に半導体素子3 を収容するための空所を形成 する凹部1aが設けてあり、該凹部1a底面には半導体素子3 がガラス、樹脂、ロウ 材等の接着材を介して取着固定される。[0008] The insulating substrate 1 is made of ceramic such as alumina, mullite, aluminum nitride, silicon carbide, etc. A cavity is formed in the center of the top surface to accommodate the semiconductor element 3. A recess 1a is provided on the bottom surface of the recess 1a, and a semiconductor element 3 is placed on the bottom surface of the recess 1a. It is attached and fixed via an adhesive such as wood.
【０００９】 また前記絶縁基体1 には凹部1aの周辺から底面にかけてメタライズ配線層5 が 導出されており、該メタライズ配線層5 の凹部1a周辺部には半導体素子3 の各電 極がボンディングワイヤ6 を介して電気的に接続され、また絶縁基体1 の底面に 導出された部位には外部電気回路と接続される外部リードピン7 が銀ロウ等のロ ウ材を介して取着される。[0009] Further, a metallized wiring layer 5 is formed on the insulating substrate 1 from the periphery of the recess 1a to the bottom surface. Each voltage of the semiconductor element 3 is connected to the peripheral part of the recess 1a of the metallized wiring layer 5. The poles are electrically connected via bonding wire 6 and are also connected to the bottom of insulating substrate 1. The external lead pin 7, which is connected to the external electric circuit, is attached to the lead-out part using a metal such as silver solder. It is attached through corrugated wood.
【００１０】 前記絶縁基体1 は例えば、アルミナセラミックスから成る場合、酸化アルミニ ウム(Al 2 O 3 ) 、シリカ(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原 料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状となすとともにこれをドク ターブレード法を採用することによってセラミックグリーンシート( セラミック 生シート) を形成し、しかる後、前記セラミックグリーンシートに適当な打ち抜 き加工を施すとともに複数枚積層し、高温( 約1600℃) で焼成することによって 製作される。When the insulating substrate 1 is made of alumina ceramics, for example, an organic solvent suitable for raw material powder such as aluminum oxide (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), magnesia (MgO), etc. A ceramic green sheet (ceramic raw sheet) is formed by adding and mixing a solvent to form a slurry and using a doctor blade method to form a slurry. After that, the ceramic green sheet is subjected to an appropriate punching process and a plurality of sheets are formed. It is manufactured by laminating layers and firing at high temperatures (approximately 1600℃).
【００１１】 また前記メタライズ配線層5 はタングステン(W) 、モリブデン(Mo)、マンガン (Mn)等の高融点金属粉末から成り、該高融点金属粉末に適当な有機溶剤、溶媒を 添加混合して得た金属ペーストを従来周知のスクリーン印刷法等の厚膜手法を採 用し、絶縁基体1 となるセラミックグリーンシートに予め被着させておくことに よって絶縁基体1 の凹部1a周辺から底面にかけて導出される。[0011] Further, the metallized wiring layer 5 is made of tungsten (W), molybdenum (Mo), manganese. (Mn) and other high melting point metal powder, and a suitable organic solvent or solvent is added to the high melting point metal powder. The metal paste obtained by adding and mixing is applied using a thick film method such as the well-known screen printing method. The ceramic green sheet that will be used as the insulating substrate 1 is coated in advance. Therefore, it is led out from around the recess 1a of the insulating substrate 1 to the bottom surface.
【００１２】 尚、前記メタライズ配線層5 はその露出する外表面にニッケル、金等の良導電 性で、且つ耐蝕性に優れた金属をメッキ法により1.0 乃至20.0μm の厚みに層着 させておくとメタライズ配線層5 の酸化腐食を有効に防止することができるとと もにメタライズ配線層5 とボンディングワイヤ6 との接続及びメタライズ配線層 5 と外部リードピン7 とのロウ付け取着が極めて強固なものとなる。従って、メ タライズ配線層5 の酸化腐食を防止し、メタライズ配線層5 とボンディングワイ ヤ6 との接続及びメタライズ配線層5 と外部リードピン7 とのロウ付けを強固な ものとなすにはメタライズ配線層5 の露出外表面にニッケル、金等を1.0 乃至20 .0μm の厚みに層着させておくことが好ましい。0012 The metallized wiring layer 5 is coated with a highly conductive material such as nickel or gold on its exposed outer surface. A layer of metal with excellent corrosion resistance and corrosion resistance is deposited to a thickness of 1.0 to 20.0 μm using a plating method. It is believed that if left untreated, oxidation corrosion of the metallized wiring layer 5 can be effectively prevented. Connection between metallized wiring layer 5 and bonding wire 6 and metallized wiring layer 5 and the external lead pin 7 become extremely strong. Therefore, mail This prevents oxidation corrosion of the metallized wiring layer 5 and protects the metallized wiring layer 5 and bonding wire. The connection with the layer 6 and the brazing between the metallized wiring layer 5 and the external lead pin 7 are made firmly. To achieve this, apply nickel, gold, etc. to the exposed outer surface of the metallized wiring layer 5 at a thickness of 1.0 to 20%. It is preferable to form a layer with a thickness of .0 μm.
【００１３】 更に前記絶縁基体1 に被着させたメタライズ配線層5 にロウ付けされる外部リ ードピン7 は内部に収容する半導体素子3 を外部電気回路に電気的に接続する作 用を為し、外部リードピン7 を外部電気回路に設けたソケット等に挿入し接続す ることによって内部に収容される半導体素子3 はメタライズ配線層5 及び外部リ ードピン7 を介して外部電気回路に接続されることとなる。[0013] Furthermore, an external lead is soldered to the metallized wiring layer 5 deposited on the insulating substrate 1. The lead pin 7 serves to electrically connect the semiconductor element 3 housed inside to an external electric circuit. Insert the external lead pin 7 into the socket etc. provided on the external electric circuit to connect it. The semiconductor element 3 housed inside the metallized wiring layer 5 and the external wiring layer It will be connected to an external electrical circuit via the field pin 7.
【００１４】 前記外部リードピン7 はコバール金属(Fe-Ni-Co 合金) や42アロイ(Fe-Ni合金 ) 等の金属から成り、コバール金属等のインゴット( 塊) を圧延加工法や打ち抜 き加工法等、従来周知の金属加工法を採用することによって所定のピン状に形成 される。[0014] The external lead pin 7 is made of Kovar metal (Fe-Ni-Co alloy) or 42 alloy (Fe-Ni alloy). ), etc., and the ingot (lump) of Kovar metal etc. is rolled or punched. Formed into a predetermined pin shape by employing conventionally well-known metal processing methods such as metal processing methods. be done.
【００１５】 また前記外部リードピン7 は図2 に示す如く絶縁基体1 の一主面に周列状に配 置取着されており、その最外周角部に位置する外部リードピン7 の外側にはダミ ーの外部リードピン7aが取着されている。このダミーの外部リードピン7aは後述 する外部リードピン7 の外表面に電解メッキ方法によりメッキ金属層を析出層着 させる際、最外周角部に位置する外部リードピン7 の先端表面に多量のメッキ金 属が層着して外部リードピン7 の径が極めて大きなものとなるを有効に防止する 作用を為す。[0015] Further, the external lead pins 7 are arranged in a circumferential row on one main surface of the insulating base 1 as shown in FIG. The external lead pin 7, which is located at the outermost corner of the - external lead pin 7a is attached. This dummy external lead pin 7a will be explained later. A plating metal layer is deposited on the outer surface of the external lead pin 7 using an electrolytic plating method. When placing a large amount of plated gold on the tip surface of the external lead pin 7 located at the outermost corner, This effectively prevents the diameter of the external lead pin 7 from becoming extremely large due to layering of metal. perform an action.
【００１６】 尚、前記ダミーの外部リードピン7aは外部リードピン7 と実質的に同じ金属材 料によって形成される。[0016] The dummy external lead pin 7a is made of substantially the same metal material as the external lead pin 7. Formed by materials.
【００１７】 また前記外部リードピン7 は図3 に示す如くその外表面に酸化腐食を有効に防 止し、且つ外部電気回路との電気的接続を良好とするためのニッケル、金等から 成るメッキ金属層8 が1.0 乃至20.0μm の厚みに層着されている。[0017] In addition, the external lead pin 7 effectively prevents oxidation corrosion on its outer surface as shown in Figure 3. Made of nickel, gold, etc. to ensure good electrical connection with external electrical circuits. A plated metal layer 8 consisting of the following is deposited to a thickness of 1.0 to 20.0 μm.
【００１８】 前記メッキ金属層8 は従来周知の電解メッキ方法を採用することによって外部 リードピン7 の露出外表面に層着され、この場合、電解メッキの際の荷電粒子は 周列状に配列取着した外部リードピン7 のうち最外周角部に位置する外部リード ピン7 の先端に集中しようとするが最外周角部に位置する外部リードピン7 はそ の外側にダミーの外部リードピン7aが取着されているため荷電粒子はダミーの外 部リードピン7aに集中し、その結果、各外部リードピン7 は荷電粒子の集中が有 効に防止されて析出層着されるメッキ金属層8 も略均一となり、各外部リードピ ン7 の先端径が特別大きくなることはない。従って、外部リードピン7 をソケッ ト等に挿入し外部電気回路に接続する場合、外部リードピン7 のソケット等への 挿入が極めて容易となり、外部リードピン7 を外部電気回路に確実、且つ強固に 電気的接続することが可能となる。[0018] The plated metal layer 8 is formed externally by employing a conventionally well-known electrolytic plating method. A layer is deposited on the exposed outer surface of lead pin 7, and in this case, charged particles during electrolytic plating are The external lead located at the outermost corner of the external lead pins 7 arranged in a circumferential row. It tries to concentrate on the tip of pin 7, but the external lead pin 7 located at the outermost corner Since the dummy external lead pin 7a is attached to the outside of the dummy, charged particles are As a result, each external lead pin 7 has a concentration of charged particles. The plated metal layer 8 that is effectively prevented from depositing is also approximately uniform, and each external lead pin is The diameter of the tip of tube 7 is not particularly large. Therefore, connect external lead pin 7 to the socket. When inserting the external lead pin 7 into the socket etc. and connecting it to an external electric circuit, It is extremely easy to insert, and the external lead pin 7 can be connected securely and firmly to the external electrical circuit. Electrical connection becomes possible.
【００１９】 尚、前記ダミーの外部リードピン7aはその長さが周列状に取着した各外部リー ドピン7 の長さに対して0.75倍未満であると電解メッキ方法によって各外部リー ドピン7 の外表面にメッキ金属層8 を層着させる際、最外周角部の外部リードピ ン7 に荷電粒子が集まって多量のメッキ金属層8 が析出層着される危険性があり 、また1.5 倍を越えるとダミーの外部リードピン7aに荷電粒子が大きく集中して 周列状に取着した各外部リードピン7 の外表面に所定厚みのメッキ金属層8 を層 着させることができなくなる傾向にある。従って、ダミーの外部リードピン7aは その長さを周列状に取着した各外部リードピン7 の長さに対して0.75乃至1.5 倍 となすことが好ましく、より好適にはダミーの外部リードピン7aの長さを各外部 リードピン7 より15乃至30% 長いものとしておくのがよい。[0019] The length of the dummy external lead pin 7a is equal to that of each external lead attached in a circumferential row. If the length of each external lead is less than 0.75 times the length of the doping pin 7, When depositing the plating metal layer 8 on the outer surface of the lead pin 7, the external lead pin at the outermost corner There is a risk that charged particles will collect on the metal plate 7 and a large amount of plated metal layer 8 will be deposited. , and if it exceeds 1.5 times, charged particles will be concentrated on the dummy external lead pin 7a. A plated metal layer 8 of a predetermined thickness is layered on the outer surface of each external lead pin 7 attached in a circumferential row. They tend to be unable to wear them. Therefore, the dummy external lead pin 7a is Its length is 0.75 to 1.5 times the length of each external lead pin 7 attached in a circumferential row. It is preferable to set the length of the dummy external lead pin 7a to the length of each external lead pin 7a. It is best to make it 15 to 30% longer than lead pin 7.
【００２０】 かくして本考案のプラグイン型半導体素子収納用パッケージによれば、絶縁基 体1 の凹部1a底面に半導体素子3 を接着材を介して取着固定し、該半導体素子3 の各電極をボンディングワイヤ6 によりメタライズ配線層5 に接続させるととも に絶縁基体1 と蓋体2 とを樹脂等の封止材で接合させ、絶縁基体1 と蓋体2 とか ら成る容器4 内部に半導体素子3 を気密に封止することによって最終製品として の半導体装置が完成する。[0020] Thus, according to the plug-in semiconductor device storage package of the present invention, the insulating base A semiconductor element 3 is attached and fixed to the bottom surface of the recess 1a of the body 1 via an adhesive, and the semiconductor element 3 is Each electrode is connected to the metallized wiring layer 5 by a bonding wire 6. The insulating base 1 and the lid 2 are bonded together using a sealing material such as resin, and the insulating base 1 and the lid 2 are bonded together. By airtightly sealing the semiconductor element 3 inside the container 4 consisting of A semiconductor device is completed.
【００２１】 尚、本考案は上述の実施例に限定されるものではなく本考案の要旨を逸脱しな い範囲であれば種々の変更は可能である。[0021] The present invention is not limited to the above-mentioned embodiments, and there may be no deviation from the gist of the present invention. Various changes are possible within a reasonable range.
【００２２】[0022]
本考案のプラグイン型半導体素子収納用パッケージによれば、絶縁基体の一主 面に周列状に取着された外部リードピンのうち最外周角部に位置する外部リード ピンの外側にダミーの外部リードピンを取着したことから外部リードピンの外表 面に電解メッキ方法によってメッキ金属層を層着させる際、電解メッキの荷電粒 子はダミーの外部リードピン先端に集中するものの各外部リードピンの先端に集 中することは一切なく、その結果、各外部リードピンはその外表面に略同一厚み のメッキ金属層が析出層着され、先端径が特別大きくなることは皆無となる。従 って、外部リードピンをソケット等に挿入し外部電気回路に接続する場合、外部 リードピンのソケット等への挿入が極めて容易となり、外部リードピンを外部電 気回路に確実、且つ強固に電気的接続することが可能となる。 According to the plug-in type semiconductor device storage package of the present invention, one of the main parts of the insulating substrate is The external lead located at the outermost corner of the external lead pins attached to the surface in a circumferential row. Since a dummy external lead pin was attached to the outside of the pin, the external surface of the external lead pin When depositing a plated metal layer on a surface by electrolytic plating, charged particles of electrolytic plating The children are concentrated at the tip of the dummy external lead pin, but they are concentrated at the tip of each external lead pin. There is no centering, so that each external lead pin has approximately the same thickness on its outer surface. The plated metal layer is deposited and the tip diameter does not become particularly large. subordinate Therefore, when inserting an external lead pin into a socket etc. and connecting it to an external electrical circuit, It is extremely easy to insert the lead pin into a socket, etc., and the external lead pin can be connected to an external power source. It becomes possible to make a reliable and strong electrical connection to the air circuit.
【図面の簡単な説明】[Brief explanation of drawings]
【図１】本考案のプラグイン型半導体素子収納用パッケ
ージの一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a plug-in type semiconductor device storage package of the present invention.
【図２】図１に示すパッケージの底面図である。FIG. 2 is a bottom view of the package shown in FIG. 1.
【図３】図１に示すパッケージの要部拡大断面図であ
る。FIG. 3 is an enlarged sectional view of a main part of the package shown in FIG. 1;
１・・・・絶縁基体 ２・・・・蓋体 ４・・・・容器 ５・・・・メタライズ配線層 ７・・・・外部リードピン ７ａ・・・ダミーの外部リードピン 1...Insulating base 2... Lid body 4... Container 5...Metallized wiring layer 7...External lead pin 7a...Dummy external lead pin
Claims (2)
が周列状に取着されて成るプラグイン型半導体素子収納
用パッケージにおいて、前記周列状に取着された外部リ
ードピンのうち最外周角部に位置する外部リードピンの
外側にダミーの外部リードピンが取着されていることを
特徴とするプラグイン型半導体素子収納用パッケージ。1. A plug-in type semiconductor device storage package comprising a plurality of external lead pins attached in a circumferential row on one main surface of an insulating base, wherein the most external lead pin among the external lead pins attached in the circumferential row is provided. A plug-in type semiconductor device storage package characterized in that a dummy external lead pin is attached to the outside of the external lead pin located at a corner of the outer periphery.
状に取着した外部リードピンの長さに対し0.75乃至1.5
倍であることを特徴とする請求項１に記載のプラグイン
型半導体素子収納用パッケージ。[Claim 2] The length of the dummy external lead pin is 0.75 to 1.5 with respect to the length of the external lead pins attached in a circumferential row.
2. The plug-in type semiconductor device storage package according to claim 1, wherein the package is twice the size of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991026930U JP2550488Y2 (en) | 1991-04-19 | 1991-04-19 | Plug-in type semiconductor element storage package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991026930U JP2550488Y2 (en) | 1991-04-19 | 1991-04-19 | Plug-in type semiconductor element storage package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04121753U true JPH04121753U (en) | 1992-10-30 |
| JP2550488Y2 JP2550488Y2 (en) | 1997-10-15 |
Family
ID=31911324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991026930U Expired - Fee Related JP2550488Y2 (en) | 1991-04-19 | 1991-04-19 | Plug-in type semiconductor element storage package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550488Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6265845U (en) * | 1985-10-14 | 1987-04-23 | ||
| JPH0220054A (en) * | 1988-07-08 | 1990-01-23 | Hitachi Ltd | Circuit package |
| JPH03104149A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Semiconductor package |
-
1991
- 1991-04-19 JP JP1991026930U patent/JP2550488Y2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6265845U (en) * | 1985-10-14 | 1987-04-23 | ||
| JPH0220054A (en) * | 1988-07-08 | 1990-01-23 | Hitachi Ltd | Circuit package |
| JPH03104149A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2550488Y2 (en) | 1997-10-15 |
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