JPH04117030A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of an external input discrimination level due to fluctuation in a power supply voltage by connecting a P-channel MOS transistor(TR) whose unsaturation region is used to a source of an input discrimination circuit. CONSTITUTION:The title circuit consists of series connection of a P-channel MOS TR Q3 whose unsaturation region is used, a P-channel MOS TR Q1 receiving an external input discrimination level IN and an N-channel MOS TR Q2. The P-channel MOS TR Q3 whose gate connects to ground and whose unsaturation region is used acts like a resistor as its DC characteristic, a drain- source voltage VDS of the TR Q3 is increased as a power supply voltage VCC increases and the drain-source voltage VDS of the TR Q3 is decreased as a power supply voltage VCC decreases. As a result, a change in a level at a node 1 is smaller than a change in the power supply voltage VCC. Thus, an external input TTL level is applied to the title circuit, a stable normal operation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an external input determination circuit.

[Conventional technology]

Conventionally, in the external input determination circuit of this type of semiconductor integrated circuit, the input level is converted from the TTL (transistor-transistor-logic) level to the MOS (one transistor) level as shown in Figure 2(a). , P-channel transistor Q1 and N-channel transistor Q
It had an inverter configuration consisting of 2.

[Problem to be solved by the invention]

The external input determination circuit of the conventional semiconductor integrated circuit described above is
As shown in Figure 2(b), the external input judgment level IN varies greatly with variations in the power supply voltage vcc, so stable and normal operation cannot be achieved when the external input level is applied at the TTL level. The disadvantage is that it cannot be used.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit in which the above drawbacks are solved and the input determination level does not change much even if the power supply voltage fluctuates.

[Means to solve the problem]

The structure of the semiconductor integrated circuit of the present invention is that MOs which are complementary to each other.
A series body of S transistors, one end of the series body and one power supply potential are connected to the source and drain of a third MOS transistor, and the gate of the third MOS transistor is connected to another power supply potential. It is characterized by being equipped with an input determination circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a circuit diagram showing an external input determination circuit of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1(a), this embodiment has a P-channel type MO8 transistor Q3 using a non-saturation region and an external input determination level I
P-channel type MO8 transistor Q1 to which N is applied
and an N-channel MOS transistor Q2 in series.

FIG. 1(b) is a DC characteristic diagram of the external input determination circuit according to the embodiment of FIG. 1(a). In Figures 1(a) and (b), the P-channel transistor Q3, whose gate is grounded and uses a non-saturation region, becomes a resistance as a direct current characteristic, so when the power supply voltage v0 fluctuates, the transistor Q3
3 changes, and the power supply voltage V. When 0 increases, the vDs of transistor Q3 increases, and when VCC decreases, Vt19 of transistor Q3 decreases, resulting in a level like 1 in FIG. 2(b). Here, since the external input judgment level IN is determined by the size ratio of Ql:Q2, the fluctuation range of the external input judgment level IN is also smaller as the fluctuation of the level that is the source of the transistors Ql and Q2 is reduced. Become. As a result, stable and normal operation can be obtained when an external input level is applied as a TTL level.

In this embodiment, the external input determination level fluctuation range due to power supply voltage fluctuations can be reduced by connecting the P-channel type MO8 transistor Q3 using a non-saturation region to the source side of the input determination circuit.

〔Effect of the invention〕

As explained above, the present invention particularly connects a P-channel type MO3 transistor using a non-saturation region to the source side of the input determination circuit, thereby reducing the fluctuation width of the external input determination level due to fluctuations in the power supply voltage. I can do it.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram of an external input determination circuit of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 1(b) is a circuit diagram of an external input determination circuit of a semiconductor integrated circuit according to an embodiment of the present invention.
FIG. 2(a) is a circuit diagram of an example of a conventional external input determination circuit, and FIG. 2(b) is a DC characteristic diagram of FIG. 2(a). VCC...Power supply voltage, IN...External input, OUT...Output, 1...Node, Q
l, Q2...P-channel type MO8 transistor, Q3...N-channel type MO8 transistor. Agent Patent Attorney Susumu Uchihara (α→ (b) Obi tII!J 7zo't-c VCC Hiri (b) etc. 2 Drunkenness

Claims (1)

[Claims] A series body of MOS transistors complementary to each other, and a source/drain of a third MOS transistor are connected between one end of the series body and one power supply potential, and the third MOS transistor
A semiconductor integrated circuit comprising an external input determination circuit in which a gate of a transistor is connected to another power supply potential.