JPH04115644A - Memory monitor circuit - Google Patents

Abstract

PURPOSE:To always monitor competitive relation between a transmission line clock and an intra-device clock, and to remove a protection circuit against a memory error by invalidating the alarm output of a memory error detecting part to the output signal of an elastic memory when it is detected that an read address outruns a write address. CONSTITUTION:The transmission line clock and the intra-device clock are converted by a write address converting part 2 and a read address converting part 3 into the write address and the read address of the elastic memory 1 respectively, and are given to an outrunning detecting part 4. Accordingly, the outrunning detecting part 4 comes to monitor always the write address and the read address of the elastic memory 1, and when it detects the outrunning relation of write address < read address, it invalidates the memory error signal from the memory error detecting part 5 by a circuit 6. Thus, the competitive relation between the transmission line clock and the intra-device clock is always monitored not only at the point of the time of the start of a frame, and the protection circuit against the memory error can be removed.

Description

[Detailed Description of the Invention] [Summary] Concerning a memory monitoring circuit that monitors delay insertion/removal when switching from a transmission line clock to an internal device clock using elastic memory, there is a competitive relationship between the transmission line clock and the internal device clock. The purpose is to eliminate the memory error protection circuit by constantly monitoring the data not only at the start of the frame, and to convert the memory error into a write address corresponding to the transmission line clock in the elastic memory. a read address conversion unit that converts the memory into a read address corresponding to an internal clock of the device; an overtaking detection unit that compares both addresses and detects that the read address has overtaken the write address; and the overtaking detection unit. and a circuit for disabling the alarm output of the memory error detection section for the output signal of the elastic memory when the elastic memory section detects overtaking.

[Industrial application field]

The present invention relates to a memory monitoring circuit, and more particularly to a memory monitoring circuit that uses an elastic memory to monitor delay insertion/removal when switching from a transmission line clock to an internal clock.

In multiplexing/demultiplexing equipment, etc., the data speed is converted by switching from the transmission line clock to the device clock using elastic memory. Since errors occur in memory, there is a need to strengthen memory error monitoring.

However, if the relationship between the memory transmission line clock and the device clock is delayed insertion/removal, this is not a memory abnormality, and in such a case, it is necessary to disable the memory abnormality alarm.

[Conventional technology]

Figure 3(a) shows a conventional memory monitoring circuit that disables the alarm of memory abnormality when memory is inserted or removed with a delay.l is the transmission line clock as the write clock WC, and l is the internal clock of the device. Elastic memory (ES) with a read clock RC, 10 a parity focus insertion unit that inserts a parity bit into a transmission line signal, 20 a maximum count that is incremented by the transmission line clock and equal to the period of the transmission line frame pulse FP. Elastic memory 1 by counting up to the value
21 is an OR gate that inputs the transmission path frame pulse FP and the lithop carry signal RC of the counter 20 to reset the counter 20; 30 is an internal clock of the device; The internal frame pulse FP' is increased by
A counter 31 receives the internal frame pulse FP' and the ripple carry signal of the counter 30, and generates a ripple carry signal that counts up to the maximum count value and becomes the read reset signal RR of the elastic memory 1. an OR gate that resets the counter 30;
40 is a phase monitoring unit that monitors the phase of the write reset signal WR from the counter 20 and the read reset signal RR from the counter 30 and generates a delayed insertion/extraction signal; 5 is a parity bit inserter for detecting a memory abnormality in the elastic memory 1; A memory error detection section 60 detects a parity error etc. using the parity bit inserted in the section 10, a protection circuit 60 is composed of a predetermined number of flip-flops (FF) and delays the output of the memory error detection section 5 for a certain period of time; 61 is an OR gate for inputting the input disconnection signal REC and the delay insertion/removal signal of the phase monitoring section 40 to reset the protection circuit 60.

In the operation of such a memory monitoring circuit, the elastic memory 1, which is manually operated using the transmission line clock as the write clock, sequentially writes the transmission line signal into which the parity bit has been inserted by the parity bit insertion unit 10, and the The counter 20 is caused to count based on the transmission line clock.

Then, when the transmission line frame pulse FP is input to the counter 20 via the OR gate 21, a write reset signal WR is generated at the moment the counter 20 is reset.
New data is written to the elastic memory 1 from the beginning.

In addition, when the transmission line frame pulse is missing, when the counter 20 counting the transmission line clock counts the same number as the period of the transmission line frame pulse FP, it counts up and writes a ripple carry signal as the write reset signal WR. It is designed to be given to elastic memory l.

On the other hand, when reading the transmission line signal written in the elastic memory 1, the elastic memory 1 sequentially performs reading using the internal clock as the read clock.

Then, the in-device frame pulse FP' is output from the OR gate 31.
When the data is input to the counter 30 via the counter 30, the read reset signal RR is generated at the moment the counter 30 is reset, and the elastic memory 1 is newly read from the beginning.

In addition, when the internal frame pulse FP' is missing, when the counter 30 that counts the internal clock has counted the same period as the internal frame pulse FP', the count is amplified and the ripple key + re signal is read out and reset. The signal is applied to the elastic memory 1 as a signal RR.

Then, a memory error detection unit 5 detects a memory error in the elastic memory 1, and a protection circuit 6 with a predetermined number of protection stages detects a memory error in the elastic memory 1.
0, an alarm signal indicating an abnormal operation of the elastic memory 1 is generated. Note that this number of protection stages corresponds to the period necessary to eliminate memory errors caused by the input disconnection signal REC input to the OR gate 61.
Unless the input cutoff signal REC resets the protection circuit 60 within this period, an alarm signal will be generated as a memory error.

In such a memory monitoring circuit, writing and reading of the elastic memory 1 is performed within the frame-by-frame jitter range (-α) of the internal frame pulse FP' as shown in FIG.
~+α) If a conflict arises in which the transmission line frame pulse FP enters the phase monitoring window, the memory contents of the elastic memory 1 will not be guaranteed and a failure will occur where data will be inserted or removed with a delay. The phase monitoring unit 40 that monitors and detects this resets the flip-flop of the protection circuit 60 in the same way as in the case of the input cutoff signal REC, so that even if the memory error detection unit 5 generates an error detection signal at this time, Since this is not an abnormality in the memory 1 itself, this error detection signal is disabled so as not to be output as an alarm signal.

[Problem to be solved by the invention]

In this way, in the conventional memory monitoring circuit, the phase monitoring unit 40 monitors frame pulses, and therefore phase monitoring can only be performed at the start of this frame pulse. There is a problem in that a memory error alarm is generated when the transmission line clock and the device internal clock overtake each other.

In addition, in order to monitor the phase of each frame, the input disconnection signal R
There is also the problem that the number of protection stages for EC must be provided as a protection circuit 60, making the circuit complicated.

Therefore, in a memory monitoring circuit that uses elastic memory to monitor delay insertion/removal when switching from a transmission line clock to an internal clock, the present invention detects the competitive relationship between the transmission line clock and the internal clock only at the frame start point. The purpose is to constantly monitor and eliminate memory error protection circuits.

[Means to solve the problem]

In order to achieve the above object, the memory monitoring circuit according to the present invention converts a write address into a write address corresponding to a transmission line clock in the elastic memory 1, as shown in principle in FIG. 2, a read address conversion unit 3 that converts the address into a read address corresponding to the internal clock in the elastic memory 1, and an overtaking detection unit that compares both addresses and detects that the read address has overtaken the write address. 4, and a circuit 6 for disabling the alarm output of the memory error detection unit 5 in response to the output signal of the elastic memory 1 when the overtaking detection unit 4 detects overtaking.
It is equipped with

[For production]

In the memory monitoring circuit according to the present invention shown in FIG. 1, the elastic memory 1 performs writing and reading in the same way as in the past, using the transmission line clock and the internal device clock as the write clock and read clock, respectively.

These transmission line clocks and device clocks are converted by the write address converter 2 and the read address converter 3 into the write address and read address of the elastic memory 1, respectively, and are provided to the overtaking detector 4. .

Therefore, the overtaking detector 4 always monitors the write address and the read address of the elastic memory 1, and when it detects an overtaking relationship between the write address and the read address, the memory error detector 4 The memory error signal from 5 is invalidated by circuit 6.

As described above, in the present invention, the write phase and read phase in the elastic memory 1 are constantly monitored to detect overtaking of an address that causes delayed insertion/removal of the memory, and in such a case, the memory is immediately removed. You can override the error.

(Embodiment) FIG. 3 shows an embodiment of the memory monitoring circuit according to the present invention, and the same reference numerals as in FIGS. 1 and 3 indicate the same parts. In the example, counters 2 and 3 are used as the write address conversion unit 2 and read address conversion unit 3, respectively, and a subtracter is used as the overtaking detection unit 4 that inputs the addresses M and n being counted by these counters 2 and 3. Further, as the circuit 6, an AND gate is used.

In such an embodiment, the subtracter 4 subtracts the read address n of the counter 3 from the write address M of the counter 2, and when M≧n, since there is no delayed insertion/removal state, the output level is set to 1'', and the memory When the error detection unit 5 is generating a parity error detection signal (“1”), it directly generates an alarm signal via the AND gate 6.

On the other hand, when M<n, the parity value of the memory contents of the elastic memory 1 is not guaranteed, so the output signal of the memory error detection unit 5 becomes meaningless. 1"), in order to prevent this from occurring as an alarm, the subtracter 4 sets the output level to "0" and outputs the AND gate 6.
is considered disaple.

〔Effect of the invention〕

As described above, according to the memory monitoring circuit according to the present invention, the writing/reading phase of the elastic memory is constantly monitored, and when an overtaking state of an address that causes delayed insertion/removal is detected, a memory alarm is immediately issued. Since the memory is configured to be disabled, memory monitoring can be performed reliably and unnecessary protection circuits can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle configuration of a memory monitoring circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment of the memory monitoring circuit according to the present invention, and FIG. 3 is a block diagram showing a conventional example. Figure. In FIG. 1, 1... Elastic memory (BS), 2... Write address conversion section, 3... Read address conversion section, 4... Overtaking detection section, 5... Memory error Detection section, 6...AND gate. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A write address conversion unit (
2), a read address converter (3) that converts the elastic memory (1) into a read address corresponding to the internal clock of the device, and a read address converter (3) that compares both addresses and determines that the read address has overtaken the write address. an overtaking detector (4) that detects overtaking; and when the overtaking detector (4) detects overtaking, disables the alarm output of the memory error detector (5) for the output signal of the elastic memory (1). A memory monitoring circuit comprising: a circuit (6) for controlling