JP2942326B2 - Memory monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A memory monitoring circuit that monitors delay insertion / removal when switching from a transmission line clock to an internal clock using an elastic memory, and relates to a competition relationship between the transmission line clock and the internal clock. A write address conversion unit for converting to a write address corresponding to a transmission line clock in an elastic memory; A read address conversion unit that converts the read address corresponding to the internal clock in the device, an overtake detection unit that compares both addresses to detect that the read address has overtaken the write address, and an overtake detection unit When an overtaking is detected, an alarm output of the memory error detection unit for the output signal of the elastic memory is output. And a circuit for disabling.

[Industrial applications]

The present invention relates to a memory monitoring circuit, and more particularly to a memory monitoring circuit that monitors delay insertion / removal when switching from a transmission line clock to a device clock using an elastic memory.

In a multiplexing / demultiplexing device, the data speed is converted by switching from the transmission line clock to the device clock using an elastic memory. In such a speed conversion, the output data of the memory is converted due to a memory failure. Since an error occurs, it is required to enhance monitoring of the memory error.

However, if the relationship between the transmission line clock of the memory and the device clock is delayed insertion / removal, there is no abnormality in the memory. In such a case, it is necessary to invalidate the alarm of the memory abnormality.

[Conventional technology]

FIG. 3 (a) shows a conventional memory monitoring circuit for invalidating a memory abnormality alarm at the time of delayed insertion / removal of a memory. Reference numeral 1 denotes a transmission line clock as a write clock WC, and an internal clock as a read clock. Elastic memory (ES) used as RC, 10 is a parity bit insertion unit that inserts parity bits into the transmission path signal, 20 is incremented by the transmission path clock and counts up to the maximum count value equal to the cycle of the transmission path frame pulse FP A counter for generating a ripple carry signal serving as a write reset signal WR of the elastic memory 1; an OR gate 21 for receiving the transmission line frame pulse FP and the ripple carry signal RC of the counter 20 to reset the counter 20; Increments by the internal clock and counts up to the maximum count value equal to the cycle of the internal frame pulse FP '. 1 of the read reset signal
A counter that generates a ripple carry signal that becomes RR, 31
Is an OR gate that resets the counter 30 by inputting the frame pulse FP 'in the device and the ripple carry signal of the counter 30, and 40 monitors the phase of the write reset signal WR from the counter 20 and the read reset signal RR from the counter 30. A phase monitoring unit for generating a delay insertion / removal signal, and a memory error detection unit for detecting a memory error in the elastic memory 1 based on the parity bit inserted by the parity bit insertion unit 10; A protection circuit which is constituted by flip-flops (FF) and delays the output of the memory error detection unit 5 for a certain period of time, and 61 receives the input disconnection signal REC and the delay insertion / removal signal of the phase monitoring unit 40 to activate the protection circuit 60 This is an OR gate for resetting.

In such an operation of the memory monitoring circuit, the elastic memory 1 which inputs the transmission line clock as the write clock sequentially writes the transmission line signal into which the parity bit is inserted by the parity bit insertion unit 10, and then writes the transmission line signal. The counter 20 is counted by the transmission line clock.

When the transmission line frame pulse FP is input to the counter 20 via the OR gate 21, a write reset signal WR is generated at the moment when the counter 20 is reset, and the elastic memory 1 is newly written from the beginning. It is.

When the transmission line frame pulse is lost, the counter 20 counting the transmission line clock counts up when the counter 20 counts the same as the period of the transmission line frame pulse FP, and the ripple carry signal is used as the write reset signal WR. It is provided to the elastic memory 1.

On the other hand, when reading the transmission path signal written in the elastic memory 1, the elastic memory 1
Reading is sequentially performed using the internal clock as a reading clock.

When the in-device frame pulse FP 'is input to the counter 30 via the OR gate 31, a read reset signal RR is generated at the moment when the counter 30 is reset, and the elastic memory 1 is newly read from the beginning. I do.

When the internal frame pulse FP 'is missing, the counter 30 counting the internal clock counts up when the counter 30 counts the same period as the internal frame pulse FP', and the ripple carry signal is read out. This is given to the elastic memory 1 as RR.

Then, a memory error of the elastic memory 1 is detected by the memory error detection unit 5 and a protection circuit of a predetermined number of protection stages is provided.
After 60, an alarm signal indicating an abnormal operation of the elastic memory 1 is generated. The number of protection stages is determined by the OR gate.
This corresponds to the period required to eliminate the memory error due to the input disconnection signal REC input to 61, and an alarm signal is generated as a memory error unless the input disconnection signal REC resets the protection circuit 60 during this period. Will be done.

In such a memory monitoring circuit, writing and reading of the elastic memory 1 are performed in the jitter range (−α to −α) for each frame of the frame pulse FP ′ in the device as shown in FIG.
(Α), the contention of the transmission line frame pulse FP in the phase monitoring window may cause a failure in which the memory contents of the elastic memory 1 are not guaranteed and data may be inserted / removed with delay. The phase monitoring unit 40 that monitors and detects the reset signal resets the flip-flop of the protection circuit 60 in the same manner as in the case of the input disconnection signal REC.
At this time, even if the memory error detection unit 5 generates an error detection signal, this is not an abnormality of the memory 1 itself.
This error detection signal is invalidated so as not to be output as an alarm signal.

[Problems to be solved by the invention]

As described above, in the conventional memory monitoring circuit, the phase monitoring unit 40 monitors only the frame pulses, so that the phase monitoring can be performed only at the start time of the frame pulse. There is a problem that a memory error alarm is generated when the transmission path clock and the internal clock of the apparatus are overtaken.

Also, to monitor the phase of each frame, the input disconnection signal
The number of protection stages for REC must be prepared as the protection circuit 60, and there is a problem that the circuit becomes complicated.

Therefore, the present invention provides a memory monitoring circuit that monitors delay insertion / removal when switching from a transmission line clock to an in-device clock using an elastic memory, and determines the competition between the transmission line clock and the in-device clock only at the frame start time. The purpose of the present invention is to eliminate the memory error protection circuit by always monitoring the error.

[Means for solving the problem]

To achieve the above object, a memory monitoring circuit according to the present invention comprises a write address conversion unit for converting a write address corresponding to a transmission line clock in an elastic memory 1 as shown in principle in FIG. 2, a read address conversion unit 3 for converting a read address corresponding to an internal clock in the elastic memory 1, and an overtaking detection unit 4 for comparing both addresses to detect that the read address has overtaken the write address. And a circuit 6 for invalidating the alarm output of the memory error detection unit 5 for the output signal of the elastic memory 1 when the overtaking detection unit 4 detects overtaking.

[Action]

In the memory monitoring circuit according to the present invention shown in FIG. 1, the elastic memory 1 performs writing and reading in the same manner as in the prior art using the transmission line clock and the internal clock as the write clock and the read clock, respectively.

Then, the transmission line clock and the internal clock are converted into a write address and a read address of the elastic memory 1 by a write address conversion unit 2 and a read address conversion unit 3 and provided to the overtaking detection unit 4.

Therefore, the overtaking detection unit 4 always monitors the write address and the read address of the elastic memory 1, and when the overtaking relationship of write address <read address is detected, the memory error detection unit The circuit 6 invalidates the memory error signal from 5.

As described above, in the present invention, the write phase and the read phase in the elastic memory 1 are constantly monitored in address units to detect the overtaking of the address which causes the delay insertion / removal of the memory. Immediately invalidate memory errors.

[Embodiment] FIG. 3 shows an embodiment of the memory monitoring circuit according to the present invention. The same reference numerals as those in FIGS. 1 and 3 denote the same parts. The counters 2 and 3 are used as the write address conversion unit 2 and the read address conversion unit 3, respectively, and a subtractor is used as the overtaking detection unit 4 that inputs the addresses M and n during the counting of the counters 2 and 3. . The circuit 6 uses an AND gate.

In such an embodiment, the subtractor 4 is
Is subtracted from the write address M of the counter 3, and when M ≧ n, the delay insertion / removal state is not set, so that the output level is set to “1”, and the memory error detection unit 5 sets the parity error detection signal (“1”). ), An alarm signal is generated via the AND gate 6 as it is.

On the other hand, when M <n, since the parity value of the memory content of the elastic memory 1 is not guaranteed, the output signal of the memory error detection unit 5 is meaningless. For example, the parity detection unit 5 outputs the parity error signal (“1 "), So that it does not trigger an alarm,
The subtractor 4 sets the output level to "0" and disables the AND gate 6.

〔The invention's effect〕

As described above, according to the memory monitoring circuit of the present invention,
Since the write / read phase of the elastic memory is constantly monitored and the overtaking state of the address causing the delay insertion / removal is detected in address units, the memory alarm is immediately invalidated. Memory monitoring can be performed, and unnecessary protection circuits can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of a memory monitoring circuit according to the present invention. FIG. 2 is a block diagram showing an embodiment of the memory monitoring circuit according to the present invention. FIG. 3 is a block diagram showing a conventional example. FIG. In FIG. 1, 1 ... Elastic memory (ES), 2 ... Write address conversion unit, 3 ... Read address conversion unit, 4 ... Overtaking detection unit, 5 ... Memory error detection unit, 6 ... ... AND gate. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroyoshi Sato 3-28-1, Joto, Koyama City, Tochigi Prefecture Inside Fujitsu Digital Technology Co., Ltd. (56) References JP-A-61-84136 (JP, A) JP-A-1-154648 (JP, A) JP-A-2-31224 (JP, A) JP-A-61-156954 (JP, A)

Claims (1)

(57) [Claims] A write address conversion unit (2) for converting a write address corresponding to a transmission line clock in an elastic memory (1), and a read address corresponding to an internal clock in the elastic memory (1). A read address conversion unit (3) for comparing the two addresses, an overtaking detection unit (4) for detecting that the read address has overtaken the write address, and an overtaking detection unit (4) A circuit for disabling an alarm output of a memory error detection section (5) for an output signal of the elastic memory (1) when an overtaking is detected.