JPH05165729A - Malfunction restoration system for counter for memory access - Google Patents

Abstract

PURPOSE:To provide the malfunction detection/restoration system of an address counter for memory access, which can improve the fault of a data system on the malfunction detection/restoration system of the counter for memory. CONSTITUTION:This system is constituted of a memory 1 storing data, a write control part 2 generating a write address into the memory 1, a read control part 3 generating a read address into the memory 1, a use quantity detection part 4 supervising data capacity in the memory from a write clock and a read clock, a difference detection part 5 calculating the use quantity of data in the memory from the write address and the read address, a malfunction detection storage part 6 transmitting the erroneous restoration operation of a write address counter 2b, a read address counter 3b and the use quantity detection part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction detection / restoration system for a memory counter. If a malfunction occurs in the counter of each part due to the influence of noise, etc., when using the access method of monitoring the memory usage and reading the data accordingly, an error occurs in the memory usage and the write / read address counter. Therefore, the self-recovery becomes impossible due to a failure such as improper data discard, data loss, and output of unintentional data. Therefore, it is necessary to forcibly restore the counter.

[0002]

2. Description of the Related Art A circuit configuration of a conventional embodiment will be described below with reference to FIG. In the figure, reference numeral 1 denotes a memory, which is composed of, for example, a writable / readable two-port random access memory, and requires a capacity of, for example, 4 kilobytes.

Reference numeral 2 is a control unit 2a and a write address counter 2b.
The write control section is constituted by, and the number of bits of the write address counter 2b is 13 bits, for example. The control unit 2a
Generates a write clock (wc) by hitting the head signal with the main clock, and adds this wc signal to the write address counter 2b to generate the write address (w) of the memory 1.

Reference numeral 3 is a control section 3a and a read address counter 3b.
And the read address counter 3b has a bit number of 13 bits, for example. The control unit 3a
Generates a read clock (rc) by hitting the output data request signal with the main clock, and adds this rc signal to the read address counter 3b to generate the read address (r) of the memory 1.

In the circuit of the conventional example, input data is written to the memory 1 by the w signal of the write operation and r of the read operation is used.
It operates so as to read data from the memory 1 by a signal and send output data.

As described above, the write address counter 2a
Since the recovery process for the malfunction of the read address counter 3a and the read address counter 3a has not been performed, if an error occurs in the usage amount of the memory 1 or the counter value of the write address counter 2b or the read address counter 3b, the data is unjustly discarded or the unintentional data is deleted. The self-recovery is impossible because of the failure such as the output of.

[0007]

Therefore, when each counter malfunctions, there is a problem that the self-recovery cannot be performed and a failure occurs in the data system.

It is an object of the present invention to provide a malfunction detecting / restoring method for a memory access address counter which can improve a data system failure by a method of detecting malfunction of a write / read address counter and restoring each counter. And

[0009]

In order to achieve the above object, in the present invention, a write controller having a memory 1 for storing data and a write address counter 2b for generating a write address for the memory 1 from a write clock. 2, a read controller 3 having a read address counter 2b for generating a read address for the memory 1 from a read clock, and data in the memory 1 by counting up / down the write clock and the read clock. A usage detector 4 for monitoring the capacity, a difference detector 5 for calculating the usage of the data in the memory 1 from the difference between the write address and the read address, the write address counter 2b and the read address counter 3b. And sends a reset signal for performing malfunction detection and recovery operation of the usage amount detector 4. To, the data amount of the memory 1 which is monitored by the amount detecting unit 4 difference detector 5
The malfunction detection and restoration section 6 is provided with a comparison section 6a for comparing the agreement of the data amounts in the memory 1 calculated in step 1 and a reset section 6b for sending a reset signal when the comparison results are inconsistent.

[0010]

As shown in FIGS. 1 and 2, the present invention detects the amount of data in the memory 1 by each of the usage amount detector 4 and the difference detector 5 and detects the two data amounts detected there as a malfunction. The recovery unit 6 makes a comparison to detect a malfunction of the write address counter 2b, the read address counter 3b, and the capacity monitoring counter 4a. When a malfunction is detected, the malfunction detection recovery unit 6 performs a recovery operation of each counter.

Therefore, when any of the counters malfunctions due to the influence of noise or the like, it is possible to avoid the subsequent occurrence of a failure in the data system by recovering each counter by the recovery operation.

[0012]

Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a diagram showing a circuit configuration of the present invention, FIG. 2 is a diagram showing a time chart of the circuit of the present invention, and FIG. 3 is a diagram showing an example of detecting a data usage amount in the present invention.

In FIG. 1, 1 to 3 have the same structure as the conventional example, 1 is a memory, 2 is a write controller, and 3 is a read controller. Reference numerals 4 to 6 are circuits constituting the present invention. Reference numeral 4 is a usage amount detecting unit, which includes a capacity monitoring counter 4a for counting up / down of 7 bits. Reference numeral 5 is a difference detection unit, which is formed of, for example, a 7-bit full adder.

Reference numeral 6 denotes a malfunction detection / restoration unit, which is a 7-bit data amount m output from the difference detection unit 5 from the 7-bit data amount n output from the capacity monitoring counter 4a.
And a reset unit 6b for generating a reset signal (RST) from the malfunction alarm.

In FIG. 2, (a) to (c) are signals applied from the outside, and (d) to (k) are signals generated by the circuit of the present invention. It should be noted that (a) to (k) are the same signals as those described in each circuit portion of FIG.

(A) is the main clock, (b) is the input data,
(c) is a head signal indicating the head of the input data (b). Note that (d) is a write address (w) to the memory 1, (e) is output data read from the memory 1, and (f) is a read address (r) to the memory 1.

Further, (g) is the data amount m of the calculation result of the difference detection section 5, and (h) is the write clock (w) from the control section 2a.
c) and (i) are the read clocks (rc) from the control unit 3a, (j) is the data amount n of the monitoring result of the capacity monitoring counter 4a, and (k) is the reset output from the malfunction detection circuit. It is a signal.

In FIGS. 1 and 2, first, the head signal (c)
Write address (d) by tapping on the main clock (a)
"1" of the memory 1 is generated, and the data amount m (g) and the data amount n (j) of the memory 1 written by the write address (d) are both in the normal "1" state. If there is no read, the read address (f) is at "0" and the output data (e) is "undefined".

In normal operation, first, at the timing, the write signal counter 2b is triggered by the head signal (c).
Starts the operation, the write address (d) of the input data (b) is counted up from "1" to "2" based on "1" of the data amount n (j), and the input data (b ) 'A'
Write.

At this time, the capacity monitoring counter 4a in the usage amount detector 4 counts up, and the data amount n (j) is increased from "1" to "2". The difference detection unit 5 calculates the data amount m (g) in the memory 1 based on the difference between the write address (d) and the read address (f), and sets the data amount m (g) to "2".

In addition, the malfunction detection / restoration unit 6 stores these 2
The data amount n (j) and the data amount m (g) in one memory 1 are compared and it is confirmed that they both match with '2', and the reset signal (k) is not sent (the current state is maintained). ..

Next, when a data amount request signal is added at the timing, the read address counter 3b starts its operation based on "0" of the data amount n (j) to start the read address.
(f) is set to "1", the data "A" stored in the memory 1 is read and sent as output data (e). At this time, the data amount n output from the capacity monitoring counter 4a
(j) is counted down to '1'.

The difference detecting section 5 calculates the data amount m (g) of the memory 1 from the difference between the write address (d) and the read address (f) and reduces the data amount m (g) to "1". Further, the comparison unit 6a of the malfunction detection / restoration unit 6 compares the data amount n (j) with the data amount m (g) and confirms that they both match '1'. At the time of writing / reading, the read address counter 2b or the read address counter 3b is incremented to enter the state of accessing the memory 1.

On the other hand, if the read address counter 3b malfunctions at the timing, for example, the read address (f) remains "0" as shown by the shaded portion, and the data m (g) output from the difference detection unit 5 is It remains '2', which indicates an abnormality.

However, since the write clock (h) and the read clock (i) are output normally, the capacity monitoring counter 4a
Counts down and becomes normal "1" as shown by the shaded portion of the data amount n (j).

The comparing unit 6a of the malfunction detecting unit 6 detects a mismatch between the data amount n (j) '1' and the data m (g) '2', outputs a malfunction alarm, and resets this malfunction alarm. The write address counter 2b, the read address counter 3b, and the capacity monitoring counter 4a are reset by the negative logic reset signal (k) output in addition to the part 6b to restore the write address (d) and the read address (f). To do.

Similarly, when the capacity monitoring counter 4a malfunctions, the malfunction detection restoration unit 6 causes the data amount n
The comparison unit 6a detects a mismatch between (j) and the data m (g), and outputs a malfunction alarm. The malfunction alarm generates a negative logic reset signal (k) to write address counter 2b and read address counter 3b. And the capacity monitoring counter 4a is restored.

FIG. 3 is a diagram showing an example of detecting the amount of data used in the present invention. In the figure, D is a memory capacity, wc is a write clock, w is a write address, n is a data amount (usage detecting unit 4), rc is a read clock, r is a write address, and m is a data amount (difference detecting unit 5). Is. Now D =
9 fixed.

(1) When w> r ───── FIG. 3A When wc = 7, w = 7, rc = 2, r = 2, the data amount n = wc-rc = 7-2 = 5 Data amount m = w-r = 7-2 = 5 (2) When w = r ───────────────────────────────────────────────── , Data amount n = wc-rc = 5-5 = 0 Data amount m = w-r = 5-5 = 0 (2) In the case of w <r ───── FIG. 3 (C) wc = 11, w = 2, rc = 6, r = 6, the data amount n = wc-rc = 11-6 = 5 the data amount m = D- (r-w) = 9- (6-2) = 9-4
= 5

[0030]

As is apparent from the above description, according to the present invention, when the write / read address counter malfunctions, the malfunction is notified by the output of a malfunction alarm, and the write / read address counter and the capacity monitoring counter are reset. By doing so, the write / read address counter can be restored. Further, even when the capacity monitoring counter malfunctions, the malfunction can be detected and the recovery operation can be performed in the same manner, and the failure of the data system due to the mismatch between the write / read address and the data can be avoided. It has an effect that it greatly contributes to the improvement of reliability.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of the present invention.

FIG. 2 is a diagram showing a time chart of the circuit of the present invention.

FIG. 3 is a diagram showing an example of data usage detection according to the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional example.

[Explanation of symbols]

1 is memory 2 is write controller 2a is controller 2b is write address counter 3 is read controller 3a is controller 2b is read address counter Imaging dose detector 4a is capacity monitoring counter 5 is difference detector 6 Malfunction detection recovery Part 6a is comparison part 6b is reset part

Claims (1)

[Claims] 1. A write controller (2) having a memory (1) for storing data, and a write address counter (2b) for generating a write address for the memory (1) from a write clock, the memory (1) ) To a read control section (3) having a read address counter (2b) for generating a read address from the read clock, and by performing up / down counting of the write clock and the read clock in the memory (1). A usage detector (4) for monitoring the data capacity, and a difference detector for calculating the data usage in the memory (1) from the difference between the write address and the read address.
(5), the write address counter (2b), the read address counter (3b), and the usage amount detection section (4) Comparison unit (6a) for comparing the amount of data in the memory (1) monitored by the unit (4) with the amount of data in the memory (1) calculated by the difference detection unit (5) and the comparison result Reset section (6
A malfunction recovery method for a memory access counter, which is provided with a malfunction detection recovery unit (6) provided with b).