JPH08221116A - Digital input device with diagnostic function - Google Patents

Abstract

PURPOSE: To provide a digital input device with the diagnostic function which can be made highly reliable by preventing misdiagnosis. CONSTITUTION: The digital input device is provided internally with a duplicated input circuit 2, a comparison input generating circuit 3, a comparative decision circuit 4 which detects abnormality of the input circuit 2, a signal change detecting circuit 7 which detects a change point of the signal outputted from the input circuit 2, a counter 5 which counts up at intervals 1/n time as long as the pulse width of the digital signal inputted from a plant and clears its counted value with the output of the signal change detecting circuit 7, and flip-flop circuits 8 and 9 which temporarily store an abnormality detection signal, and outputs the abnormality detection signal when the counted value reaches a specific value. Consequently, a diagnosis is prevented from being taken at the signal change point and high reliability is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plant control device using a computer, and more particularly to an input device for inputting a status signal from a plant which requires high speed and high reliability.

[0002]

2. Description of the Related Art In a conventional input device, a simulated input is applied within a preset diagnosis time to diagnose an abnormality. Further, as disclosed in Japanese Patent Laid-Open No. 59-47612, a dual input circuit section for taking in input information from a system and a mismatch between outputs from these dual input circuit sections are detected. An inconsistency detection gate is provided to diagnose an abnormality in the input circuit section.

[0003]

However, in the above-mentioned prior art, the timing for detecting the mismatch of the output signals from the duplicated input circuit is not taken into consideration, and therefore, the input is made from the grid or the plant. At the change point of the signal, the output from the input circuit unit becomes unstable, and if the diagnosis is executed at this timing, there is a risk of erroneous diagnosis.

It is an object of the present invention to provide a digital input device with a diagnostic function which can improve reliability by preventing erroneous diagnosis.

[0005]

SUMMARY OF THE INVENTION The present invention comprises a dual input circuit for inputting a digital signal from a plant,
In a digital input device having a comparison circuit for comparing the output signals from the duplicated input circuits and detecting the presence or absence of abnormality, a signal change detecting means for detecting a change point of a signal output from the input circuit, Counting means for counting the pulse width of the digital signal input from the plant at intervals of 1 / n, and clearing the count value by the output of the signal change detecting means, and an abnormality detection signal from the comparison circuit temporarily. And holding means for storing the abnormality detection signal stored in the holding means when the count value of the counting means reaches a predetermined value.

[0006]

According to the present invention, the count value stored in the counting means is cleared when the change point of the signal input from the plant is detected by the signal change detecting means.
At the change point of the signal, the abnormality detection signal is not output, and the occurrence of erroneous diagnosis can be prevented.

[0007]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows an embodiment of the present invention. The digital input signal 24 from the plant is converted in signal level by the input circuit 2, and at the same time the input state is detected by the comparison input generation circuit 3. The comparison input generation circuit 3 generates a comparison signal 12 (V1) according to the detected input state,
The comparison signal 12 is output to the comparison / determination circuit 4. The comparison / determination circuit 4 compares and determines the digital input signal (hereinafter, DI signal) 11 obtained from the input circuit 2 and the comparison signal 12, and outputs the determination result.

Output signal (judgment result) 1 of the comparison / judgment circuit 4
5 is a flip-flop circuit (F / F-
A, F / F-B) 8 and 9 are output. Since the comparison input generation circuit 3 and the input circuit 2 are in parallel, the comparison signal 12 and the DI signal 11 become unstable at the point where the input signal 24 from the plant changes, and if the comparison determination result is output at this timing. There may be a misdiagnosis.
In order to avoid this, the output signal (judgment result) 15 of the comparison / judgment circuit 4 at the time of signal stabilization by the diagnosis timing generation circuit 6, the signal change detection circuit 7, and the diagnosis number counter 5
A diagnostic result output flip-flop circuit (F / F-A,
F / F-B) It is output after being latched in 8 and 9.

The DI signal 11 and the ERR-N signal (diagnosis result) 19 are input / output via the bus interface circuit 10.
Connect to the O-bus 20. In response to a read request from the host computer, the DI signal 11 and the ERR-N signal (diagnosis result) 19 are simultaneously output to the I / O bus 20, and the host computer confirms the ERR-N signal (diagnosis result) 19 DI signal 1
1 can be used.

FIG. 2 shows an application example based on the circuit configuration shown in FIG. As the comparison input generation circuit 3, a signal conversion circuit composed of a comparator circuit 22 and a flip-flop circuit 23 is used, and is connected to the input circuit 2 by a capacitor 21. The value V1 of the comparison signal 12 is set to the same level as the DI signal 11, and the comparison determination circuit 4 sets the determination conditions that both signal levels match.

The diagnostic number counter 5 is a quaternary counter and counts the diagnostic command signal 14 output from the diagnostic timing generation circuit 6. The count value of this count is 2
At the time of, the signal 17 is output to latch the output signal (judgment result) 15 of the comparison / judgment circuit 4 in the diagnostic result output flip-flop circuit (F / FA) 8, and when the count value reaches 3, the signal 18 is output. Is output to latch the output signal 16 of the diagnostic result output flip-flop circuit (F / F-A) 8 in the diagnostic result output flip-flop circuit (F / FB) 9 and to the bus interface circuit ERR.
Output as -N signal (diagnosis result) 19.

When the count value of the diagnosis number counter 5 reaches 4, or when the DI signal 11 changes before counting the diagnosis command 14 three times in succession, the counter is cleared to prepare for the next diagnosis. .

FIG. 3 shows another application example based on the circuit configuration shown in FIG.

As the comparison input generation circuit, a signal level conversion circuit using the same photo coupler as the input circuit 2 is used,
The value V1 of the comparison signal 12 is at the same level as the DI signal 11. The determination conditions in the comparison / determination circuit 4 and the method of outputting the determination result 15 are the same as in FIG.

FIG. 4 shows a time chart of the failure diagnosis circuit in the application example shown in FIGS.

During normal operation, DI signal 11 and comparison signal 12
Becomes the same level, and the comparison / determination circuit output 15 is constant, but at the change point of the input signal 24, the DI signal 11 and the comparison signal 12 change at the response speeds of the respective circuits, so that the comparison / determination circuit output 15 is temporarily changed. An abnormal waveform is generated in the. In order to avoid the diagnosis at this point, the diagnosis command 14 is counted by the diagnosis number counter 5 and the diagnosis result latch signal 17 is output at the time of continuous two-time counting (points: n-1, n + 3) to make a comparison and judgment circuit. The output 15 is latched in the diagnostic result output flip-flop circuit (F / F-A), and the diagnostic result output control signal 18 is output during continuous three-time counting (point: n, n + 4) to output the diagnostic result output flip-flop. The output 16 of the flip-flop circuit (F / FA) is latched in the diagnosis result output flip-flop circuit (F / FB) and output as ERR-N (diagnosis result) 19.

The diagnostic number counter 5 is cleared by the counter clear signal 13 when the count or input signal 24 changes four times or more.

In order to output the diagnostic result to the bus interface circuit 10 once after the DI signal 11 changes, the diagnostic command signal 14 must be provided three times or more within the minimum input pulse width Tmin of the input signal 24. Becomes Therefore, the pulse interval Ts of the diagnostic command signal 14 is set to 1/4 to 1/5 of Tmin.

FIG. 5 shows a time chart of the failure detection operation in the application example shown in FIGS. If an abnormality occurs due to damage or deterioration of parts in the input circuit, DI
It is assumed that the signal 11 should be at the low level but should remain at the high level. The DI signal 11 becomes High level after the abnormality occurrence point, and the comparison result with the comparison signal 12 does not match. As a result, the output 1 of the comparison / determination circuit
5 becomes Low level (abnormal), and diagnostic result latch signal 17
Diagnostic output flip-flop circuit (F / F-
A), and the output 16 of the diagnostic result output flip-flop circuit (F / FA) becomes Low level (abnormal). Diagnostic result output flip-flop circuit (F / F-
The output 16 of A) is latched by the diagnostic result output control signal 18 in the diagnostic result output flip-flop circuit (F / FB) and is output to the diagnostic result output flip-flop circuit (F / F-B).
The output 19 of FB), that is, the ERR-N signal becomes Low level (abnormal).

FIG. 6 shows a redundant configuration example of the input device, which is an example in which one signal source is taken in by two different input devices 1.

The input signal 24 on the plant side is converted into the DI signal 11 in each digital input device 1,
It is taken into the host computer together with the ERR-N signal 19. The system software uses one digital input device 1 as a regular system and the other digital input device 1 as a standby system, and while monitoring the ERR-N signal 19, performs plant control by the DI signal 11 fetched from the regular system. . When an abnormality is detected in the regular system, the DI signal 11 on the standby system side is used to improve the reliability of the system.

[0023]

According to the present invention, it is possible to suppress the execution of diagnostic processing at a change point of an input signal, prevent erroneous diagnosis, and achieve high reliability.

[Brief description of drawings]

FIG. 1 shows an example of a circuit configuration of a digital input device according to the present invention.

2 is an application example based on the circuit configuration shown in FIG. 1 (NO
1).

FIG. 3 is an application example based on the circuit configuration shown in FIG. 1 (NO
2).

FIG. 4 is a time chart of a failure detection operation in the application example of FIGS. 2 and 3.

FIG. 5 is a time chart of a failure detection operation in the application examples of FIGS.

FIG. 6 is a diagram illustrating an example of a redundant configuration of an input device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital input device, 2 ... Input circuit, 3 ... Comparison input generation circuit, 4 ... Comparison determination circuit, 5 ... Diagnostic number counter,
6 ... Diagnostic timing generation circuit, 7 ... Signal change detection circuit,
8, 9 ... Diagnostic result output flip-flop circuit, 10 ...
Bus interface circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location G05B 15/02 9063-3H G05B 15/02 A (72) Inventor Yoshiyuki Futashi Oita Mika, Hitachi City, Ibaraki Prefecture 5-2-1, Machi, Hitachi Process Computer Engineering Co., Ltd. (72) Kenji Kikuchi, 5-2-1, Omika-cho, Hitachi City, Hitachi City, Ibaraki Prefecture (72) Inventor, Yasunori Nomoto Ibaraki, Ibaraki 5-2-1 Omika-cho, Hitachi, Ltd. Inside the Omika Plant, Hitachi Ltd. (72) Inventor, Yoshifumi Kurisu 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi Ltd.

Claims (1)

[Claims] 1. A digital input device having a dualized input circuit for inputting a digital signal from a plant and a comparison circuit for comparing an output signal from the dualized input circuit to detect the presence or absence of an abnormality. In the signal change detecting means for detecting the change point of the signal output from the input circuit, and counting at intervals of 1 / n with respect to the pulse width of the digital signal input from the plant. A counting unit that clears the count value by output and a holding unit that temporarily stores the abnormality detection signal from the comparison circuit are provided, and when the count value of the counting unit reaches a predetermined value, the holding unit stores the count value. A digital input device with a diagnostic function, which outputs a stored abnormality detection signal.