KR0150652B1 - Buffer error detector of digital transmitter - Google Patents

Abstract

The present invention relates to a buffer error detection device of a digital transmission device, which performs a parity calculation when an error occurs in the transmission data of the digital transmission device to self-diagnose a buffer failure and improve the reliability of the system.

The present invention has a counter means for counting an external input write clock and read clock to a set value to generate a write address signal, a read address signal and a write / read enable signal, and a write / read address signal obtained by the counter means. Buffer means for storing external input write data in the address and outputting the data in the address, and the external write data and buffer according to the write / read enable signal and the write / read clock inputted from the counter means. This is achieved by means of error calculating means for detecting an error by calculating parity for read data buffered from the means.

Description

Buffer error detection device of digital transmission device.

1 is a configuration diagram of a buffer system of a conventional digital transmitter.

2 is a block diagram of a buffer error detection system of the present invention.

3 is a detailed configuration diagram of the error detection means in FIG.

* Explanation of symbols for main parts of the drawings

200: counter means 201: buffer means

202: error calculating means 202a: first parity calculating means

202b: second parity calculation means 202c: comparison means

202d: error detection means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to performance monitoring of a digital transmission device, and more particularly, to a buffer error detection device of a digital transmission device for self-diagnosing a failure of a buffer for transmitting data using parity and improving the reliability of the system.

In general, a digital transmission device converts a low speed signal into a high speed signal to transmit data, and conversely, converts a high speed signal into a low speed signal to transmit data.

The buffer is a circuit capable of converting signals of two different speeds in order to bundle the low-speed electric signals and convert them into one high-speed signal.

At this time, the two different clock signals are counted to form a corresponding address and used as an enable signal for buffering write data.

As shown in FIG. 1, the buffer device of the conventional digital transmission apparatus counts the write clock signal LWCK and the read clock signal LRCK up to a set value, thereby writing the write address signal LWAD and the read address. The counter means 100 for generating the signal LRAD and the write data LWD input from the outside are stored in the corresponding address by the write address signal LWAD generated by the counter means 100 and the read address signal ( And buffer means 101 for outputting data stored in the address by LRAD.

As described above, in the buffer device of the conventional digital transmission device configured, first, when the write clock LWCK and the read clock LRCK are input from the outside, the counter means 100 counts the input write clock and the read clock to write the write address signal ( LWAD and read address signal LRAD are generated.

That is, the counter means 100 counts the write address signal and the read address signal corresponding to the number of buffers of the buffer means 101, and counts the input write clock LWCK and read clock LRCK to buffer means 101. This will enable the corresponding buffer in.

The buffer of the buffer means 101 stores the write data LWD input from the outside by the write address signal LWAD generated by the counter means 100 in the corresponding address, and also reads the read address signal LRAD. Outputs the stored data (LRDT).

However, such a buffer device of the conventional digital transmission device has a problem in that an error occurs due to a failure of the buffer when an error occurs in the transmission data to be transmitted.

Accordingly, it is an object of the present invention to provide a buffer error detection device of a digital transmission device for performing a parity calculation when the transmission data in the digital transmission device generates an error to diagnose the failure of the buffer by itself, and to improve the reliability of the system. Is in.

As a means for achieving the object of the present invention, the counter means for counting the external input write clock and read clock to a set value to generate a write address signal, a read address signal and a write / read enable signal; Buffer means for storing external input write data in the address and outputting the data in the address by the write / read address signal obtained by the counter means, and the write / read enable signal and the write / read input from the counter means. This is achieved by an error calculating means for detecting an error by calculating parity for external write data and read data buffered from a buffer means according to a clock. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. .

2 is a block diagram of a buffer error detection system of the present invention. As shown in this figure, the write clock signal WCK and the read clock RCK inputted from the outside are counted up to a set value to write address signal WD. To the counter means 200 for generating the read address signal RAD and the write / read enable signal WEN REN, and to the write / read address signal WAD obtained from the counter means 200. Buffer means 201 for outputting the write data WDT input from the outside by means, a write / read enable signal WEN RCK input from the counter means 200, and a write / read clock input from the outside; And an error calculating means 202 for detecting an error by calculating parity with respect to the external write data WDT and the read data RDT buffered from the buffer means 201 in accordance with (WCK) (RCK).

The error calculating means 202 is enabled according to the write enable signal WEN generated from the counter means 200 and the parity of the external write data WDT according to the external write clock WCK. The first parity calculation unit 202a calculates and outputs the write parity data WPDT, and is enabled in accordance with the read enable signal REN obtained by the counter unit 200, and in accordance with an external read clock RCK. Second parity calculating means 202b for calculating the parity of the read data RDT of the buffer means 201 and outputting the read parity data RPDT, and the first and second parity calculating means 202a and 202b. Comparing means 202c for comparing the read parity data and the read parity data calculated in the reference value and outputting the result data, and error detecting means 202d for detecting an error using the result data compared in the comparing means 202c. ).

Thus, the operation and effect of the present invention configured in detail as follows.

First, when the write clock WCK and the read clock RCK are input from the outside, the counter means 200 counts the input write clock and read clock, and writes the write address signal LWAD, the read address signal LRAD and the write clock. The read enable signal WEN REN is generated and input to the buffer means 201 and the error calculating means 202, respectively.

The buffer means 201 stores the write data WDT input from the outside by the write address signal WAD generated by the counter means 200 and stores the write data WDT in the corresponding address and inputs the read address signal RAD to the input address. The stored data RDT is outputted.

The error calculating means 202 reads the buffer means 201 according to the write / read enable signal WEN (REN) generated from the counter means 200 and the external write / read clock WCK (RCK). The parity is calculated on the data RDT and the external write data WDT to detect an error.

That is, as shown in FIG. 3, the error calculation means 202 receives an error calculation means when the write enable signal WEN is input from the counter means 200 and the write clock WCK is input from the outside. The first parity calculating means 202a of 202 is enabled to store the recording data WDT input from the outside in the corresponding address by the recording clock WCK, and calculates the parity for the recording data WDT. The resulting recording parity data WPDT is input to the comparing means 202c.

On the other hand, the second parity calculating means 202b of the error calculating means 202 is enabled by the read enable signal REN generated from the counter means 200 and is buffered by an external read clock RCK. The parity of the read data RDT input from 201 is calculated, and the resulting read parity data RPDT is input to the comparing means 202c.

The comparison means 202c compares the read parity data with the write parity data calculated by the first and second parity calculation means 202a and 202b, and inputs the result data into the error detection means 202d.

The error detecting means 202d of the error calculating means 202 detects an error using the comparison data obtained from the comparing means 202c.

That is, since the parity calculation is performed by comparing the input write data with the buffered read data, the performance of the buffer means 201 can be monitored.

As described in detail above, according to the present invention, when an error occurs in the transmission data in the digital transmission device, the failure of the buffer can be diagnosed by performing parity calculation on the write data and the buffered read data to be transmitted. As a result, the reliability of the system is improved.

Claims (1)

An external input by counter means for counting an external input write clock and read clock to a set value and generating a write address signal, a read address signal and a write / read enable signal; and an external input by a write / read address signal obtained by the counter means Buffer means for storing the record data in the address and outputting the data in the address; and calculating parity with respect to the external record data in accordance with the write enable signal generated from the counter means and according to the external write clock. First parity calculating means for outputting the write parity data, an enable signal according to the read enable signal obtained by the counter means, and parity of the read data of the buffer means according to an external read clock to calculate read parity data. Second parity calculating means for outputting said first and second parity calculating means A comparison means for comparing the read parity data and the read parity data calculated in the step, and outputting the result data, and an error detection means for detecting an error using the result data compared by the comparison means, inputting in the buffer means. A buffer error detection of a digital transmission device comprising error calculation means for detecting an error by calculating parity for external write data and read data buffered from the buffer means according to the recorded write / read enable signal and the read / write clock. Device.