JPH1145213A - Method and circuit for monitoring fifo memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor the loss of frame data in an FIFO(first-in first-out) memory and to monitor the error of data by a parity check. SOLUTION: Sequence numbers are added, frame by frame, by using free bits of data written in the data FIFO memory 1. The loss of frame data is monitored by monitoring whether or not sequence numbers are successively read out of the read data of the data FIFO memory 1. Further, the parity of the data is checked by using a parity FIFO memory 8 to monitor errors of the data. Operation abnormality of the FIFO memories is monitored according to both the monitoring results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving circuit of a high-speed data transmission apparatus, which is used for a FIFO (First In Firs
t Out) A FIFO memory monitoring method and circuit for monitoring frame data loss and data errors caused by passing through a memory.

[0002]

2. Description of the Related Art Conventionally, this type of FIFO memory monitoring circuit employs a configuration as shown in FIG. That is, the parallel data 2 composed of n bits (n> 1) is stored in the FIFO
As a monitoring method when outputting data via a memory, a data FIFO memory 1 and a parity FIFO memory 8 are provided, and data error monitoring is performed by a vertical parity check, thereby monitoring data error via the FIFO memory. It is configured to perform.

The data FIFO memory 1 writes parallel data 2 using a FIFO memory write frame pulse 3 and a FIFO memory write clock 4, and outputs parallel data 2 using a FIFO memory read frame pulse 6 and a FIFO memory read clock 7. Read 5 out.

The parity operation circuit 9 performs a vertical parity operation on the write data 2 and outputs the result to the parity F
Output to the IFO memory 8.

The parity FIFO memory 8 writes the output of the arithmetic circuit 9 by the FIFO memory write frame pulse 3 and the FIFO memory write clock 4 in the same manner as the data FIFO memory 1, and the FIFO memory read frame pulse 6 Data is read by the FIFO memory reading clock 7.

By using the read data of the parity FIFO memory 8 and the read data 5 of the data FIFO memory 1, the parity monitoring circuit 10 monitors data errors.

[0007]

The conventional FIFO memory monitoring circuit monitors data errors and the like by a parity check. However, when a FIFO memory is used, a frame unit due to a slip of a frame pulse or the like is likely to occur. Monitoring of malfunction such as data loss is difficult by parity check. Further, the loss of data as described above due to the FIFO memory is caused by two FIFOs.
There is also a problem in that monitoring that can occur in any of the memories and that is performed only by parity check is not sufficient.

(Object) It is an object of the present invention to monitor the loss of frame data due to the use of a FIFO memory.

It is another object of the present invention to simultaneously monitor data error and frame data loss by parity check, and comprehensively monitor data error and malfunction due to use of a FIFO memory. .

[0010]

A FIFO memory monitoring method according to the present invention is a FIFO memory monitoring method for detecting a loss of frame data by a FIFO memory. Add the unit sequence number,
When reading the data FIFO memory, the sequence number is detected, and the normality of the frame data is monitored based on whether or not the sequence number is continuously read.

In addition, when the data is written to the data FIFO memory, a parity operation is performed on the data, and the parity operation result is written into the parity FIFO memory.
When reading data from the IFO memory, the parity F
The parity operation result is read from the IFO memory, and the parity of data read from the data FIFO memory is monitored to monitor data errors in the data FIFO memory.

Further, the FIFO memory monitoring circuit of the present invention comprises a data FIFO memory, a sequence number insertion circuit for inserting a sequence number in frame data units on the data write side of the data FIFO memory, and a data FIFO memory data. A sequence number monitoring circuit for extracting the inserted sequence number on the reading side and monitoring the continuity thereof. A parity for writing the parity calculation result of the input frame data and reading the parity calculation result for the parity monitoring calculation of the output frame data in synchronization with writing and reading of the frame data to and from the data FIFO memory. It has a FIFO memory and performs data error monitoring by parity check in addition to loss of frame data.

(Operation) A sequence number is added to each frame using empty bits of data to be written in the FIFO memory. The loss of the frame data is monitored by monitoring whether the sequence number is continuously read from the FIFO memory read data. Also, data errors are monitored by performing a parity check on the data using a parity FIFO memory. Based on both monitoring results, the operation abnormality of the FIFO memory is monitored with high accuracy.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

[1] Description of Configuration Next, the configuration of the embodiment of the present invention will be described in detail with reference to FIG.

The writing side of the data FIFO memory 1 includes a sequence number generation circuit 12 for generating a sequence number to be added to the parallel data (n> 1) composed of n bits in units of frames, and a vacant bit position of the data. The circuit includes a FIFO memory write-side pulse generation circuit 13 for generating a pulse as shown in the figure, and a sequence number insertion circuit 11 for inserting a sequence number into a vacant bit position of data.

The write side of the parity FIFO memory 8 performs a vertical parity operation on the data to which the sequence number has been added, and outputs the result to the parity FIFO memory 8, a parity operation circuit 9, and a data FIFO.
The reading side of the memory 1 includes a FIFO memory reading side pulse generation circuit 14 indicating a sequence number insertion position of the read data 5 and a sequence number monitoring circuit 15 for monitoring a sequence number added to the read data.

The read side of the parity FIFO memory 8 is provided with a parity monitoring circuit 10 for performing a parity check using the read data of the parity FIFO memory 8 and the read data 5 of the data FIFO memory 1.

Further, the configuration of the monitoring result output side includes a sequence number monitoring circuit 15, a parity monitoring circuit 10, and a monitoring result output circuit 16 for outputting a monitoring result of the FIFO memory from each output result.

[2] Description of Operation Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

In the data write operation, the data FIFO memory 1 and the parity FIFO memory 8 are used.
Are the frame pulses 3 and F for writing to the FIFO memory.
Data is written by an I / O memory write clock 4, and data is read by a FIFO memory read frame pulse 6 and a FIFO memory read clock 7.

As shown in FIG. 2, write data (n-bit parallel; n> 1) is written in the data FIFO memory 1 (a).
When writing the write data (a), the FIFO memory write-side pulse generation circuit 13 generates a pulse signal (c) which becomes low level at an empty bit position of the write data (a). Further, the sequence number generation circuit 12 generates a sequence number (b) to be added to the write data (a) on a frame basis.

In the sequence number insertion circuit 11, the FIF
The sequence number (b) generated by the sequence number monitoring circuit 15 is inserted using the pulse signal (c) indicating the empty bit position generated by the O memory write side pulse generation circuit 13. The memory write data (d) to which the sequence number is added is written to the data FIFO memory 1.

The parity operation circuit 9 performs a vertical operation on the memory write data (d) to which the sequence number has been added, and writes the output to the parity FIFO memory 8.

Next, as shown in FIG.
When reading the O memory 1, the sequence number monitoring circuit 15 uses the pulse signals (g) and (g ′) indicating the insertion position of the sequence number generated by the FIFO memory read side pulse generation circuit 14 to read the memory. Data (e),
The sequence number of (e ') is extracted to monitor whether the sequence number is normal. Further, the parity monitoring circuit 10 checks based on the read data from the parity FIFO memory 8 and the read data 5 from the data FIFO memory 1.
Then, the monitoring results of the sequence number monitoring circuit 15 and the parity monitoring circuit 10 are output to the monitoring result output circuit 16.

Next, the operation of the present invention for monitoring abnormalities such as frame loss will be described more specifically.

First, when the write and read operations of the FIFO memory are normal, as shown in the time chart of FIG. 3A, the memory read data (e) is generated by the pulse signal (g).
Since the sequence number extracted from the sequence number matches the sequence number (f) at the time of writing and is detected as a continuous number, the monitoring result (h) of the sequence monitoring circuit 15 indicates a normal state and there is no loss of frame data. Can be confirmed.

In the case where the frame data is lost due to the abnormal operation of the FIFO memory, FIG.
As shown in the time chart of FIG. 7, the sequence number to be extracted does not match the sequence number (f ′) at the time of insertion and is detected as a discontinuous number because of the lack, so the monitoring result (h ′) of the sequence monitoring circuit 15 is obtained. ) Is an output indicating an abnormal state from the discontinuous number position, and a malfunction due to loss of frame data is detected.

Further, by using the parity FIFO memory 8 together to detect a data error by the FIFO memory, any one of the F
It is possible to monitor malfunctions such as loss of data in the IFO memory.

The monitoring results of the sequence number monitoring circuit 15 and the parity monitoring circuit 10 are comprehensively determined in the monitoring result output circuit 15 by a combination of the monitoring results. That is, the monitoring result of the parity monitoring circuit 10 is F
It is possible to monitor the data error rate caused by passing through the IFO memory, and to monitor the abnormal state by increasing the data error rate in the case of malfunction due to loss of frame data or data of the parity operation result. On the other hand, the sequence number monitoring circuit 15
Since the monitoring result of (1) allows only monitoring of an abnormal state of loss of frame data, it is possible to perform more accurate monitoring including mutual monitoring of the operation of each monitoring circuit.

[0030]

As described above, according to the present invention, the frame data is written in the FIFO memory by adding the sequence number of each empty frame to the empty bits.
By detecting whether or not the sequence number is continuously read on the reading side of the FIFO memory, it is possible to reliably monitor a malfunction in which frame data is lost in the FIFO memory.

Further, by using a parity FIFO memory for monitoring by parity check between the input side frame data and the output side frame data of the FIFO memory, it is possible to detect a data error caused by passing through the FIFO memory. Further, the monitoring result based on the error rate by the parity check and the monitoring result based on the sequence number enable the FIFO memory to be monitored with higher accuracy.

[0032]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a time chart for explaining an operation of inserting a sequence number on a FIFO memory writing side.

FIG. 3 is a time chart illustrating an operation of monitoring a sequence number on a FIFO memory reading side.

FIG. 4 is a block diagram showing an example of a conventional FIFO memory monitoring circuit.

[Explanation of symbols]

 1 FIFO memory for data 2 Write data 3 Frame pulse for FIFO memory write 4 Clock for FIFO memory write 5 Read data 6 Frame pulse for FIFO memory read 7 FIFO memory read clock 8 Parity FIFO memory 9 Parity operation circuit 10 Parity monitor circuit 11 Sequence number insertion circuit 12 Sequence number generation circuit 13 FIFO memory write side pulse generation circuit 14 FIFO memory read side pulse generation circuit 15 Sequence number monitoring circuit 16 Monitoring result output circuit

Claims (5)

[Claims] 1. A FIFO for detecting loss of frame data caused by passing through a data FIFO memory.
In the memory monitoring method, a sequence number for each frame is added to an empty bit in frame data when writing to the data FIFO memory, and the sequence number is continuously read when the data FIFO memory is read. A FIFO memory monitoring method, wherein the normality of frame data is monitored depending on whether or not the frame data has been output. 2. A parity operation of data is performed at the time of writing to the data FIFO memory, a parity operation result is written to the parity FIFO memory, and at the time of reading data from the data FIFO memory, the parity operation result is read from the parity FIFO memory. FI for read data
2. The FIFO according to claim 1, wherein data errors in the data FIFO memory are monitored by monitoring parity with data read from the FO memory.
O memory monitoring method. 3. A data FIFO memory and a data FIFO memory.
A sequence number insertion circuit for inserting a sequence number in frame data units on the data writing side of the FIFO memory, and a sequence number monitoring circuit for extracting the inserted sequence number and monitoring the continuity of the inserted sequence number on the data reading side of the data FIFO memory A FIFO memory monitoring circuit, comprising: 4. A sequence number generating circuit for generating a sequence number in units of frame data, and a write-side pulse generating circuit for generating a pulse indicating a vacant bit position of the frame data, wherein the sequence number inserting circuit includes 4. The FIFO memory monitoring circuit according to claim 3, wherein said sequence number is inserted by a pulse indicating an empty bit position. 5. A method for writing a parity operation result of input-side frame data and reading the parity operation result for parity-monitoring operation of output-side frame data in synchronization with writing and reading of frame data to and from a data FIFO memory. 5. A memory according to claim 3, further comprising a parity FIFO memory, wherein data errors are monitored by parity check in addition to loss of frame data.
A FIFO memory monitoring circuit as described in the above.