JPS6316776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a diagnostic method, and particularly to a diagnostic method suitable for diagnosing code conversion circuits and error detection/correction circuits.

[Prior art]

Conventionally, code conversion circuits and error detection/correction circuits have been used in main memory, external memory, or data transmission systems used in information processing devices such as computers, and are useful for improving reliability. As a method for diagnosing these code conversion circuits and error detection/correction circuits, a method has conventionally been proposed in which the code conversion function, error detection function, and error correction function are tested by generating pseudo errors.

As an example of a conventional diagnostic method, diagnosis of a magnetic tape control device will be explained with reference to FIG.

1, the internal data path of magnetic tape controller 20 and magnetic tape unit 6 are shown.
In the GCR (Group Coded Recording) method of 6250RPI, 4-bit data is converted to 5-bit data, and this 5-bit recording information is written on a magnetic tape using the NRZI method. In the data converted to 5 bits, only 2 bits of "0" are consecutive, so that a self-synchronizing demodulation circuit can be used like the PE method.

Write data WD is sent through selector 2.
ECC for error correction that occurred in ECC generation circuit 1
After appending the (Error Correcting Code) byte,
The signal is code-converted by the 4-5 conversion circuit 3, further modulated into the NRZI code by the modulation circuit 4, and sent to the magnetic tape device 6. On the other hand, the data read by the magnetic tape device 6 is demodulated by the demodulation circuit 7 of the magnetic tape control device 20, and is demodulated by the 5-4 conversion circuit 8.
After being inversely transformed, the signal is sent to the error detection/correction circuit 9. If an error is detected here,
Error correction is performed using ECC. 6250RPI
In the GCR method, 1 byte is added to 7 bytes of data.
ECC is added to make it possible to correct errors that occur simultaneously across two tracks.

In FIG. 1, when diagnosing the error detection/correction circuit 9, the output of the microprocessor 10 controls the AND circuit 9, forcibly closes the output of the modulation circuit 4, and outputs the signal to the magnetic tape device 6. By generating a pseudo fault in the magnetic tape device 6, demodulation circuit 7, and 5-
Error detection/correction circuit 9 via conversion circuit 8
The pseudo-failure mentioned above is detected and corrected. However, in this method, (1) it is necessary to provide an AND circuit 5 on the output side of the modulation circuit 4, which increases the amount of hardware. (2) The instruction to close the AND circuit 5 is issued by the microprocessor 10 during diagnosis execution, but since the microprocessor 10 operates under program control, the processing speed of the microprocessor 8 is slower than the data transfer speed. Therefore, it is difficult to synchronize with the data, and it is difficult to cause a pseudo failure to any data in one data block. (3) For the reason mentioned in (2) above, usually,
Although the AND circuit 5 is closed before data transfer, a pseudo failure occurs from the beginning of the data block. In other words, no data is input to the faulty track, so the 5-4 conversion circuit 8 does not operate.
Therefore, the portion related to error detection inside the 5-4 conversion circuit 8 cannot be diagnosed. There are drawbacks such as.

Another method for diagnosing the error detection/correction circuit 9 is to modify a part of the circuit shown in FIG. 1 to configure it as shown in FIG. 2, and to arbitrarily set the ECC. That is, a separate selector 12 is connected between the ECC generation circuit 1 and the selector 2 in FIG. Instead of generating the ECC from data, the microprocessor 10 generates it arbitrarily, sets it in the ECC register 11, and selector 2 adds it to the data. In this way, by arbitrarily setting ECC, it is a method of simulating failure and diagnosis, and this method utilizes the use of ECC for error detection and correction. However, with this method, (1)
In order to arbitrarily set the EC, hardware such as a selector 12 and an ECC register 11 is required. (2)１
In order to cause a failure in any part of a block, it is necessary to set the ECC in synchronization with the timing at which the ECC is added. (3) It is not possible to cause pseudo failures in the data itself. There are drawbacks such as.

Furthermore, as another method for diagnosing the error detection/correction circuit, the microprocessor 10 shown in FIG.
Instead, there is a method of generating arbitrary ECC from the security panel (see Japanese Patent Application Laid-open No. 162162/1983), or bypassing the write data as it is to the reading circuit, and diagnosing the circuit during reading without using the medium. method (see Japanese Patent Application Laid-Open No. 53-122341),
Or give diagnostic data to the ECC generation circuit,
A method of generating ECC including errors and diagnosing error detection/correction circuits and ECC generation circuits (Unexamined Japanese Patent Publication No.
52-94744).

However, since both have the same drawbacks as mentioned above, they cannot be said to be the best solution.

[Purpose of the invention]

The purpose of the present invention is to eliminate these conventional drawbacks by creating a pseudo failure at any point in the data without synchronizing the data flow, and by causing a pseudo fault to occur at any point in the data, thereby reducing the code conversion circuit and error detection/correction circuit. An object of the present invention is to provide a diagnostic method that can realize failure diagnosis with a simple circuit.

[Summary of the invention]

The diagnostic method of the present invention is a device that converts and outputs data to which ECC has been added, and also performs code inversion of input data to detect and correct errors. The present invention is characterized by providing a circuit for converting into a defined code pattern and outputting it, and forming a path for returning the output of the device to the input, thereby diagnosing the code inverse conversion circuit and the error detection/correction circuit.

[Embodiments of the invention]

Hereinafter, a case where the present invention is applied to self-diagnosis of a magnetic tape control device will be described as an example. FIG. 3 is a block diagram inside a magnetic tape control device showing an embodiment of the present invention.

In FIG. 3, the channel buffer 16 is
A memory that stores write data when executing self-diagnosis.The microprocessor 10 executes a diagnostic program in response to a start signal S when the power is turned on, and the test data read from the memory 13 is sent to the selector 15. is written to this channel buffer 16 through. This test data is sequentially output from channel buffer 16 and is
An additional circuit 17 adds ECC, a 4-5 conversion circuit 23 converts the code, and a modulation circuit 4 modulates the signal. During self-diagnosis, the output of the modulation circuit 4 is directly input to the demodulation circuit 7 through the selector 14,
5-4 The data that has passed through the conversion circuit 8 and the error detection/correction circuit 9 is taken into the microprocessor 10, and the data written to the channel buffer 16 is conveyed to diagnose each of the above circuits. If there is a failure, it is reported to the outside of the device by flashing LEDs, etc. In addition, with magnetic tape, 9
In order to record by track, each circuit from 3 to 9 has 1
It is equipped with logic for nine circuits so that 9 bits of data (8 bits of data + 1 bit of parity) can be processed in parallel.

The 4-5 conversion circuit 23 performs code conversion on serially inputted 4-bit data for each track based on certain rules, and serially outputs it as 5-bit data. There is a rule in this 4-5 conversion that there is no pattern in which three or more 0's follow in the 5 bits after conversion, so in the conventional 4-5 conversion circuit, a pattern that continues three or more 0's is output. It was never done. On the other hand, the 4-5 conversion circuit 23 of this embodiment has an instruction line 24 from the microprocessor 10, and when this instruction line 24 is "0", it performs the same 4-5 conversion as the conventional one. , when the instruction line 24 is “1” and the first three bits of the four input data bits are “0”, all five output bits are “0”, that is, the normal four bits are “0”.
-5 conversion outputs an undefined pattern.

Figure 5 shows a GCR conversion diagram. As shown in FIG. 5, the values of data 0000 to 1111 are converted into record values of 11001 to 01111 by the 4-5 conversion circuit 23. Since the record value has only 2 consecutive 0 bits, even if it is written to tape using the NRZI method, the PE
A self-synchronizing demodulation circuit 7 can be used in the same manner as in the above method. Note that the 4-bit data value forms 8 bits in data subgroups A and B for each track, with the last bit in subgroup B being the ECC bit. Parity bit 8 on track 4
Arrange bits. Also, the 5-bit record value is written to the magnetic tape with storage subgroups A and B forming 10 bits.

In the embodiment shown in FIG. 3, when a data value "0001" marked with a star is input during self-diagnosis, it is not converted to "11011" but to "00000".

The 5-4 conversion circuit 8 performs an operation opposite to the 4-5 conversion, converting 5 bits of input into a 4-bit output. Normally, this circuit 8 outputs a pattern in which all 4 bits are "0" when inputting 5 bits of an undefined pattern like the one described above, and at the same time, the input of an undefined pattern is detected at the subsequent stage. It is reported to the error detection/correction circuit 9.

When performing self-diagnosis with a circuit such as the one described above, the microprocessor 10, among the series of data set in the channel buffer 16 for diagnosis, sets the 4-bit value "0001" only in the corresponding part of the track where a pseudo failure is to occur. Insert the pattern in advance. Then, the instruction line 24 is set to "1" to issue a write (WR) instruction. As a result, the data in the channel buffer 16 starts to pass through the channels 17 to 9, but at this time, the 4-5 conversion circuit 23 converts to the above "0001".
If you input the pattern "00000", it will output the pattern "00000". This data is given to the 5-4 conversion circuit 8 via circuits 4 to 7, where it is converted into data "0000" as an undefined pattern, and at the same time, the error detection/correction circuit 9 detects that an undefined pattern has been input. will be reported. In this case, the written pattern "0001" and the read pattern "0000" are different, so if the 5-4 conversion circuit 8 and the error detection/correction circuit 9 are normal, the parity bit will be correct when the fault is only in one track. and ECC
By using the information that the above-mentioned undefined pattern has been input when there are two tracks, the error is detected and corrected by the circuit 9, and the microprocessor 10 receives exactly the same data as the written data. Can be done.

In this way, by using the instruction line 24 and a specific data pattern, a pseudo failure is caused in the data, and 5
-4 Conversion circuit and error detection/correction circuit can be diagnosed. Moreover, by including a specific pattern in advance in the data to be provided, it is possible to generate a pseudo failure only in that part, so there is no need to synchronize the data flow between circuits 16 to 4. It is possible to create a false fault on any part of any track in a data block.

The 4-5 conversion circuit 23 in this embodiment can be realized by simply adding simple hardware to the conventional 4-5 conversion section 26, as shown in FIG.
That is, in FIG. 4, since the instruction OD from the microprocessor 10 is normally "0", the output of the NAND circuit 29 is "1" regardless of the value of the input 4 bits (IN4B), and the AND circuit By opening 27, the 4-5 converter 26 converts the fifth
It is converted to the record value (OUT5B) shown in the figure and output as is. During self-diagnosis, the instruction OD from the microprocessor 10 is "1", so only when the first 3 bits of the input 4 bits (IN4B) are "0", it is inverted to "1" by the inverter 28, and the NAND circuit 29 The output becomes "0" and the AND circuit 27 is closed. By this, 4-
Regardless of the output conversion value of the 5 conversion unit 26, the output (OUT5B) is all "0".

Note that if the conventional 4-5 converter 26 is implemented with a P-ROM, there is no need to add a logic circuit as shown in FIG. 4, and the value corresponding to "0001" in the P-ROM is simply changed to "00000 ” Just set it to ”.

In this way, during self-diagnosis, when the data of the track containing the pseudo fault passes through the error detection/correction circuit 9 and is stored again in the channel buffer 16, the data written by the diagnostic program of the microprocessor 10 and the The data is compared with the stored data, and if they match, it can be determined that the functions of the 5-4 conversion circuit 8 and the error detection/correction circuit 9 are normal. That is, the 6250RPI check characters include an ECC character, an Auxiliary CRC character, and a CRC character. Of these, the ECC character is created using the last bit of each data group (the fourth track is excluded because it is a parity bit), and the error correction circuit 9 uses this ECC character, the parity of each character, and each Simultaneous error correction of two tracks is performed using the track error pointer. Therefore, when the 5-4 conversion circuit 8 inputs an undefined pattern and converts it into data "0000" and reports it to the error detection/correction circuit 9, the correction circuit 9 detects the error track "0000". Due to an error, correct the bit to “0001” and set the channel buffer to 16.
Therefore, when the comparison results in a match, both circuits 8 and 9 will operate normally. On the other hand, when the 5-4 conversion circuit 8 is abnormal, even if an undefined pattern is input, it is converted into some data and output. If there is only one error track, it will still be corrected, so no failure will be detected, but if an error occurs in two tracks in the same way, it will not be possible to correct it because no information that an undefined pattern has been input will be obtained. It is stored in the channel buffer 16 without being corrected to the correct bit "0001".

Further, even if the 5-4 conversion circuit 8 normally outputs "0000", if the error detection/correction circuit 9 operates abnormally, the bit will not be corrected to the correct bit "0001". If correction is not possible, it is of course possible to display the error externally.

In this way, when the data stored again in the channel buffer 16 and the data stored for the first time do not match, either one or both of the 5-4 conversion circuit 8 or the error detection/correction circuit 9 may fail or malfunction. That means you did it.

In addition, in the magnetic tape control device shown in FIG.
Normally, when a command or write data is sent from a channel CH, the selector 15 is selected to the channel CH side and the data is stored in the channel buffer 16. Further, the data read from the magnetic tape passes through the 5-4 conversion circuit 8 and the error detection/correction circuit 9, and by selecting the selector 15 to the error detection/correction circuit 9 side, the data is bypassed and sent to the channel buffer 16. Once stored, the channel
Sent to CH.

Conventionally, a pseudo failure was generated by externally synchronizing the data flow under program control of the microprocessor 10, whereas in the present invention, a pseudo pattern is generated in data under program control. After the pattern is stored in the channel buffer 16 and before it is sequentially read out, a diagnostic operation start instruction (OD) is sent via the instruction line 24, so a pseudo failure occurs without synchronization. can do.

〔Effect of the invention〕

As explained above, according to the present invention, a pseudo failure is generated at any point in a series of data without synchronizing with the data flow, and a code conversion circuit and an error detection/correction circuit are diagnosed. This can be easily realized by using a P-ROM or the like as a code conversion circuit.

In the embodiment, a case where the present invention is applied to a magnetic tape control device has been described, but it is also applicable to a main memory control device, other external memory control devices, communication systems, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional magnetic tape control device, FIG. 2 is a partially modified block diagram of FIG. 1, and FIG. 3 is a block diagram of a magnetic tape control device showing an embodiment of the present invention. FIG. 4 is a specific configuration diagram of the code conversion circuit shown in FIG. 3, and FIG. 5 is a diagram showing an example of code conversion using the GCR method. 1: ECC generation circuit, 4: Modulation circuit, 7: Demodulation circuit, 8: 5-4 conversion circuit, 9: Error detection/correction circuit, 10: Microprocessor, 13: Memory, 2, 12, 14, 15: Selector, 16: Channel buffer, 17: ECC addition circuit, 3,
23: 4-5 conversion circuit, 26: conversion section.

Claims (1)

[Claims] 1. In a device that converts and outputs ECC-added data and performs code inverse conversion of input data to detect and correct errors, only when an external instruction is received. A code conversion circuit that converts into an undefined code pattern and outputs it, and a circuit that returns the above output to the input side of the code inversion conversion are provided to diagnose the normal operation of the code inversion circuit and the error detection/correction circuit. A diagnostic method characterized by 2. The diagnostic method according to claim 1, wherein the code conversion circuit is constructed of a P-ROM.