JPS59139459A - Diagnostic system of logical unit - Google Patents

Abstract

PURPOSE:To simplify a diagnostic procedure and shorten the time required for diagnosis by writing diagnostic data in shift buses as they are. CONSTITUTION:When diagnosis is performed, stored data are read out from an external memory 13 and these data are written in shift buses 30 and 40 as they are. Then, a clock is set forward, the contents of the shift bus 30 are read out, and the values of memory elements 33 and 35 are verified. In diagnosis of a diagnosed device 20, writing twice in each of shift buses 30 and 40 is enough by setting of diagnostic data for combination of diagnosed circuits 24, 26 and 28 and combination of diagnosed circuits 25 and 27. In reading of the contents of shift buses, it is enough to read out the result of diagnosis of combination of diagnosed circuits 24, 26 and 28 and combination of diagnosed circuits 25 and 27 twice for the shift bus 30, and read out the result of diagnosis of combination of diagnosed circuits 24, 26 and 28 once for the shift bus 40.

Description

[Detailed description of the invention] Technical field to which the invention belongs The invention relates to a diagnostic method for logical devices.

BACKGROUND OF THE INVENTION Recent logic devices are equipped with a full set of check circuits that detect failures when they occur, so that they do not continue processing with erroneous data due to failures and disrupt services.

^4 Referring to FIG. 1, the check circuit 2 determines whether the parity bits of the preceding and succeeding registers are correct. The output of the check circuit 2 is provided to a failure detection and notification mechanism (not shown) K via a flip-flop or the like called an error indicator flag (hereinafter referred to as EIF). The check circuit 21 needs to operate correctly in terms of its function, and its diagnosis is indispensable.

In conventional check circuit diagnosis, diagnostic data is set in the input register for each check circuit via a shift path, the check circuit is operated by clock increments, and the contents of the shift path including its output EIFi are read out. , it is determined whether the EIFO value has been set correctly.

However, the input registers are not necessarily consecutive on the shift path due to implementation and performance reasons. For this reason, in the diagnostic data setting operation, the contents of all shift paths including the VillaTrader that make up the register are read out for each input register of the circuit to be diagnosed, and only the bits corresponding to the register VtJR among the contents are read out for each input register of the circuit to be diagnosed. changed to data.

Furthermore, there are disadvantages in that the shift pass requires complicated processing such as writing and returning pages, which is tedious and takes a lot of time.

Furthermore, since one shift path +C includes the input registers of multiple check circuits, diagnostic data settings for different input registers (also for C, it is difficult to read and write back the contents of the same shift path many times). is required,
The drawback is that diagnosis requires a huge amount of time.

An object of the present invention is to provide a diagnostic method for a logic device that eliminates the above-mentioned disadvantages that it takes time and effort to set the diagnostic data, and the disadvantage that the diagnosis time is enormous due to the setting operation being performed many times in one shift pass. Our goal is to provide the following.

Structure of the Invention The diagnosis method for a logic device according to the present invention includes a plurality of parts to be diagnosed consisting of combinational circuits, an input storage part for storing values to be input to the parts to be diagnosed at the time of diagnosis, and an output storage part to serve as an output. , a shift path section which connects the input storage section and the output storage section in a chain and is divided into one or more parts to serve as a shift register at the time of diagnosis; and a clock which fully increments the clock of the section to be diagnosed. a stepper section, an input storage section VCG of the section to be diagnosed; a storage section for storing regular diagnostic data; and a shift section that operates in correspondence with each section to be diagnosed and has all the input storage sections of the section to be diagnosed. A diagnostic data setting section that reads the contents of the path section, rewrites only the portion corresponding to the input storage section of the diagnosed section, and writes it back to the shift path section; a determination unit that reads out the contents of the shift nozzle having an output storage unit and determines whether the value of the corresponding output storage unit matches a relative value; The contents of the diagnostic data setting section corresponding to the plurality of sections to be diagnosed are operated sequentially, and the contents of the output storage section are exclusive, and all the contents of the output storage section can be observed at the same clock step number, and at least all related a diagnostic data generation section that reads out the contents of a shift path section of and stores it in the storage means, and at the time of diagnosis, outputs diagnostic data km from the storage section, writes it to the same shift path section as the diagnostic data generation section, and increments a clock. The method further includes a diagnosis execution unit that sequentially determines the normality of the diagnosed unit in the determination unit.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 2, one embodiment of the present invention includes a diagnosis execution unit 11, a local storage 12 connected to the diagnosis execution unit 11,
A diagnostic processing device 10 having an external storage 13 and a diagnostic control unit 14, a diagnostic interface unit 21, a clock control unit 22 connected to the diagnostic interface unit 21, a shift path control unit 23, circuits to be diagnosed 24-28. A device to be diagnosed 20 that is connected to the circuits to be diagnosed 24 to 28 and has memory elements 31 to 36 and 41 to 46 that serve as input and output thereof.
including. The memory elements 31-36 are the circuits to be diagnosed 24-
Connect in a chain with a connection different from the connection between 1 and 28.
A shift path 30 is formed that operates as one shift register. The memory elements 41 to 46 are also the memory element 31.
36 are connected in a chain to form a shift path 40 that operates as one shift register. Further, the shift path 30 and the shift path 40 are connected to the shift path control section 23. The diagnostic control section 14 is connected to a diagnostic interface section 21 .

The diagnosis execution section 11 gives a command to the diagnosis control section 14 to operate the clock control section 22't- through all the diagnosis interface sections 21, so that the clocks of the circuits to be diagnosed 24 to 28 can all be clocked at an arbitrary clock increment number. only step forward. At the same time, the diagnosis execution section operates the shift path control section 23, selects either the shift path 30 or the shift path 40, shifts the selected shift path, reads out the value of the shift hash into the local memory 12, and selects either the shift path 30 or the shift path 40. 1
It is possible to write any data within 2 to the 'tE shift path.

Before explaining the diagnosis method according to the present invention, a conventional diagnosis method will be explained. When diagnosing the device to be diagnosed 20 using the conventional diagnosis method, first, the contents of the shift path 30 to which the memory string 31, which is a part of the input register of the circuit to be diagnosed 24, belongs are read to the local memory 12, and among the read data, memory cord 3
The portion corresponding to 1 is replaced with diagnostic data and written back in shift pass 3 (1).Next, the read operation of shift pass 40, data Diagnostic data is set in the procedure of change operation and write back operation, and the clock is advanced by the clock control unit 22.Next, the shift paths 30 and 40 to which the memory elements 34 and 46 that form all the output registers of the circuit to be diagnosed 24 belong, respectively, are set. The contents of the circuit 24 to be diagnosed are read out and the value thereof is examined to diagnose the circuit to be diagnosed 24. Similarly, the circuits to be diagnosed 25 to 28 are successively diagnosed one circuit at a time using VC.

By the way, referring to FIG. 2, the memory string 34 serves as an output of the circuit to be diagnosed 24 and also serves as an input to the circuit to be diagnosed 27.
and the circuit to be diagnosed 27. On the other hand, there is no shared storage element of VC between the circuit to be diagnosed 25 and the circuit to be diagnosed 27, and the circuit to be diagnosed 25 and the circuit to be diagnosed 27 are independent from each other. Here, it is assumed that the circuit to be diagnosed 25 and the circuit to be diagnosed 27 are set in the memory element 33 and the memory element 35 with the same clock step number and the operation results thereof as the respective outputs. First, diagnostic data is set in the memory elements 31 and 42, which serve as inputs to the circuit to be diagnosed 25, by the same shift pass operation as in the prior art. Furthermore, the memory elements 34 and 45Vc, which are the inputs of the circuit to be diagnosed 27, are similarly set with diagnostic data, and then the clocks are advanced, and the outputs of the memory element 33 and the circuit to be diagnosed 27, which are the outputs of the circuit to be diagnosed 25, are set. The contents of the shift path 3o including the memory search element 35 are local memory 1
2+C is read. After this, memory strings 33 and 35
By examining the value of , the circuit to be diagnosed 25 and the circuit to be diagnosed 27 can be diagnosed at the same time.

In the diagnostic method according to the present invention, diagnostic data is set in all input storage elements of the plurality of mutually independent circuits to be diagnosed by utilizing the principle that VC diagnosis can be performed simultaneously for mutually independent circuits to be diagnosed. The contents of all related shift paths are read from the state in which the

The read data is stored in an external storage in advance, and the stored data is used for subsequent diagnosis. In other words, in the circuits 25 and 27 to be diagnosed which are independent of each other in FIG.
A process is executed in advance in which the diagnostic data is set in the shift lot 13, the contents of the shift boxes 30 and 40 are read in that state, and the read data is further stored in the external storage 13. From then on,
When performing diagnosis, the stored data is read from the external storage 13, and the read data is directly transmitted to the site path 3.
Written to 0 and 40. The clock is then advanced, the contents of shift path 30 are read, and the values of storage elements 33 and 35 are examined. For circuits to be diagnosed other than circuits to be diagnosed 25 and 27 in Figure 2, ¥'i, circuit to be diagnosed 2
4. There is no memory element shared with each other in 26 and 28,
It is independent. The operation results of the circuits to be diagnosed 24, 26 and 28 are stored in the memory elements 34, 36, 44 at the same clock step number.
and 46, the circuit to be diagnosed 24°2
6 and 28 may be diagnosed in the same manner as the circuits to be diagnosed 25 and 27. In the end, in diagnosing the device to be diagnosed 20, setting diagnostic data for the combination of the circuits to be diagnosed 24, 26 and 28 and the combination of the circuits to be diagnosed 25 and 270 requires only two writes to each of the shift paths 30 and 40. . In addition, in the read operation of the contents of the shift path, the read operation of the diagnosis results of the combination of the circuits to be diagnosed 24, 26 and 28 and the combination of the circuits to be diagnosed 25 and 27 is performed using the shift path 30V.
It is only necessary to perform the reading operation of the diagnostic results of the combination of the circuits to be diagnosed 24, 26 and 28 once for the shift path 40, twice in total for the circuits 24, 26 and 28 for the shift path 40. Furthermore, there is no need to replace part of the shift path data that has been read once with the diagnostic data. The simplification of the processing described above results in a reduction in the time required for direct diagnosis.

Effects of the Invention An advantage of the invention is to prepare an external storage VC for diagnostic data regarding a plurality of circuits to be diagnosed that can be independently and simultaneously diagnosed. This has the effect of simplifying the procedure and shortening the diagnostic time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the entire configuration of a general check circuit of a logic device, and FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 1 and FIG. 2, 1... register, 2
...Parity check circuit, 3...Error indicator flag (EIF), 10...
...Diagnosis processing device% 11...Diagnosis execution unit, 12...Local storage, 13...External storage, 14...Mark/diagnosis control unit, 20... ...Diagnosed device, 21...Diagnosis interface section, 22.
...Clock control section, 23... Mountain, shift path control section, 24-28... Mark, circuit to be diagnosed, 30...
・Schiff) Pass, 31-36... Memory element % 4
0... River shift path, 41-46... Memory element.

Claims (1)

[Scope of Claims] A plurality of parts to be diagnosed consisting of combinational circuits, an input storage part that stores values input to the parts to be diagnosed during diagnosis, and an output storage part to store values output from the parts to be diagnosed. and. a shift path section formed to connect the input storage section and the output storage section in a chain to form a shift register during diagnosis; a clock increment section that advances the clock of the section to be diagnosed; A storage section that stores diagnostic data to be set in an input storage section of the diagnosis section, and a storage section that operates in correspondence with each of the sections to be diagnosed and has an input storage section for the section to be diagnosed. a section setting section corresponding to the input storage section of the section; and a shift bus section that operates in correspondence with each of the sections to be diagnosed and has an output storage section of the section to be diagnosed, and reads out the contents of the corresponding output storage section. a determination unit that determines whether the value matches an expected value; and a determination unit that determines whether the contents of the input storage unit and the output storage unit are exclusive when creating diagnostic data, and that all contents of the output storage unit can be observed at the same clock step number. a diagnostic data generating section that sequentially operates the contents of the diagnostic data setting section corresponding to the plurality of sections to be diagnosed, reads out the contents of the related shift bus section, and stores it in the storage section; 1. A diagnostic method comprising: a diagnosis execution unit that reads out data and causes the determination unit to sequentially determine the normality of the part to be diagnosed.