200915330 九、發明說明： 【發明所屬之技術領域】 本發明概略關於處理系統記憶體子系統，尤指一種使 用一記憶體模組的診斷方法，其提供可程式化功能性來觀 察及/或改變記憶體模組行為，以及一種診斷記憶體模組， 其提供可程式化功能性來觀察及/或改變記憶體模組行為。 【先前技術】 在現今的電腦系統中的記憶體子系統包括提供系統記 憶體的多個記憶體模組。於設計及製造這些電腦系統及其 元件期間，例如處理器刀鋒單元或主機板，特別是專屬的 記憶體控制單元及加入有一記憶體控制單元的處理器，其 需要評估像是錯誤偵測及錯誤修正的特徵，以及記憶體效 能的設計餘裕，例如讀取循環延遲及寫入循環時序餘裕。 但是，一實際記憶體裝置的效能基本上被設計所固 定，因此測試該錯誤偵測/修正機制的技術在傳統上受限於 像是使用「已知不良」模組的方法，或是像是藉由使同位 資訊失效來迫使同位誤差之技術。軟體長久以來已可用於 執行系統記憶體測試，但是這些測試係在被設計所固定的 記憶體實施上來執行，或是在一實驗室環境中於外部來操 縱。時序餘裕已藉由改變外部負載或終端器來評估，但這 些技術相當耗時，並僅可提供該實際時序餘裕的概約評 估。再者，這些方法無法顯示出描述一記憶體模組内部之 行為的資訊，而僅顯示當被外部負載影響時該記憶體模組 5 200915330 的行為。200915330 IX. Description of the Invention: Technical Field of the Invention The present invention generally relates to a processing system memory subsystem, and more particularly to a diagnostic method using a memory module that provides programmable functionality to observe and/or change Memory module behavior, and a diagnostic memory module that provides programmable functionality to observe and/or change memory module behavior. [Prior Art] The memory subsystem in today's computer systems includes a plurality of memory modules that provide system memory. During the design and manufacture of these computer systems and their components, such as processor blade units or motherboards, in particular dedicated memory control units and processors incorporating a memory control unit, which need to be evaluated for error detection and errors. Modified features, as well as design margins for memory performance, such as read cycle delay and write cycle timing margin. However, the performance of an actual memory device is basically fixed by design, so the technique for testing the error detection/correction mechanism is traditionally limited by methods such as using a "known bad" module, or like The technique of forcing the co-location error by invalidating the parity information. Software has long been available for performing system memory tests, but these tests are performed on memory implementations that are designed to be fixed, or externally manipulated in a laboratory environment. Timing margins have been evaluated by changing external loads or terminators, but these techniques are quite time consuming and provide only a rough estimate of the actual timing margin. Furthermore, these methods do not display information describing the behavior within a memory module, but only the behavior of the memory module 5 200915330 when it is affected by an external load.
可直接插入到一標準化記憶體模组插槽中的負載裝置 已經提供了記憶體控制器及系統設計評估的某種簡化，其 中可以提供測試點，而仍可提供等效於一實際記憶體裝置 的額定負載。但是，這種測試模組基本上具有固定的信號 負載值，並僅利用被動負載及測試點來取代一記憶體裝 置，其中該被動負載近似於一實際記憶體模組的負載。為 了改變負載，該插入的負載裝置將必須被移除，而必須插 入具有不同負載特性之另一個負載裝置。所提供的測試點 亦並未位在儲存的實際位置處，其不能夠寫入及讀取，因 此僅可提供外部記憶體匯流排信號之測量。再者，使用這 種裝置於測試錯誤偵測/修正機制仍受限於像是外部載入 一測試點直到發生一錯誤為止的技術。 因此有需要提供一種方法及裝置來評估記憶體控制器 及記憶體子系統設計，藉以提供該記憶體子系統行為的彈 性化操縱，以及關於在該儲存器之實際位置處信號行為的 資訊。其另需要提供關於一記憶體模組内部之信號行為的 資訊。 【發明内容】 本發明提供一種診斷記憶體模組及測試方法，其中可 提供記憶體子系統行為的彈性操縱，以及關於在該儲存器 之實際位置處信號行為的資訊，其中包括在該記憶體模組 内部的信號行為。 6 200915330 該診斷記憶體模組包括記憶體模組介面終端，用於連 接該診斷記憶體模組到一記憶體子系統，而取代一正常的 記憶體模組，以及用於在該診斷記憶體模組與一外部診斷 系統之間通訊的介面。 該診斷記憶體模組可提供可程式化的元件，用於改變 該記憶體模組信號的行為，例如具有可程式化驅動強度的 輸出驅動器、可程式化負載電路，用於改變在該記憶體模 組介面終端處的電氣負載。該診斷記憶體模組亦可包括一 處理器核心，用於執行程式指令來執行診斷作業，而且該 等程式指令可由該外部診斷系統被下載到該處理器核心。 另外，其可提供專屬的邏輯來回應於自該介面接收的命令 而執行診斷作業。 該處理器核心或專屬邏輯可執行的作業像是改變寫入 到該診斷記憶體模組之資料流來模擬錯誤，改變位址與資 料信號之間的時序，並操縱在該診斷記憶體模組之終端上 的信號，例如在一類比域中的電源連接來造成雜訊。該診 斷記憶體模組亦可包括測試點，用於藉由外部測試設備來 提供存取到該診斷記憶體模組的信號。 前述及其它本發明之目的、特徵及好處將可由以下對 於本發明之較佳具體實施例的更為特定的說明來進行瞭 解，如所附圖式中所述。 【實施方式】 本發明關於一使用一診斷記憶體模組之測試方法，用 7A load device that can be directly inserted into a standardized memory module slot has provided some simplification of the memory controller and system design evaluation, where test points can be provided while still providing an equivalent to an actual memory device Rated load. However, such a test module basically has a fixed signal load value and replaces a memory device with only passive loads and test points, where the passive load approximates the load of an actual memory module. In order to change the load, the inserted load device will have to be removed and another load device with different load characteristics must be inserted. The test points provided are also not located at the actual location of the store, they cannot be written and read, so only the measurement of the external memory bus signal can be provided. Furthermore, the use of such a device for testing error detection/correction mechanisms is still limited by techniques such as externally loading a test point until an error occurs. It is therefore desirable to provide a method and apparatus for evaluating a memory controller and memory subsystem design to provide an elastic manipulation of the behavior of the memory subsystem and information about signal behavior at the actual location of the memory. It is also necessary to provide information about the behavior of signals within a memory module. SUMMARY OF THE INVENTION The present invention provides a diagnostic memory module and test method in which flexible manipulation of memory subsystem behavior and information about signal behavior at the actual location of the memory are included, including in the memory Signal behavior within the module. 6 200915330 The diagnostic memory module includes a memory module interface terminal for connecting the diagnostic memory module to a memory subsystem instead of a normal memory module, and for using the diagnostic memory Interface between the module and an external diagnostic system. The diagnostic memory module can provide a programmable component for changing the behavior of the memory module signal, such as an output driver having a programmable drive strength, and a programmable load circuit for changing the memory The electrical load at the interface of the module interface. The diagnostic memory module can also include a processor core for executing program instructions to perform diagnostic operations, and the program instructions can be downloaded to the processor core by the external diagnostic system. In addition, it can provide dedicated logic to perform diagnostic tasks in response to commands received from the interface. The processor core or the dedicated logic executable job is to change the data stream written to the diagnostic memory module to simulate an error, change the timing between the address and the data signal, and manipulate the diagnostic memory module. Signals on the terminals, such as power connections in an analog domain, cause noise. The diagnostic memory module can also include test points for providing signals to the diagnostic memory module by an external test device. The foregoing and other objects, features, and advantages of the invention will be apparent from the description of the preferred embodiments of the invention. [Embodiment] The present invention relates to a test method using a diagnostic memory module, and 7
200915330 於執行記憶體子系統設計之測試與評估。該記憶體 根據該系統之實體設計及可由該系統接受的記憶體 型而包裝成插入到可接受正常記憶體模組的一標準 中。在該例示性具體實施例中，根據現今通用的包 而假設為一雙進線記憶體模組（DIMM， “Dual memory module”）。但是，其可瞭解到本發明之診斷 模組可以實施成任何型式的包裝，以及用於任何記 置架構。本發明之診斷記憶體模組包括一可程式化 像是一處理器核心，其用於執行在診斷記憶體模組 種作業，例如改變該記憶體模組介面信號之負載及 係，以及改變所提供的記憶體模組之内容而影響錯 診斷記憶體模組可以包含一實施正常記憶體模組功 完整儲存陣列，也可不包含，因此該等内容可為「假 而相對於實際上儲存在一實際儲存陣列中的内容。 一寫入傳輸的内容可以儲存在一缓衝器中，經過改 後回應於一寫入作業而傳回，因此該診斷記憶體模 供或不提供由軟體所預期的實際儲存，而非用於該 憶體模組之測試程式。 本發明之診斷記憶體模組可為型別可程式化， 施該記憶體模組之一積體電路的一單一實施可以選 調整來仿真例如DDR及DDR2 DRAM模組，其對於 互連接方式有適當的改變。該選擇可以在程式控制 行/或藉由下載一診斷記憶體模組程式到該記憶體 一程式儲存器當中，或可由一硬接線選擇機制來進 模組係 模組類 連接器 裝型式 inline 記憶體 憶體裝 元件， 内的多 時序關 誤。該 能性的 設性」， 另外， 變，然 組可提 診斷記 所以實 擇性地 該實體 之下進 模組内 行，例 8 200915330 如跳接器或開關。該記憶體模組可以透過上述的下載機制 而程式化，或是該診斷程式可以永久地儲存或儲存在一可 支援重新程式化的非揮發記憶體中。該可程式化元件及診 斷程式可為一處理器核心及相關的程式指令，一專屬邏 輯，或一可程式邏輯陣列，以及相關的程式碼。 現在請參照第1圖，其例示可實施本發明的一種系 統。一工作站電腦1 0可為一個人電腦、通用工作站、或專 屬的測試電腦系統。工作站電腦系統1 0包括一圖形顯示器 1 6，用於提供視覺資訊給一使用者，並可用於監視自本發 明具體實施例接收的操作性數值，以及控制設定及下載可 執行本發明之方法的程式碼，其藉由與一目標電腦系統2 1 内一診斷記憶體模組20進行通訊來完成。一鍵盤17A及 一指向裝置1 7 B係附加至工作站電腦1 0來接收使用者輸 入。工作站電腦10包括耦合至一記憶體14之處理器12, 其中包含由處理器12執行的程式指令，其中包括根據本發 明具體實施例的程式指令，用於控制及自目標地電腦系統 2 1接收資訊。根據本發明之具體實施例的電腦程式產品包 括媒體，例如光碟片 C D，其可儲存編碼的程式指令，用 於由光碟機 15讀取，並儲存在記憶體14中由處理器12 執行。 目標電腦系統2 1係例示成刀鋒處理器單元的型式，其 可實施在一刀鋒伺服器系統當中。處理器核心2 4 A及2 4 B 係耦合於一第3層（L 3)快取單元2 6，其耦合至一記憶體控 制器單元（MCU, “Memory controller unit”）28，其可控制在 200915330200915330 Performing tests and evaluations of memory subsystem design. The memory is packaged into a standard that can be inserted into an acceptable normal memory module based on the physical design of the system and the type of memory that can be accepted by the system. In the exemplary embodiment, a dual in-line memory module (DIMM, "Dual memory module") is assumed based on the conventional package. However, it will be appreciated that the diagnostic module of the present invention can be implemented in any type of package, as well as in any recording architecture. The diagnostic memory module of the present invention includes a programmable image processor core for performing operations in a diagnostic memory module, such as changing the load and system of the memory module interface signal, and changing the location The content of the memory module provided and the error-diagnostic memory module may include a complete storage array of normal memory modules, or may not be included, so the content may be "false" and actually stored in one Actually storing the contents of the array. The content of a write transfer can be stored in a buffer and returned to respond to a write operation, so that the diagnostic memory is provided or not provided by the software. Actual storage, not the test program for the memory module. The diagnostic memory module of the present invention can be typed, and a single implementation of the integrated circuit of the memory module can be adjusted. To simulate, for example, DDR and DDR2 DRAM modules, which have appropriate changes to the interconnection method. The selection can be made in the program control line or by downloading a diagnostic memory module program to the record. In the memory module, or a hard-wired selection mechanism can be used to enter the module-type module type connector type inline memory memory component, and multiple timing errors in the device. In addition, the change group can be diagnosed so that the entity is subordinate to the module, for example, 200915330 is a jumper or switch. The memory module can be programmed by the download mechanism described above, or the diagnostic program can be permanently stored or stored in a non-volatile memory that can be reprogrammed. The programmable component and diagnostic program can be a processor core and associated program instructions, a proprietary logic, or a programmable logic array, and associated code. Referring now to Figure 1, a system in which the present invention may be implemented is illustrated. A workstation computer 10 can be a personal computer, a general purpose workstation, or a dedicated test computer system. The workstation computer system 10 includes a graphical display 16 for providing visual information to a user and for monitoring operational values received from embodiments of the present invention, as well as controlling settings and downloading methods for performing the present invention. The code is accomplished by communicating with a diagnostic memory module 20 in a target computer system 2 1 . A keyboard 17A and a pointing device 1 7 B are attached to the workstation computer 10 to receive user input. The workstation computer 10 includes a processor 12 coupled to a memory 14 including program instructions for execution by the processor 12, including program instructions in accordance with embodiments of the present invention for controlling and receiving from the target computer system 21 News. A computer program product in accordance with a particular embodiment of the present invention includes a medium, such as a CD C, that stores encoded program instructions for reading by the optical disk drive 15 and stored in the memory 14 for execution by the processor 12. The target computer system 2 1 is exemplified as a blade processor unit type that can be implemented in a blade server system. The processor cores 2 4 A and 2 4 B are coupled to a Layer 3 (L 3) cache unit 2 6 and coupled to a memory controller unit (MCU) 28, which is controllable In 200915330
一記憶體子系統與L3快取單元26之間的程式指令舆資料 的傳輸。該記憶體子系統包括四個系統記憶體之DIMM插 槽，其根據本發明一具體實施例在所例示的具體實施例中 出現有三個正常DIMMS 22及一診斷DIMM 20。工作站電 腦系統1 0之測試器介面1 8經由一介面耦合至診斷DIMM 20，像是一聯合試驗行動群組（JTAG, “Joint Test Action Group”）介面、專屬的序列介面、掃描鏈介面，或任何其它 適合在診斷DIMM 20與工作站電腦系統1 0之間傳送資料 及程式/ P G A組癌資料的通訊鍵結。測試介面1 8之間的 電氣連接可透過探針到診斷DIMM 20之電路板，其透過一 纜線到診斷DIMM 20上額外的連接器，或透過加入到一通 訊介面之額外協定，其透過正常的 DIMM連接器實施在 DIMM 20中，其可提供給DIMM電源管理及DIMM組態資 訊取得。 現在參照第2圖，診斷DIMM 20之方塊圖係根據本發 明一具體實施例來說明。一介面3 6提供上述工作站電腦系 統1 0與一處理器核心3 4之間的資料與程式鏈結（或另為專 屬或可程式化邏輯，例如一 PGA)。診斷DIMM 20包括一 連接器3 0，其透過邊緣連接器終端3 1連接至目標系統2 0， 其提供資料信號D[0:N]、位址信號Α[0:Μ]及控制信號CTL 之連接。一選擇性儲存陣列3 8提供如同一正常DIMM之 作業，並可為了特殊診斷作業而由處理器核心3 4繞過，其 將在以下更為詳細地說明。一緩衝器3 3提供來模擬資料讀 取及資料寫入作業，其可隨著與儲存器陣列3 8所執行之作 10 200915330 業效能而改變。處理器核心3 4可修改缓衝器3 3之内容來 模擬錯誤，且緩衝器33亦可包括ECC及/或同位位元，所 以錯誤指示或實際錯誤狀況可在一寫入之後設定，所以一 後續讀取作業可產生該錯誤狀況。錯誤狀況，例如整體線 失效、單一及多位元線失效及瞬變位元錯誤容易地以任何 形態產生。一可程式化缓衝器/延遲電路3 2允許處理器核 心3 4來設定該介面與缓衝器3 3之特性。緩衝器/延遲電路 3 2之讀取輸出強度可被設定配合位址信號 A [0 : M]、控制 信號CTL及/或資料信號D[0:N]之延遲，所以位址、資料 與控制信號之間的早期/晚期時序關係可被探索來評估設 計及作業系統來找出缺點或邊界線時序條件，以決定時序 餘裕。 一可程式化負載/終端器電路3 5提供匯流排負載、時 序及電壓特性之變化，其係由處理器核心34藉由可程式地 調整Α[0:Μ]、控制信號CTL及/或資料信號D[0:N]之匯流 排終端/負載特性。一雜訊產生器電路3 7，其可為一類比 電路，例如透過一電阻耦合到連接器3 0上一或多個信號之 類比到數位轉換器（ADC, “Analog-to-digital converter”）， 或是一數位切換的電路，其可影響在該類比域中連接器3 0 上的信號，其藉由放出雜訊來提供記憶體子系統中的雜訊 效果之模擬。例如，雜訊產生器電路3 7可對連接器3 0之 電源供應連接器V D D放出雜訊，且該雜訊的大小/特性可 被改變來觀察診斷第1圖之DIMM 20或正常DIMMS 22之 效能上的影響。 11 200915330 現在請參照第3圖，所示為根據本發明一具體實施例 之可程式化邏輯/終端器電路35之細節。一暫存器41接收 一來自處理器核心34之數值，並控制一組電晶體Νι_Ν4， 其可選擇地耦合任何終端電阻R1及R2的組合，其連接至 終端電壓源VI及V2，分別到像是終端τ的連接器3〇之 信號。負載電容器01及C2亦可選擇地耦合至連接器W 之信號，以改變該電容負載。 現在請參照第4圖，所示為根據本發明一具體實施例 之可程式化緩衝器/延遲電路32之細節。—暫存器Ο接收 -數值來設定由電晶體N10及P10所實施之三態反相琴的 驅動強度’其藉由電UPU_P14M至電源供應軌卿 及藉由電晶® mu_N14 @合至接地。電晶體ρι卜pi4及電 晶體Nil-N14之閘極為根據在暫存器 中設定的數值而 可選擇性地以組合方式致能，藉以改變由電晶體ni〇及 P10所實施的三態反相器之源電阻，其可改變由該相對應 輸出信號提供的跳越率/延遲時間到終端τ。可程式化緩衝 ί: 器/延遲科32亦提供在終端T處接收的一輸入信號之可 程式化輸入延遲’其係藉由使用一多工毋， 夕工盗43選擇由反相器 U_16形成的-延遲鏈的-分接點，其具有由暫存器”提 供的位元所控制的一選擇。 上述具體實施例提供可程式化匯流排線負載、延遲及 資料操縱，其可模擬-寬廣範圍的操作及錯誤條件。多種 程式可被下載到處理器核心34’並用於執行測試樣式，发 可驗證及診斷在記憶體子系統設計中的錯帛。上述具體實 12 200915330 施例亦可提供能力來在電源供應及/或匯流排線上產 訊，以聚集操作條件來測試記憶體子系統設計的穩固， 當本發明已經參照其較佳具體實施例進行特定的 及描述之後，本技藝專業人士將可瞭解到可在其中進 式及細節上的多種變化，而其皆不#離本發明的精神 疇。 【圖式簡單說明】 在附屬申請專利範圍中提供本發明之創新特徵所 的特性。但是本發明本身以及較佳的使用模式，以及 目的及好處，將可藉由參照以下一例示性具體實施例 細說明並配合附屬圖面閱讀時可得到最佳的瞭解，其 似的參考編號代表類似的成分，以及： 第1圖為安裝有根據本發明一具體實施例的一診 憶體模組，並耦合至一工作站測試系統之電腦系統的 圖。 第2圖為根據本發明一具體實施例之診斷記憶體 之方塊圖。 第3圖為詳細描述根據本發明一具體實施例中第 之可程式化負載/終端器35之示意圖。 第4圖為詳細描述根據本發明一具體實施例中第 之可程式化缓衝器/延遲32之示意圖。 【主要元件符號說明】 生雜 J·生。 顯示 行型 及範 認為 其它 的詳 中類 斷記 方塊 模組 2圖 2圖 13 200915330The transfer of program instructions and data between a memory subsystem and the L3 cache unit 26. The memory subsystem includes four DIMM slots for system memory, which in the illustrated embodiment exhibit three normal DIMMs 22 and a diagnostic DIMM 20 in accordance with an embodiment of the present invention. The tester interface 1 of the workstation computer system 10 is coupled via an interface to the diagnostic DIMM 20, such as a Joint Test Action Group (JTAG, "Joint Test Action Group") interface, a proprietary sequence interface, a scan chain interface, or Any other communication link suitable for transferring data and program/PGA group cancer data between the diagnostic DIMM 20 and the workstation computer system 10. The electrical connection between the test interfaces 18 can pass through the probe to the circuit board of the diagnostic DIMM 20, through a cable to the additional connector on the diagnostic DIMM 20, or through an additional agreement added to a communication interface, through normal The DIMM connector is implemented in DIMM 20, which provides DIMM power management and DIMM configuration information acquisition. Referring now to Figure 2, a block diagram of a diagnostic DIMM 20 is illustrated in accordance with an embodiment of the present invention. An interface 36 provides a data and program link (or another proprietary or programmable logic, such as a PGA) between the workstation computer system 10 and a processor core 34. The diagnostic DIMM 20 includes a connector 30 that is coupled to the target system 20 through an edge connector terminal 31, which provides a data signal D[0:N], an address signal Α[0:Μ], and a control signal CTL. connection. A selective storage array 38 provides operation as the same normal DIMM and can be bypassed by the processor core 34 for special diagnostic operations, as will be explained in more detail below. A buffer 3 3 is provided for analog data reading and data writing operations, which may vary with the performance of the memory array 38. The processor core 34 can modify the contents of the buffer 3 3 to simulate an error, and the buffer 33 can also include ECC and/or co-located bits, so an error indication or an actual error condition can be set after a write, so one Subsequent read jobs can produce this error condition. Error conditions such as overall line failure, single and multi-bit line failure, and transient bit errors are easily generated in any form. A programmable buffer/delay circuit 32 allows the processor core 34 to set the characteristics of the interface to the buffer 33. The read output strength of the buffer/delay circuit 32 can be set to match the delay of the address signal A [0: M], the control signal CTL and/or the data signal D[0:N], so the address, data and control Early/late timing relationships between signals can be explored to evaluate design and operating systems to identify shortcomings or boundary line timing conditions to determine timing margins. A programmable load/terminator circuit 35 provides for changes in bus load, timing, and voltage characteristics by processor core 34 by programmably adjusting Α[0:Μ], control signal CTL, and/or data. Bus terminal/load characteristics of signal D[0:N]. A noise generator circuit 317 can be an analog circuit, for example, analog to digital converter (ADC, "Analog-to-digital converter") through a resistor coupled to one or more signals on the connector 30. , or a digitally switched circuit that affects the signal on connector 30 in the analog domain by providing noise to provide a simulation of the noise effects in the memory subsystem. For example, the noise generator circuit 37 can release noise to the power supply connector VDD of the connector 30, and the size/characteristic of the noise can be changed to observe the diagnosis of the DIMM 20 or the normal DIMMS 22 of FIG. The impact on performance. 11 200915330 Referring now to Figure 3, there is shown details of a programmable logic/terminator circuit 35 in accordance with an embodiment of the present invention. A register 41 receives a value from the processor core 34 and controls a set of transistors Νι_Ν4, which are optionally coupled to any combination of termination resistors R1 and R2, which are coupled to terminal voltage sources VI and V2, respectively to the image It is the signal of the connector 3 of the terminal τ. Load capacitors 01 and C2 are also selectively coupled to the signal of connector W to change the capacitive load. Referring now to Figure 4, there is shown detail of a programmable buffer/delay circuit 32 in accordance with an embodiment of the present invention. —Scratchpad Ο Receive - The value is used to set the drive strength of the three-state phase piano implemented by transistors N10 and P10' which is connected to ground by the electrical UPU_P14M to the power supply rail and by the transistor @ mu_N14 @. The gates of the transistor ρι pi4 and the transistor Nil-N14 are selectively enabled in combination according to the values set in the register, thereby changing the three-state inversion implemented by the transistors ni〇 and P10. The source resistance of the device, which can change the skip rate/delay time provided by the corresponding output signal to the terminal τ. The programmable buffer ί: / delay section 32 also provides a programmable input delay of an input signal received at the terminal T 'by using a multiplex, the thief 43 is selected by the inverter U_16 - Delay chain - tap point, which has a choice controlled by the bit provided by the register. The above specific embodiment provides programmable bus line load, delay and data manipulation, which can be simulated - wide Scope of operation and error conditions. A variety of programs can be downloaded to the processor core 34' and used to perform test patterns, verifying and diagnosing errors in the memory subsystem design. The above example can also be provided. Ability to test the power supply and/or bus line to test the stability of the memory subsystem design with aggregate operating conditions, and the skilled artisan after the invention has been specifically described and described with reference to preferred embodiments thereof It will be appreciated that various changes can be made in the form and details, and none of them are in the spirit of the invention. [Simplified description of the drawings] The features of the innovative features of the present invention, but the present invention as well as the preferred mode of use, as well as the objects and advantages, will be best understood by reference to the following exemplary embodiments and the accompanying drawings. The reference numbers refer to like components, and: FIG. 1 is a diagram of a computer system with a diagnostic memory module mounted to a workstation test system in accordance with an embodiment of the present invention. 2 is a block diagram of a diagnostic memory in accordance with an embodiment of the present invention. Fig. 3 is a block diagram showing in detail a first programmable load/terminator 35 in accordance with an embodiment of the present invention. A schematic diagram of the first programmable buffer/delay 32 in accordance with an embodiment of the present invention is described. [Explanation of main component symbols] Synchronous J·sheng. Display line type and norm consider other detailed class break block mode Group 2 Figure 2 Figure 13 200915330
10 工作站 電腦 28 記 憶 體 控 制 器 單元 12 處理器 30 連 接 器 14 記憶體 3 1 邊 緣 連 接 器 終 端 15 光碟機 32 緩 衝 器 /延遲電路 16 圖形顯 示器 33 缓 衝 器 1 7A鍵盤 34 處 理 器 核 心 17B滑鼠 35 可 程 式 化 負 載 /終端器 18 測試益 介面 36 介 面 20 診斷雙進線記憶 體模組 37 雜 訊 產 生 器 21 目標系 統 38 選 擇 性 儲 存 陣 列 22 雙進線 記憶體 模組 41 暫 存 器 24A處理 器核心 42 暫 存 器 24B處理； 器核心 43 多 工 器10 workstation computer 28 memory controller unit 12 processor 30 connector 14 memory 3 1 edge connector terminal 15 optical disk drive 32 buffer / delay circuit 16 graphic display 33 buffer 1 7A keyboard 34 processor core 17B mouse 35 Programmable Load/Terminal 18 Test Benefit Interface 36 Interface 20 Diagnostic Dual Input Memory Module 37 Noise Generator 21 Target System 38 Selective Memory Array 22 Dual Input Memory Module 41 Register 24A Processing Core 42 register 24B processing; core 43 multiplexer